BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view schematically showing the configuration of a semiconductor device according to a first embodiment of the present invention.
FIGS. 2A to 2E are cross-sectional views schematically showing process steps of a method for fabricating a semiconductor device according to the first embodiment.
FIGS. 3A to 3E are cross-sectional views schematically showing the process steps of the method for fabricating a semiconductor device according to the first embodiment.
FIGS. 4A to 4D are cross-sectional views schematically showing process steps of a method for fabricating a semiconductor device according to a second embodiment of the present invention.
FIGS. 5A to 5B are cross-sectional views schematically showing process steps of the method for fabricating a semiconductor device according to the second embodiment.
FIGS. 6A to 6D are cross-sectional views schematically showing process steps of the method for fabricating a semiconductor device according to the second embodiment.
FIGS. 7A to 7B are cross-sectional views schematically showing process steps of the method for fabricating a semiconductor device according to the second embodiment.
FIGS. 8A to 8E are cross-sectional views schematically showing process steps of a method for fabricating a semiconductor device according to a third embodiment of the present invention.
FIGS. 9A to 9B are cross-sectional views schematically showing process steps of the method for fabricating a semiconductor device according to the third embodiment.
FIGS. 10A to 10E are cross-sectional views schematically showing process steps of the method for fabricating a semiconductor device according to the third embodiment.
FIGS. 11A to 11B are cross-sectional views schematically showing process steps of the method for fabricating a semiconductor device according to the third embodiment.
FIG. 12 is a plan view schematically showing the configuration of a known semiconductor device.
FIGS. 13A to 13E are cross-sectional views schematically showing process steps of a known method for fabricating a semiconductor device.
FIGS. 14A to 14E are cross-sectional views schematically showing the process steps of the known method for fabricating a semiconductor device.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
A description is given below of embodiments of the present invention with reference to the drawings. For simplicity of explanation, elements with substantially the same functions are identified by the same reference numerals. Note that the present invention is not limited to the following embodiments.
Embodiment 1
FIG. 1 is a plan view schematically showing the configuration of a semiconductor device according to a first embodiment of the present invention. As shown in the figure, a dual gate electrode 20 is formed across the top of a first element region 10A having an N-type MIS transistor formed therein and the top of a second element region 10B having a P-type MIS transistor formed therein.
FIGS. 2A to 2E and FIGS. 3A to 3E are cross-sectional views schematically showing process steps of a method for fabricating a semiconductor device according to this embodiment, wherein FIGS. 2A to 2E are cross-sectional views taken along the line II-II of FIG. 1 and showing process steps when viewed in a direction of the gate width and FIGS. 3A to 3E are cross-sectional views taken along the line IIIa-IIIa and the line IIIb-IIIb of FIG. 1 and showing the process steps when viewed in a direction of the gate length.
The following description is given of the method for fabricating a semiconductor device according to this embodiment with reference to FIGS. 2A to 2E and FIGS. 3A to 3E.
First, as shown in FIGS. 2A and 3A, an isolation region 12 is formed in a semiconductor substrate 11 of silicon by STI to isolate an N-type MIS transistor forming region A (hereinafter, referred to as a region A) from a P-type MIS transistor forming region B (hereinafter, referred to as a region B). Thereafter, a 2 to 4 nm thick gate insulating film 13 made of silicon dioxide or a hafnium oxide is formed on the semiconductor substrate 11 and a 100 nm thick polycrystalline silicon film 14 and a 60 nm thick silicon dioxide film 15 are then formed in this order on the semiconductor substrate 11 (on the gate insulating film 13). Subsequently, the silicon dioxide film 15, the polycrystalline silicon film 14 and the gate insulating film 13 are sequentially etched by photolithography or RIE to pattern the polycrystalline silicon film 14 into the shape of a gate electrode.
Next, as shown in FIGS. 2B and 3B, extension regions 21 and pocket regions (not shown) are formed in both the regions A and B of the semiconductor substrate 11, sidewalls 16 are then formed on the sides of the patterned polycrystalline silicon film 14 and source/drain regions 22 are then formed in both the regions A and B. Thereafter, the semiconductor substrate 11 is thermally treated to activate impurities implanted into the semiconductor substrate 11 and the polycrystalline silicon film 14 and only the top surfaces of the source/drain regions 22 of the semiconductor substrate 11 are silicided to form silicide regions 23. Subsequently, an interlayer film 17 of silicon dioxide is deposited on the layer stack, then thinned by CMP or RIE until exposure of the silicon dioxide film 15 and then completely removed by wet etching or RIE.
Next, as shown in FIGS. 2C and 3C, a resist film 18 is formed on the polycrystalline silicon film 14 to cover the region A and expose the region B. Thereafter, the exposed portion of the polycrystalline silicon film 14 is etched about a thickness of 60 nm by RIE using the resist film 18 as a mask to thin that portion of the polycrystalline silicon film 14 on the region B down to about 40 nm.
The etching is performed under a condition where the selective etching ratio of the resist film 18 to the polycrystalline silicon film 14 is substantially 1 to 1. Thus, and since the etching progresses while gradually reducing the surface level of the resist film 18, the polycrystalline silicon film 14 after the end of the etching is formed with a stepped part having a tilted shoulder (forward tapered shoulder) as shown in FIG. 2C. The etching may be implemented by wet etching. In this case, the resist film 18 is preferably formed so that its relevant end can be offset towards the region B by about an amount of film etched away more than that by RIE.
Next, as shown in FIGS. 2D and 3D, a nickel (Ni) film 19 is then deposited with a thickness of about 70 nm on the polycrystalline silicon film 14 and the semiconductor substrate 11 is then thermally treated at about 350° C. for about 30 seconds to induce silicidation reaction between the polycrystalline silicon film 14 and the Ni film 19.
Thereafter, an unreacted part of the Ni film 19 is selectively removed and the semiconductor substrate 11 is then additionally thermally treated at about 520° C. for about 30 seconds. Thus, as shown in FIGS. 2E and 3E, a NiSi film 20A and a Ni3Si film (or Ni31Si12 film) 20B are formed on the regions A and B, respectively. The induction of the two-step silicidation reaction provides complete silicidation of the Ni film 19 on the polycrystalline silicon film 14. As a result, a fully silicided gate electrode made of the NiSi film 20A is formed on the N-type MIS transistor forming region A and a fully silicided gate electrode made of the Ni3Si film (or Ni31Si12 film) 20B is formed on the P-type MIS transistor forming region B. In this case, the first and second silicide regions 20A and 20B are formed so that the position of their interface at the bottom of their thickness can be on the isolation region 12 and near the region B and the position thereof at the top of their thickness can be directly above the isolation region 12 and near the region A or directly above the region A.
The semiconductor device obtained by the above fabrication method includes a dual gate electrode 20 lying across the tops of both of a first element region (N-type MIS transistor region) 10A and a second element region (P-type MIS transistor region) 10B formed apart from each other with the isolation region 12 interposed therebetween. The dual gate electrode 20 is composed of two silicide regions with different compositions: a first silicide region (NiSi film) 20A on the first element region 10A and a second silicide region (Ni3Si film or Ni31Si12 film) 20B on the second element region 10B. The interface between the first and second silicide regions 20A and 20B includes a tilted plane.
Specifically, the first and second silicide regions 20A and 20B are constituted by different regions formed by siliciding first and second regions of different thicknesses of the polycrystalline silicon film 14. The stepped part between the first and second regions of the polycrystalline silicon film 14 is formed to have a tilted shoulder. The position of the interface between the first and second silicide regions 20A and 20B substantially corresponds to the position of the stepped part between the first and second regions of the polycrystalline silicon film 14.
The position to form the stepped part between the first and second regions of the polycrystalline silicon film 14 is preferably determined in advance so that the interface between the first and second silicide regions 20A and 20B can be located on the isolation region 12.
According to this embodiment, since the dual gate electrode is formed to have a tilted plane between silicide films 20A and 20B of different compositions as described above, the amount of surplus metal supplied from the part of the metal film (Ni film) 19 adjoining the tilted shoulder of the stepped part of the polycrystalline silicon film 14 can be less than the amount of surplus metal supplied from the vertical shoulder of the stepped part in the known technique. As a result, the amount of offset of the interface between the silicide films 20A and 20B can be reduced to less than that in the known technique. This prevents variations in transistor characteristics due to offset of the interface and in turn provides a semiconductor device including a dual gate electrode having stable transistor characteristics even when miniaturized.
Embodiment 2
FIGS. 4A to 5B and FIGS. 6A to 7B are cross-sectional views schematically showing process steps of a method for fabricating a semiconductor device according to a second embodiment of the present invention, wherein FIGS. 4A to 5B are, like the first embodiment, cross-sectional views taken along the line II-II of FIG. 1 and showing process steps when viewed in a direction of the gate width and FIGS. 6A to 7B are cross-sectional views taken along the line IIIa-IIIa and the line IIIb-IIIb of FIG. 1 and showing process steps when viewed in a direction of the gate length.
The following description is given of the method for fabricating a semiconductor device according to this embodiment with reference to FIGS. 4A to 5B and FIGS. 6A to 7B. Out of the process steps of the fabrication method according to this embodiment, process steps common to those shown in FIGS. 2A to 2E and FIGS. 3A to 3E are not given in detail.
First, as shown in FIGS. 4A and 6A, an isolation region 12 is formed in a semiconductor substrate 11 of silicon to isolate an N-type MIS transistor forming region A (hereinafter, referred to as a region A) from a P-type MIS transistor forming region B (hereinafter, referred to as a region B). Thereafter, a gate insulating film 13 made of silicon dioxide or a hafnium oxide is formed on the semiconductor substrate 11 and a 100 nm thick polycrystalline silicon film 14 is then formed on the semiconductor substrate 11 (on the gate insulating film 13).
Next, as shown in FIGS. 4B and 6B, a resist film 18 is formed on the polycrystalline silicon film 14 to cover the region A and expose the region B. Thereafter, the exposed portion of the polycrystalline silicon film 14 is etched about a thickness of 60 nm using the resist film 18 as a mask to thin that portion of the polycrystalline silicon film 14 on the region B down to about 40 nm. The etching is performed, like the first embodiment, under a condition whereby the polycrystalline silicon film 14 after the end of the etching is formed with a stepped part having a tilted shoulder (forward tapered shoulder).
Next, as shown in FIGS. 4C and 6C, a silicon dioxide film 15 is formed with a thickness of 200 nm on the polycrystalline silicon film 14 and then planarized by CMP until it reaches a thickness of 60 nm on the region A. Thereafter, the silicon dioxide film 15, the polycrystalline silicon film 14 and the gate insulating film 13 are sequentially etched by photolithography or RIE to pattern the polycrystalline silicon film 14 into the shape of a gate electrode.
Next, as shown in FIGS. 4D and 6D, extension regions 21 and pocket regions (not shown) are formed in both the regions A and B of the semiconductor substrate 11, sidewalls 16 are then formed on the sides of the patterned polycrystalline silicon film 14 and source/drain regions 22 are then formed in both the regions A and B. Thereafter, the semiconductor substrate 11 is thermally treated to activate impurities implanted into the semiconductor substrate 11 and the polycrystalline silicon film 14 and only the top surfaces of the source/drain regions 22 of the semiconductor substrate 11 are silicided to form silicide regions 23. Subsequently, an interlayer film 17 of silicon dioxide is deposited on the layer stack, then thinned by CMP or RIE until exposure of the silicon dioxide film 15 and then completely removed by wet etching or RIE.
Next, as shown in FIGS. 5A and 7A, a Ni film 19 is deposited with a thickness of about 70 nm on the polycrystalline silicon film 14 and the semiconductor substrate 11 is thermally treated to induce silicidation reaction between the polycrystalline silicon film 14 and the Ni film 19.
Thereafter, an unreacted part of the Ni film 19 is selectively removed and the semiconductor substrate 11 is then additionally thermally treated. Thus, as shown in FIGS. 5B and 7B, a NiSi film 20A and a Ni3Si film (or Ni31Si12 film) 20B are formed on the regions A and B, respectively. Like the first embodiment, the induction of the two-step silicidation reaction provides a fully silicided gate electrode structure. In this case, the first and second silicide regions 20A and 20B are formed so that the position of their interface at the bottom of their thickness can be on the isolation region 12 and near the region B and the position thereof at the top of their thickness can be directly above the isolation region 12 and near the region A or directly above the region A.
Embodiment 3
FIGS. 8A to 9B and FIGS. 10A to 11B are cross-sectional views schematically showing process steps of a method for fabricating a semiconductor device according to a third embodiment of the present invention, wherein FIGS. 8A to 9B are, like the first embodiment, cross-sectional views taken along the line II-II of FIG. 1 and showing process steps when viewed in a direction of the gate width and FIGS. 10A to 11B are cross-sectional views taken along the line IIIa-IIIa and the line IIIb-IIIb of FIG. 1 and showing process steps when viewed in a direction of the gate length.
The following description is given of the method for fabricating a semiconductor device according to this embodiment with reference to FIGS. 8A to 9B and FIGS. 10A to 11B. Out of the process steps of the fabrication method according to this embodiment, process steps common to those shown in FIGS. 2A to 2E and FIGS. 3A to 3E are not given in detail.
First, as shown in FIGS. 8A and 10A, an isolation region 12 is formed in a semiconductor substrate 11 of silicon to isolate an N-type MIS transistor forming region A (hereinafter, referred to as a region A) from a P-type MIS transistor forming region B (hereinafter, referred to as a region B). Thereafter, a gate insulating film 13 made of silicon dioxide or a hafnium oxide is formed on the semiconductor substrate 11 and a 100 nm thick polycrystalline silicon film 14 is then formed on the semiconductor substrate 11 (on the gate insulating film 13).
Next, as shown in FIGS. 8B and 10B, a resist film 18 is formed on the polycrystalline silicon film 14 to cover the region A and expose the region B. Thereafter, the exposed portion of the polycrystalline silicon film 14 is etched about a thickness of 60 nm using the resist film 18 as a mask to thin that portion of the polycrystalline silicon film 14 on the region B down to about 40 nm. The etching is implemented by anisotropic etching, so that the polycrystalline silicon film 14 after the end of the etching is formed with a stepped part having a substantially vertical shoulder.
Next, as shown in FIGS. 8C and 10C, a silicon nitride film is deposited with a thickness of 5 to 10 nm on the layer stack and then etched to form a sidewall 30 on the shoulder (side face) of the stepped part of the polycrystalline silicon film 14.
Next, as shown in FIGS. 8D and 10D, a silicon dioxide film 15 is formed with a thickness of 200 nm on the polycrystalline silicon film 14 and then planarized by CMP until it reaches a thickness of 60 nm on the region A. Thereafter, the silicon dioxide film 15, the sidewall 30, the polycrystalline silicon film 14 and the gate insulating film 13 are sequentially etched by photolithography or RIE to pattern the polycrystalline silicon film 14 into the shape of a gate electrode.
Next, as shown in FIGS. 8E and 10E, extension regions 21 and pocket regions (not shown) are formed in both the regions A and B of the semiconductor substrate 11, sidewalls 16 are then formed on the sides of the patterned polycrystalline silicon film 14 and source/drain regions 22 are then formed in both the regions A and B. Thereafter, the semiconductor substrate 11 is thermally treated to activate impurities implanted into the semiconductor substrate 11 and the polycrystalline silicon film 14 and only the top surfaces of the source/drain regions 22 of the semiconductor substrate 11 are silicided to form silicide regions 23. Subsequently, an interlayer film 17 of silicon dioxide is deposited on the layer stack, then thinned by CMP or RIE until exposure of the silicon dioxide film 15 and then completely removed by wet etching or RIE. In this case, the etching is performed so that the sidewall 30 is left.
Next, as shown in FIGS. 9A and 11A, a Ni film 19 is deposited with a thickness of about 70 nm on the polycrystalline silicon film 14 and the semiconductor substrate 11 is thermally treated to induce silicidation reaction between the polycrystalline silicon film 14 and the Ni film 19. Thereafter, an unreacted part of the Ni film 19 is selectively removed and the semiconductor substrate 11 is then additionally thermally treated. Thus, as shown in FIGS. 9B and 11B, a NiSi film 20A and a Ni3Si film (or Ni31Si12 film) 20B are formed on the regions A and B, respectively. Like the first embodiment, the induction of the two-step silicidation reaction provides a fully silicided gate electrode structure. In this case, the first and second silicide regions 20A and 20B are formed so that the position of their interface at the bottom of their thickness can be on the isolation region 12.
The semiconductor device obtained by the above fabrication method includes a dual gate electrode 20 lying across the tops of both of a first element region (N-type MIS transistor region) 10A and a second element region (P-type MIS transistor region) 10B formed apart from each other with the isolation region 12 interposed therebetween. The dual gate electrode 20 is composed of two silicide regions with different compositions: a first silicide region (NiSi film) 20A on the first element region 10A and a second silicide region (Ni3Si film or Ni31Si12 film) 20B on the second element region 10B. A sidewall 30 made of an insulating film is formed at part of the interface between the first and second silicide regions 20A and 20B.
According to this embodiment, in inducing silicidation reaction between the polycrystalline silicon film 14 and the Ni film 19 as shown in FIG. 9A, surplus metal supplied from the Ni film 19 laterally adjoining the stepped part of the polycrystalline silicon film 14 can be blocked by the sidewall 30 formed at the shoulder of the stepped part. Thus, the amount of offset of the interface between the silicide films 20A and 20B having different compositions can be reduced, which prevents variations in transistor characteristics due to offset of the interface.
Although the present invention has been so far described with reference to the preferred embodiments, their descriptions are not restrictive but can be modified into various forms. For example, although in the above embodiments a Ni film 19 is used as a metal film, the material used for the metal film is not particularly limited so long as it reacts with the polycrystalline silicon film 14 to form a metal silicide film. Examples of such material include high-melting point metals such as Co, Ti and Pt. Furthermore, the polycrystalline silicon film 14 may contain germanium.
Patent Application
20080017927
