This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-162305, filed on Sep. 5, 2019; the entire contents of which are incorporated herein by reference.
Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof.
Semiconductor devices include a three-dimensionally stacked semiconductor storage device in which electrode layers are stacked. Production steps of such a three-dimensionally stacked semiconductor storage device include steps of forming a hole penetrating a stacked body stacked on a semiconductor substrate and performing epitaxial growth with a semiconductor material to form a contact part. After these steps, a semiconductor film containing a memory film is formed on the contact part.
Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments.
A semiconductor device according to an embodiment includes: a semiconductor substrate including a first surface, a first contact part provided at a deeper level than the first surface, and a second contact part protruding up to a higher level than the first surface from the first contact part; a stacked body in which insulating layers and electrode layers are alternately stacked on the first surface; and a semiconductor film extending, on the second contact part, in the stacked body in a first direction perpendicular to the first surface. At an interface between the first contact part and the second contact part, a length of the first contact part in a second direction parallel to the first surface is larger than a length of the second contact part in the second direction.
There are hereafter described semiconductor storage devices each having a memory cell array in a three-dimensional structure as embodiments. Such semiconductor storage devices each is a nonvolatile semiconductor storage device with which data can be electrically erased and written at random and which can hold the contents therein thus stored even after power supply is turned off.
The memory cell array 1 has the semiconductor substrate 10, a stacked body 100 provided on the semiconductor substrate 10, a plurality of semiconductor films CL, a plurality of separation parts 60, bit lines BL, and a source line SL.
Each semiconductor film CL is formed into a substantial cylinder shape extending inside the stacked body 100 in the Z-direction. The separation parts 60 spread on the semiconductor substrate 10 in the Z-direction and the X-direction, and separate the stacked body 100 into a plurality of blocks (or fingers) 200 in the Y-direction. The plurality of semiconductor films CL exemplarily make a staggered arrangement as shown in
The plurality of bit lines BL are provided above the stacked body 100. The plurality of bit lines BL extend in the Y-direction and are exemplarily metal films. The plurality of bit lines BL are separated from one another in the X-direction.
The semiconductor substrate 10 is exemplarily a silicon substrate. As shown in
The first contact parts 11 are provided at a deeper level than an upper surface 10a of the semiconductor substrate 10. Moreover, the first contact parts 11 contain boron (B). Each of the second contact parts 12 has a doped layer 12a protruding up to a higher level than the upper surface 10a from the first contact part 11, and an undoped layer 12b provided on the doped layer 12a. The doped layers 12a contain boron as well as the first contact parts 11 do. Meanwhile, the undoped layers 12b do not contain boron. A concentration of boron contained in the first contact parts 11 and the doped layers 12a is preferably within a range of 1×1017 m−3 to 5×1018 m−3.
The stacked body 100 is provided on the upper surface 10a of the semiconductor substrate 10. The stacked body 100 has a plurality of electrode layers 70. The plurality of electrode layers 70 are stacked via insulating layers 72 in the Z-direction. The individual electrode layers 70 are metal layers, for example, such as tungsten layers or molybdenum layers. Moreover, an insulating layer 41 is provided between the upper surface 10a of the semiconductor substrate 10 and the lowermost electrode layer 70.
The lowermost electrode layer 70 is positioned at a height below a lower end of the semiconductor film CL. Moreover, an insulating film 42 is provided between the lateral surface of the second contact part 12 and the lowermost electrode layer 70. The lateral surface of the second contact part 12 is covered by the lowermost insulating layer 72, the insulating film 42 and the insulating layer 41.
A distance between the lowermost electrode layer 70 and the second lowest electrode layer 70 is larger than distances between the other electrode layers 70. A thickness of the lowermost insulating layer 72 is larger than thicknesses of the other insulating layers 72.
As shown in
The semiconductor body 20 is formed into a pipe shape, and the core film 50 is provided inward of the same. The semiconductor body 20 is exemplarily an amorphous silicon film. A lower end part of the semiconductor body 20 is in contact with the second contact part 12. An upper end of the semiconductor body 20 is connected to the bit line BL via a contact Cb and a contact V1 which are shown in
The memory film 30 is provided between the electrode layers 70 above the lowermost electrode layer 70 and the semiconductor body 20, and encloses a periphery of the semiconductor body 20. The memory film 30 is a stacked film including a tunnel insulating film 31, a charge storage capacitor 32 and a block insulating film 33. The block insulating film 33, the charge storage capacitor 32 and the tunnel insulating film 31 are provided in this order from the electrode layer 70 side between the electrode layer 70 that is one layer higher than the lowermost electrode layer 70 and the semiconductor body 20. The semiconductor body 20, the memory film 30 and the electrode layer 70 constitute a memory cell MC.
The memory cell MC is exemplarily a charge trapping memory cell. The charge storage capacitor 32 has many trap sites which trap charges in the insulative film, and exemplarily includes a silicon nitride film. Otherwise, the charge storage capacitor 32 may be a floating gate with conductivity the periphery of which is enclosed by an insulator.
The tunnel insulating film 31 is a potential barrier when charges are injected into the charge storage capacitor 32 from the semiconductor body 20 or when charges stored in the charge storage capacitor 32 are released to the semiconductor body 20. The tunnel insulating film 31 exemplarily includes a silicon oxide film.
The block insulating film 33 prevents charges stored in the charge storage capacitor 32 from being released to the electrode layer 70. Moreover, the block insulating film 33 prevents back tunneling of electrons to the semiconductor film CL from the electrode layer 70. The block insulating film 33 exemplarily includes a silicon oxide film. Otherwise, as the block insulating film, a stacked film of a silicon oxide film and a metal oxide film with a higher dielectric constant than that of the silicon oxide film may be provided between the charge storage capacitor 32 and the electrode layer 70.
The memory cell MC has a vertical transistor structure in which the electrode layer 70 encloses a periphery of the semiconductor body 20 via the memory film 30. In this memory cell MC with the vertical transistor structure, the semiconductor body 20 functions as a channel, and the electrode layer 70 functions as a control gate. The charge storage capacitor 32 functions as a data storage layer which stores charges injected from the semiconductor body 20.
As shown in
Next, the separation parts 60 are described. As shown in
As shown in
The lowermost electrode layer 70 functions as a control gate of a bottom transistor, and the insulating layer 41 and the insulating film 42 shown in
Control of a potential given to the lowermost electrode layer 70 induces inversion layers (N-channels), in the vicinity of the upper surface 10a of the semiconductor substrate 10 and in the vicinity of the lateral surface of the doped layer 12a of the second contact part 12, and thus, can cause a cell current to flow between the semiconductor region 13 and the lower end of the semiconductor body 20.
Hereafter, a manufacturing method of a semiconductor device according to the present embodiment is described.
First, as shown in
Next, as shown in
Next, as shown in
Through the aforementioned anisotropic etching, a length “dr” of the bottom region MHB in the Y-direction becomes larger than the diameter “dMH” of the memory hole MH. Moreover, there is formed on the bottom region MHB a tapered surface 11a inclined such that the aforementioned length “dr” is larger as coming closer to the stacked body 100. The (111) plane of a silicon crystal is exposed on most of the tapered surface 11a. The tapered surface 11a includes (−111), (1-11) and (11-1), which are planes equivalent to (111), and the bottom region MHB has a surface shape of a quadrangular pyramid oriented downward.
Next, as shown in
Examples of conditions of the epitaxial growth include a flow rate of dichlorosilane (DCS) gas not less than 100 sccm and not more than 400 sccm, the flow rate of the hydrogen chloride gas not less than 100 sccm and not more than 250 sccm, and the pressure in the chamber not less than 1333 Pa (10 Torr) and not more than 5333 Pa (40 Torr). The flow rate of the hydrogen chloride gas in the anisotropic etching is greater than 10 times and smaller than 20 times the flow rate of the hydrogen chloride gas in the epitaxial growth. The pressure in the anisotropic etching is greater than twice and smaller than four times the pressure in the epitaxial growth. By using process conditions as above, anisotropy of etching can be made large. Moreover, the doping with boron is ended when a height of the silicon crystal reaches that of the lowermost sacrificial layer 71. As a result, the first contact part 11 having been doped with boron is formed in the bottom region MHB, and the doped layer 12a having been doped with boron is formed on the first contact part 11.
After the doping with boron is ended, the epitaxial growth of the silicon crystal is continued in the same apparatus for a predetermined time as shown in
After the second contact parts 12 are formed, as shown in
After the semiconductor films CL are formed, as shown in
Next, as shown in
Next, as shown in
After that, as shown in
After the electrode layers 70 are formed, as shown in
Subsequently to the production steps for the semiconductor device according to the present embodiment as described above, a manufacturing method of a semiconductor device according to a comparative example is described. Production steps different from those for the present embodiment mentioned above are herein described.
On the contrary, in the present embodiment, it is expected that the upper end of the second contact part 12 can have such a convex shape. Therefore, the bottom region MHB is anisotropically etched in advance before the silicon crystal is epitaxially grown in the memory hole MH. This anisotropic etching allows the length “dr” of the bottom region MHB to expand in the Y-direction relative to the diameter “dMH” of the memory hole (see
Moreover, in the present embodiment, boron is injected in the first contact part 11 and a part of the second contact part 12. The boron allows control of a threshold voltage “Vth” of a bottom transistor which is turned on and off by a voltage applied to the lowermost electrode layer 70. Therefore, variation of threshold voltages of bottom transistors can be reduced. Successively performing the anisotropic etching, and the epitaxial growth and the doping with boron in the same apparatus and the same furnace can control a spatial distribution in concentration of boron, which can reduce the variation of the threshold voltages.
Furthermore, the aforementioned regions of injecting boron are limited within the regions of forming the memory holes MH, not across the whole surface of the semiconductor substrate 10. Therefore, an electric resistance of a surface portion of the semiconductor substrate 10 out of a current path of a cell current from the semiconductor region 13 of the separation part 60 to the lower end of the semiconductor body 20 can be reduced to be as low as possible.
(Modification 1)
In a memory cell array 1a shown in
Since according to the present modification, at least the first contact part 11 is doped with boron, the variation among bottom transistors can be reduced. Furthermore, since in the present modification, the second contact part 12 is not doped with boron, a distance “dB” between a region of doping with boron (first contact part 11) and the semiconductor body 20 is larger than in the first embodiment. Therefore, an electric resistance of the second contact part 12 on the aforementioned current path of the cell current can be reduced.
(Modification 2)
In a memory cell array 1b shown in
Since according to the present modification, a region which is not doped with boron is also formed in a part of the first contact part 11, the distance “dB” between the region of the doping with boron and the semiconductor body 20 is larger than in Modification 1. Therefore, the electric resistance on the aforementioned current path of the cell current can be further reduced.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
---|---|---|---|
JP2019-162305 | Sep 2019 | JP | national |
Number | Name | Date | Kind |
---|---|---|---|
9324727 | Lee et al. | Apr 2016 | B2 |
10115730 | Baraskar et al. | Oct 2018 | B1 |
10269820 | Kaminaga | Apr 2019 | B1 |
10367000 | Fukushima et al. | Jul 2019 | B2 |
20160056169 | Lee et al. | Feb 2016 | A1 |
20170069657 | Hamanaka et al. | Mar 2017 | A1 |
20170288038 | Ishida et al. | Oct 2017 | A1 |
20180122822 | Lee et al. | May 2018 | A1 |
20180277555 | Fukushima et al. | Sep 2018 | A1 |
20190067318 | Shioda et al. | Feb 2019 | A1 |
Number | Date | Country |
---|---|---|
2017-55097 | Mar 2017 | JP |
2018-160612 | Oct 2018 | JP |
2019-41056 | Mar 2019 | JP |
Number | Date | Country | |
---|---|---|---|
20210074592 A1 | Mar 2021 | US |