Patent Application
20210384340
The present application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2020-098696 filed on Jun. 5, 2020, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.
The disclosure discussed herein relates to a semiconductor device and a method for manufacturing the semiconductor device.
Nitride semiconductors have features such as high saturated electron velocities and wide band gaps. Therefore, various studies have been conducted to apply nitride semiconductors to high-breakdown voltage and high-power semiconductor devices using these properties. Recently, techniques associated with GaN-based high electron mobility transistors (HEMTs) have been developed, for example.
According to one example of a GaN-based HEMT, GaN (gallium nitride) is used in an electron transit layer and AlGaN (aluminum gallium nitride) is used in an electron supply layer. In the electron transit layer, a high concentration of a two-dimensional electron gas (2DEG) is generated by the action of piezo polarization and spontaneous polarization in GaN. Hence, the application of GaN-based HEMTs to high-power amplifiers or high-efficiency switching devices is expected.
In the GaN-based HEMTs, it is preferable that the concentration of 2DEG differ between the source and drain electrodes. For example, to achieve both the reduction in on-resistance and the improvement in drain breakdown voltage, it is preferable to have a higher concentration of 2DEG between the gate and source electrodes than between the gate and drain electrodes.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2015-12037
[Patent Document 2] Japanese Patent Application Laid-Open No. 2004-221325
[Patent Document 3] Japanese Patent Application Laid-Open No. 2012-114242
According to an aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a semiconductor stack structure having an electron transit layer and an electron supply layer, the electron transit layer and the electron supply layer being compound semiconductors; a gate electrode, a source electrode, and a drain electrode, the gate electrode, the source electrode, and the drain electrode being deposed above the electron supply layer; a first insulating film disposed on the semiconductor stack structure between the gate electrode and the source electrode, the first insulating film being positively charged and in direct contact with the semiconductor stack structure; and a second insulating film disposed on the semiconductor stack structure between the gate electrode and the drain electrode, the second insulating film being covalent and in direct contact with the semiconductor stack structure.
The object and advantages of the embodiment will be realized and attained by means of the elements and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.
In related art HEMT structures, it appears difficult to stably improve the drain breakdown voltage while reducing on-resistance.
Thus, an object of the present disclosure is to provide a semiconductor device capable of stably improving the drain breakdown voltage while reducing the on-resistance, and a method for manufacturing such a semiconductor device.
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the present specification and the drawings, duplicated descriptions for components having substantially the same functional structures may be omitted by adding the same reference numerals.
A first embodiment will be described. The first embodiment relates to a semiconductor device including a high electron mobility transistor (HEMT).
The semiconductor device 100 according to a first embodiment has a semiconductor stack structure 106 that includes an electron transit layer 102 and an electron supply layer 104, as illustrated in
In the semiconductor device 100, a two-dimensional electron gas (2DEG) 109 is generated in the electron transit layer 102 near an interface with the electron supply layer 104. The first insulating film 121 is disposed on the semiconductor stack structure 106 between the gate electrode 130 and the source electrode 113, and is in direct contact with the semiconductor stack structure 106. The first insulating film 121 is positively charged. In contrast to this, the second insulating film 122 is disposed on the semiconductor stack structure 106 between the gate electrode 130 and the drain electrode 114, and is in direct contact with the semiconductor stack structure 106. The second insulating film 122 is a covalent insulating film. Covalent insulating films are electrically neutral because the covalent insulating films contain substantially no fixed charge. Thus, the concentration of 2DEG 109 is higher below the first insulating film 121 than below the second insulating film 122. Covalent insulating films are also thermally stable. Thus, the drain breakdown voltage can be stably improved while reducing the on-resistance and increasing the current.
Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described.
As illustrated in
The semiconductor device 100 according to the first embodiment can be manufactured in this manner.
Next, a second embodiment will be described. The second embodiment relates to a semiconductor device having a GaN-based HEMT.
The semiconductor device 200 according to the second embodiment has a semiconductor stack structure 206 formed on a substrate 201, as illustrated in
Openings 211 and 212 are formed on the capping layer 205, the source electrode 213 is formed inside the opening 211, and the drain electrode 214 is formed inside the opening 212. The first insulating film 221 and the second insulating film 222 are formed on the capping layer 205. The first and second insulating films 221 and 222 are in direct contact with the semiconductor stack structure 206. The first insulating film 221 is in contact with the source electrode 213 and extends toward the drain electrode 214. An end of the first insulating film 221 toward the drain electrode 214 is separated from the drain electrode 214. The second insulating film 222 is in contact with the drain electrode 214 and extends toward the source electrode 213. An end of the second insulating film 222 toward the source electrode 213 is separated from the source electrode 213. The end of the first insulating film 221 facing the drain electrode 214 and the end of the second insulating film 222 facing the source electrode 213 are separated from each other, and an opening 220 is provided between these ends of the first and second insulating films 221 and 222. A gate electrode 230 is provided between the source electrode 213 and the drain electrode 214 on the first and second insulating films 221 and 222, and the gate electrode 230 is in contact with the capping layer 205 through the opening 220. The first insulating film 221 may cover the side and top surfaces of the source electrode 213, and the second insulating film 222 may cover the side and top surfaces of the drain electrode 214.
The source and drain electrodes 213 and 214 are made of, for example, metal, and may include a stack of a titanium (Ti) film and an aluminum (Al) film thereon. The gate electrode 230 has a so-called T-shaped structure. The gate electrode 230 is made of, for example, metal, and may include a stack of a nickel (Ni) film and a gold (Au) film thereon.
The first insulating film 221 includes aluminum oxide. The first insulating film 221 may, for example, be an aluminum oxide film. When the composition of aluminum oxide is expressed as Alx1Oy1, the value of x1/y1 is greater than 2/3. The first insulating film 221 is a positively charged, ionic bonding film. The thickness of the first insulating film 221 may be, for example, 10 nm to 100 nm.
The second insulating film 222 is a covalent film. The second insulating film 222 may include, for example, siloxane polymers such as methylsilsesquioxane (MSQ). For example, the density of the second insulating film 222 is 1.1 g/cm3 or more, and the dielectric constant of the second insulating film 222 is 2.2 or more. The thickness of the second insulating film 222 may be, for example, 10 nm to 1000 nm.
In the semiconductor device 200, a 2DEG 209 is generated in the electron transit layer 202 near an interface with the electron supply layer 204. The first insulating film 221 is disposed on the semiconductor stack structure 206 between the gate electrode 230 and the source electrode 213, and is in direct contact with the semiconductor stack structure 206. The first insulating film 221 is positively charged. In contrast to this, the second insulating film 222 is disposed on the semiconductor stack structure 206 between the gate electrode 230 and the drain electrode 214, and is in direct contact with the semiconductor stack structure 206. The second insulating film 222 is a covalent insulating film. Covalent insulating films are electrically neutral because the covalent insulating films contain substantially no fixed charge. Thus, the concentration of the 2DEG 209 is higher below the first insulating film 221 than below the second insulating film 222. Covalent insulating films are thermally stable. Thus, the drain breakdown voltage can be stably improved while reducing the on-resistance and increasing the current.
Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described.
First, as illustrated in
In forming the semiconductor stack structure 206, for example, a mixture of trimethylaluminum (TMAl) gas, which is an Al source, trimethylgallium (TMG) gas, which is a Ga source, and ammonia (NH3) gas, which is an N source, is used. In this case, the presence or absence of the supply of trimethylaluminum gas and trimethylgallium gas and the flow rate thereof are set according to a composition of a compound semiconductor layer to be grown. The flow rate of the ammonia gas, which is a common precursor for each compound semiconductor layer, is approximately 100 ccm to 10 LM. For example, the growth pressure is approximately 50 Torr to 300 Torr, and the growth temperature is approximately 1000° C. to 1200° C. Also, when growing an n-type compound semiconductor layer (e.g., an electron supply layer 204), a SiH4 gas containing, for example, Si is added to the mixture at a predetermined flow rate to dope the compound semiconductor layer with Si. The doping concentration of Si may be, for example, from approximately 1×1018 cm−3 to 1×1020 cm−3.
Subsequently, as illustrated in
Before the formation of the openings 211 and 212, an element separation region may be formed to define an element region in the semiconductor stack structure 206. In the formation of the element separation region, for example, a photoresist pattern is formed on the capping layer 205 to expose an area in which the element separation region is to be formed, and ion implantation, such as argon (Ar) ion implantation, is performed using this photoresist pattern as a mask. The photoresist pattern may be dry etched using a chlorine-based gas as an etch mask. In the element separation region, 2DEG 209 is removed.
After forming the source electrode 213 and the drain electrode 214, as illustrated in
As illustrated in
Then, as illustrated in
As illustrated in
Subsequently, a gate electrode 230 is formed on the first and second insulating films 221 and 222 between the source and drain electrodes 213 and 214 through the opening 220, and is in contact with the capping layer 205 (see
The semiconductor device 200 according to the second embodiment can be manufactured in this manner.
The second insulating film 222 included in the semiconductor device 200 manufactured by such a method is resistant to defects and is thermally stable. Accordingly, even if various heat treatments are performed after the second insulating film 222 is formed, the second insulating film 222 is hardly affected by the heat history, and thus has a stable property.
With respect to the physical properties of the second insulating film 222 including siloxane polymers, the amount of the Si—CH3 bond in the second insulating film 222 formed through ultraviolet irradiation at a wavelength of 180 nm to 250 nm is approximately 7×10−5 nm−1 or less. If the amount of the Si—CH3 bond is approximately 7×10−5 nm−1 or less, the density of the second insulating film 222 is 1.15 g/cm3 or more, and the dielectric constant is 2.2 or more. The dielectric constant of 2.2 or more tends to mitigate electric field concentration in the vicinity of the end of the gate electrode 230 on the drain electrode 214 side. The amount of Si—CH3 bond can be specified as follows using an infrared spectrophotometer (JIR-100 manufactured by Japan Spectroscopy Co., Ltd.). That is, the transmission spectrum is measured in the dual mode (Sample/Background) with the measurement resolution of 4 cm−1, and the result is integrated 60 times. In the transmitted spectrum obtained by the integration, the value obtained by dividing the peak intensity of the Si—CH3 bond absorbing at around 1276 cm−1 by the film thickness (nm) of the sample is the amount of Si—CH3 bond.
Next, a third embodiment will be described. The third embodiment relates to a semiconductor device having a GaN-based HEMT, which differs from the second embodiment in terms of the configuration of the first insulating film.
As illustrated in
The first insulating film 321 has a third insulating film 321A and a fourth insulating film 321B on the third insulating film 321A. The third insulating film 321A includes aluminum oxide, and is, for example, an aluminum oxide film. When the composition of aluminum oxide is expressed as Alx1Oy1, the value of x1/y1 is greater than 2/3. The thickness of the third insulating film 321A is, for example, approximately 10 nm to 100 nm. The fourth insulating film 321B includes silicon nitride, and is, for example, a silicon nitride film. When the composition of silicon nitride is expressed as Six2Ny2, the value of x2/y2 is greater than 3/4. The thickness of the fourth insulating film 321B may be, for example, 10 nm to 100 nm. The fourth insulating film 321B may be thicker than the third insulating film 321A. The third and fourth insulating films 321A and 321B are positively charged, ionic bonding films, and the first insulating film 321 is also a positively charged, ionic bonding film.
Other configurations are substantially the same as those of the second embodiment.
The same effect as the second embodiment can be obtained by the third embodiment.
Next, a method for manufacturing the semiconductor device 300 according to the third embodiment will be described.
First, in the same manner as in the second embodiment, a source electrode 213 and a drain electrode 214 are formed, and a subsequent process up to the heat treatment is performed to establish the ohmic characteristics (see
Thereafter, the first insulating film 321 is fabricated, as illustrated in
Subsequently, as illustrated in
In this manner, the semiconductor device 300 according to the third embodiment can be manufactured.
When forming the first insulating film 321, an aluminum oxide film may be formed and heat treated, and then a silicon nitride film may be formed and heat treated. For example, the aluminum oxide film may be heat treated at 750° C., and the silicon nitride film may be heat treated at 850° C.
Next, a fourth embodiment will be described. The fourth embodiment relates to a semiconductor device having a GaN-based HEMT, which differs from the third embodiment in terms of the configuration of the first insulating film.
The semiconductor device 400 according to the fourth embodiment has a first insulating film 421 instead of the first insulating film 321 according to the third embodiment, as illustrated in
The first insulating film 421 has a third insulating film 421A and a fourth insulating film 321B on the third insulating film 421A. The third insulating film 421A includes aluminum oxide, and is, for example, an aluminum oxide film. When the composition of aluminum oxide is expressed as Alx1Oy1, the value of x1/y1 is greater than 2/3. The thickness of the third insulating film 421A is, for example, approximately 10 nm to 100 nm. The fourth insulating film 321B may be thicker than the third insulating film 421A. The third and fourth insulating films 421A and 321B are positively charged, ionic bonding films, and the first insulating film 421 is also a positively charged, ionic bonding film.
Unlike the third insulating film 321A in the third embodiment, an end of the third insulating film 421A facing the drain electrode 214 is in contact with an end of the second insulating film 222 facing the source electrode 213. In contrast to this, an end of the fourth insulating film 321B facing the drain electrode 214 and an end of the second insulating film 222 facing the source electrode 213 are separated from each other, and an opening 420 is provided between these ends of the fourth insulating film 321B facing the drain electrode 214 and the second insulating film 222 facing the source electrode 213. A gate electrode 230 is provided on the first and second insulating films 421 and 222 between the source electrode 213 and the drain electrode 214, and the gate electrode 230 is in contact with a top surface of the third insulating film 421A through the opening 420. The first insulating film 421 may cover the side and top surfaces of the source electrode 213.
Other configurations are the same as in the third embodiment.
The fourth embodiment can obtain the same effect as the third embodiment.
As described above, a gate structure may be of the Schottky type or of the MIS (metal-insulator-semiconductor) type.
Next, a method for manufacturing the semiconductor device 400 according to the fourth embodiment will be described.
First, in the same manner as in the second embodiment, a source electrode 213 and a drain electrode 214 are formed, and a subsequent process up to the heat treatment is performed to establish the ohmic characteristics (see
The fourth insulating film 321B is then fabricated so as to remain between the gate electrode 230 and the source electrode 213, as illustrated in
The third insulating film 421A is then fabricated so as to remain between the gate electrode 230 and the source electrode 213, and below the opening 420, as illustrated in
The fabrication of the first insulating film 421 results in a lower concentration of 2DEG 209 near the top surface of the electron transit layer 202 below the area where the first insulating film 421 is removed.
Subsequently, as illustrated in
The semiconductor device 400 according to the fourth embodiment can be manufactured in this manner.
Next, a fifth embodiment will be described. The fifth embodiment relates to a semiconductor device having a GaN-based HEMT, which differs from the second embodiment in terms of the configuration of the electron supply layer.
As illustrated in
In the fifth embodiment, since the recess 507 is formed on the top surface of the electron supply layer 204, the thickness of electron supply layer 204 is smaller in an area between the gate electrode 230 and the drain electrode 214 in plan view than an area between the gate electrode 230 and the source electrode 213 in plan view. Accordingly, the concentration of 2DEG between the gate electrode 230 and the drain electrode 214 is lower, and the drain breakdown voltage can thus be further improved.
Next, a method for manufacturing the semiconductor device 500 according to the fifth embodiment will be described.
First, the process up to the formation of the electron supply layer 204 is performed in the same manner as in the second embodiment (see
Subsequently, as illustrated in
The semiconductor device 500 according to the fifth embodiment can thus be manufactured in this manner.
Note that the electron supply layer 204 on which the recess 507 is formed may be used in the third or fourth embodiment.
The following describes an experiment performed according to the embodiments of the present application. In this experiment, three samples A, B, and C were prepared. The sample A is a sample that includes a substrate 201 and a semiconductor stack structure 206 in the second embodiment. The sample B is a sample obtained by forming a siloxane polymer film on the semiconductor stack structure 206 of the sample A. The sample C is a sample obtained by forming an aluminum oxide film on the semiconductor stack structure 206 of the sample A. In this experiment, the sample A, the sample B, and the sample C were subjected to heat treatment at 350° C. (corresponding to the heat history of the interconnect process) for 1 hour, and then the carrier density was evaluated. This result is illustrated in
As illustrated in
The first insulating film 221 may include silicon nitride, silicon oxynitride, aluminum oxide, or aluminum oxynitride, or any combination thereof. For example, the first insulating film 221 may include a first element that becomes a cation and a second element that becomes an anion, and the difference between electronegativity of the second element and electronegativity of the first element may be greater than 1.7. When the first insulating film 221 includes silicon nitride, the temperature of the heat treatment to generate the nitrogen holes is preferably 750° C. or more, more preferably 800° C. or more, and still more preferably 850° C. or more. The second insulating film 222 may be a silicon oxide or hydrocarbon film.
Note that compositions of the compound semiconductor layers included in the semiconductor stack structure are not limited to those described in the above-described embodiments. For example, nitride semiconductors such as InAlN, InGaAlN, and the like may be used. Compound semiconductors such as InP may also be used.
In addition, the sequence of steps in the manufacturing method in the present disclosure is not limited to those described in the above embodiments. For example, the insulating films may be formed prior to the source and drain electrodes.
Next, a sixth embodiment will be described. The sixth embodiment relates to a discrete package of a HEMT.
In the sixth embodiment, as illustrated in
Such a discrete package may be manufactured, for example, as follows. First, the semiconductor device 1210 is secured to the land 1233 of a lead frame using a die attach agent 1234, such as solder. Subsequently, with wire bonding using the wires 1235g, 1235d and 1235s, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source lead 1232s of the lead frame. Thereafter, sealing is performed using a mold resin 1231 by transfer mold method. The lead frame is then disconnected.
Next, a seventh embodiment will be described. The seventh embodiment relates to a PFC (Power Factor Correction) circuit having a HEMT.
The PFC circuit 1250 is provided with a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an alternating current power supply (AC) 1257. The drain electrode of the switch element 1251 is connected to an anode terminal of the diode 1252 and one terminal of the choke coil 1253. The source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of capacitor 1255. The other terminal of the capacitor 1254 is connected to the other terminal of the choke coil 1253. The other terminal of the capacitor 1255 is connected to a cathode terminal of the diode 1252. Further, a gate driver is connected to a gate electrode of the switch element 1251. An AC 1257 is connected between the terminals of the capacitor 1254 via the diode bridge 1256. A direct current (DC) is connected between the terminals of the capacitor 1255. According to the seventh embodiment, a compound semiconductor device having the same structure as any of the first to fifth embodiments is used for the switch element 1251.
In manufacturing the PFC circuit 1250, for example, a solder or the like is used to connect the switch element 1251 to the diode 1252, the choke coil 1253, or the like.
Next, an eighth embodiment will be described. An eighth embodiment relates to a power supply device having a HEMT, which is suitable for server power supply.
The power supply is provided with a high voltage primary circuit 1261, a low voltage secondary circuit 1262, and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262.
The primary circuit 1261 includes the PFC circuit 1250 according to the seventh embodiment, and an inverter circuit such as a full bridge inverter circuit 1260. The full bridge inverter circuit 1260 is connected between terminals of the capacitor 1255 of the PFC circuit 1250. The full bridge inverter circuit 1260 is provided with a plurality (four in this example) of switch elements 1264a, 1264b, 1264c, and 1264d.
The secondary circuit 1262 includes a plurality (three in this example) of switch elements 1265a, 1265b, and 1265c.
According to the eighth embodiment, a compound semiconductor device having the same structure as any of the first to fifth embodiments is used for the switch element 1251 of the PFC circuit 1250 that forms the primary circuit 1261, and is also used for the switch elements 1264a, 1264b, 1264c, and 1264d of the full bridge inverter circuit 1260. In contrast to this, related art MIS-type FETs (field effect transistors) using silicon are used for the switch elements 1265a, 1265b, and 1265c of the secondary circuit 1262.
Next, a ninth embodiment will be described. The ninth embodiment relates to an amplifier having a HEMT.
The amplifier is provided with a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.
The digital predistortion circuit 1271 compensates for nonlinear strain of an input signal. The mixer 1272a mixes the nonlinear strain compensated input signal and an alternating current (AC) signal. The power amplifier 1273 includes a compound semiconductor device having a structure similar to any of the first to fifth embodiments, and amplifies the input signal mixed with the AC signal. Note that in this embodiment, for example, by switching the switching elements, an output signal may be mixed with an alternating current signal by the mixer 1272b, and the mixed signals may be transmitted to the digital predistortion circuit 1271. The amplifier can be used as a high-frequency amplifier, or a high-power amplifier. High-frequency amplifiers can be used, for example, in transmitting and receiving devices for cellular base stations, radar devices, and microwave generators.
Although the preferred embodiments have been described in detail above, various alterations and substitutions can be made to the above-described embodiments without departing from the scope of the claims.
According to the present disclosure, the drain breakdown voltage can be stably improved.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to an illustrating of the superiority and inferiority of the invention. Although the embodiment(s) of the present inventions have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2020-098696 | Jun 2020 | JP | national |
