The priority of Korean patent application No. 10-2009-0127899 filed on Dec. 21, 2009, the disclosure of which is hereby incorporated in its entirety by reference, is claimed.
An embodiment of the present invention relates to a semiconductor device and a method for fabricating the same, and more specifically, to a method for forming a buried gate.
Due to a high integration of semiconductor memory devices such as DRAM, a memory cell has been micro-sized. As a result, various efforts to secure a given cell capacitance and improve a cell transistor characteristic in the micro-sized memory cell have been made. As a memory cell has been micro-sized, a smaller-sized cell transistor has been required.
In order to obtain a cell transistor that has no micro-sized problems, a method for controlling an impurity concentration in a diffusion layer has been repeatedly performed. However, as a channel length has been reduced, it is difficult to control the depth of the diffusion layer of the transistor through various thermal treatment processes during the device manufacturing process. Moreover, the effective channel length is decreased and a threshold voltage is reduced, which results in a short channel effect, thereby degrading the operation of the cell transistor.
In order to prevent the degradation, a buried gate transistor including a trench formed on a substrate surface and a transistor gate in the trench has been suggested. Since a gate is formed in the trench to increase a distance between a source and a drain, the buried gate transistor increases the effective channel length, thereby reducing the short channel effect.
a to 1c are cross-sectional diagrams illustrating a conventional method for fabricating a semiconductor device.
Referring to
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As mentioned above, when the buried gate 127 is formed, the lower portion of the recess 110 is formed in a V shape so that it is difficult to form the gate insulating film at a uniform thickness. Even though the gate insulating film is formed to have a uniform thickness, an electronic field is concentrated at the sharp bottom of the lower portion of the recess 110, thereby degrading a gate characteristic. Specifically, a Drain Induced Barrier Lowering (DIBL) characteristic is caused, and also a gate off characteristic becomes degraded.
Various embodiments of the invention are directed to changing the shape of the lower portion of the buried gate to improve a gate characteristic.
According to an embodiment of the present invention, A method for fabricating a semiconductor device, the method comprising: forming a mask pattern over a semiconductor substrate including a device isolation film; etching the semiconductor substrate with the mask pattern as a barrier to form a recess having a semi-circular shape; filling a sacrificial material in the semi-circular shaped recess and between the mask pattern; removing the mask pattern; forming a silicon layer in a portion where the mask pattern is removed; removing the sacrificial material to form a gate region; and providing gate electrode material in the gate region to form a gate pattern.
The device isolation film is formed at a higher level than the top surface of the semiconductor substrate. The width of the top side of the recess is formed to be larger than that between the mask patterns. The width between the mask patterns ranges reduced by 20 to 50% to with respect to the size of a buried gate.
The forming-a-mask-pattern includes: performing a photo-etching process with a buried gate mask to form a pattern; and forming a spacer at sidewalls of the pattern. The forming-a-recess is performed by an isotropic process, wherein the semi-circular shape has a width that is greater than the depth. After forming a recess, further comprising forming a gate insulating film an the surface of the recess.
The sacrificial material includes one selected from the group consisting of a nitride film, an oxide film and a combination thereof. The forming-a-silicon-layer includes depositing silicon in the portion where the mask pattern is removed. The forming-a-silicon-layer is performed by a Selective Epitaxial Growth (SEG) process. The silicon layer is formed to a higher location than that of the sacrificial material.
After forming a silicon layer, further comprising depositing a gate insulating film.
A semiconductor device comprising: a gate region including a recess in a semiconductor substrate and a neck part having a smaller width than that of the recess, the recess having a width and a depth, the width of the recess being greater than the depth of the recess; a gate electrode formed in a lower portion of the gate region; and a gate hard mask disposed on an upper portion of the gate electrode.
Further comprising a gate insulating film disposed below the gate electrode. Further comprising a silicon layer disposed at a side of the neck part of the gate region.
The gate electrode is formed in the recess and a lower portion of the neck part. A semiconductor device comprising: a buried gate pattern formed in a substrate, the buried gate including a lower gate pattern formed in a recess and an upper gate pattern extending from the lower gate pattern, wherein the upper gate pattern has a first width, and the lower gate pattern has a second width larger than the first width.
The substrate comprising: a first substrate formed between the lower gate patterns; and a second substrate extending from the first substrate and formed between the upper gate patterns.
The second substrate is an epitaxial layer of the first substrate. T the recess has a horizontal dimension that is great than a vertical dimension.
a to 1c are cross-sectional diagrams illustrating a conventional method for fabricating a semiconductor device.
a to 2j are cross-sectional diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.
The present invention will be described in detail with reference to the attached drawings.
a to 2j are cross-sectional diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.
Referring to
After an insulating material is formed on the upper portion of the semiconductor substrate 200 including the trench, a planarizing process is performed to form a device isolation film 205. The insulating film includes an oxide film. The first hard mask pattern (not shown) is removed. Since the device isolation film 205 is formed to substantially the same height as the first hard mask pattern (not shown), the device isolation film 205 is formed to be higher than the top side of the semiconductor substrate 200.
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A photoresist pattern 213 that defines a buried gate region is formed on the upper portion of the second hard mask layer 210.
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A photo etching process is performed with a mask that has a width of a general buried gate to form a mask pattern. A spacer is formed on the sidewalls of the mask pattern so that a mask pattern having a fine width can be formed without using a high resolution photo process.
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A sacrificial material 220 is formed on the entire surface of the semiconductor substrate 200 including the second hard mask pattern 210a and the recess 214. A planarizing process is performed to expose the top side of the second hard mask pattern 210a. A process for forming a sacrificial material 220 is performed to define a portion with a neck part which is the upper portion of the buried gate when a silicon layer is deposited or grown. The sacrificial material 220 is formed with a material that can be easily removed such as a nitride film, an oxide film and combinations thereof. An oxide film that can be used in the sacrificial material 220 has a faster wet etch speed than that of the oxide film used in the first gate insulating film 215 and the device isolation film 205.
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A gate hard mask 240 is formed on the top portion of the gate electrode material 235, thereby obtaining a buried gate 242. The buried gate 242 includes an upper gate pattern with a first width, and a lower gate pattern with a second width. The second width is larger than the first width. The lower gate pattern is enlarged in a direction along the surface of the substrate 200. Comparing
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The buried gate 342 includes a recess that has a lower portion having a half-circular shape with a large radius of curvature, and a neck part 341 over the lower portion having a smaller width than that of the lower portion. A gate electrode material 335 is buried in the lower portion of the buried gate 342, and a gate hard mask 340 is disposed on the top portion of the gate electrode material 335. The gate hard mask 340 is formed with a substantially uniform thickness between the semiconductor substrate 300 and the gate electrode material 335 in the lower portion of the recess.
A first gate insulating film 315 is disposed in the lower portion of the buried gate 342 with a substantially uniform thickness. The first gate insulating film 315 is formed with a material including an oxide film. A second gate insulating film 330 may be further formed over the first gate insulating film 315 in order to supplement the first gate insulating film 315 which may have been damaged at preceding steps. The process for forming a second gate insulating film 330 may not be performed.
Since the lower portion of the buried gate 342 is formed to have an enlarged width, for example, in a half-circular shape with a large radius of curvature, the gate insulating film 315 having a uniform thickness may be formed by a thermal oxidation process. A distance W3 between the device isolation film 305 and an upper portion of the buried gate 342 is long in comparison with the prior art, thereby increasing the contact area for connecting between a gate junction in or on the silicon layer 325 and a bit line or a storage node pattern each of which will be formed in a subsequent process. As a result, contact resistance can be improved.
As described above, the embodiments of the present invention can improve a DIBL characteristic with a large radius of curvature, thereby improving a gate characteristic. Also, an area of a region for connecting a gate junction increases to improve contact resistance.
The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps describe herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.
Number | Date | Country | Kind |
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10-2009-0127899 | Dec 2009 | KR | national |