Semiconductor device and method for fabricating the same

Abstract

A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment of the present invention.

FIGS. 2A through 2C are cross-sectional views illustrating respective steps for fabricating a semiconductor device according to an embodiment of the present invention.

FIGS. 3A through 3C are cross-sectional views illustrating respective steps for fabricating a semiconductor device according to an embodiment of the present invention.

FIGS. 4A through 4C are cross-sectional views illustrating respective steps for fabricating a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a graph showing the relationship between threshold voltage (Vt) and gate length (Lg) for MIS transistors.

FIG. 6 is a plan view illustrating a typical DRAM embedded LSI chip.

FIG. 7 is a circuit configuration of a typical sense amplifier region in a DRAM embedded LSI.

FIG. 8 is a cross-sectional view illustrating respective configurations of MIS transistors formed on regions shown in FIG. 6 and FIG. 7.

FIG. 9 is a graph showing the dependency of threshold voltage (Vt) on gate length (Lg) for the known MIS transistor.

Claims

1. A semiconductor device comprising: a first MIS transistor formed in a first region of a semiconductor substrate;a second MIS transistor formed in a second region of the semiconductor substrate; anda third MIS transistor formed in a third region of the semiconductor substrate,wherein the first MIS transistor includes a first gate insulating film formed on the first region, a first gate electrode formed on the first gate insulating film, a first impurity doped layer formed in part of the first region located at each side of the first gate electrode and a first threshold control layer formed in part of the first region located under the first gate electrode,wherein the second MIS transistor includes a second gate insulating film formed on the second region, a second gate electrode formed on the second gate insulating film, a second impurity doped layer formed in part of the second region located at each side of the second gate electrode and a second threshold control layer formed in part of the second region located under the second gate electrode,wherein the third MIS transistor includes a third gate insulating film formed on the third region, a third gate electrode formed on the third gate insulating film, a third impurity doped layer formed in part of the third region located at each side of the third gate electrode and a third threshold control layer formed in part of the third region located under the third gate electrode,wherein a thickness of the second gate insulating film is substantially the same as or smaller than a thickness of the first gate insulating film and is larger than a thickness of the third gate insulating film,wherein the second impurity doped layer has substantially the same impurity concentration profile as an impurity concentration profile of the third impurity doped layer and has a lower impurity concentration than an impurity concentration of the first impurity doped layer, andwherein the second threshold control layer has substantially the same impurity concentration profile as an impurity concentration profile of the first threshold control layer and has a lower impurity concentration than an impurity concentration of the third threshold control layer.

2. The semiconductor device of claim 1, wherein the first MIS transistor further includes first sidewalls on side surfaces of the first gate electrode, respectively, and first source/drain regions formed so that each said first source/drain doped region is located in part of the first region outwardly extending from an associated one of the first sidewalls, wherein the second MIS transistor further includes second sidewalls on side surfaces of the second gate electrode, respectively, and second source/drain regions formed so that each said second source/drain doped region is located in part of the second region outwardly extending from an associated one of the second sidewalls, andwherein the third MIS transistor further includes third sidewalls on side surfaces of the third gate electrode, respectively, and third source/drain regions formed so that each said third source/drain doped region is located in part of the third region outwardly extending from an associated one of the third sidewalls.

3. The semiconductor device of claim 1, wherein each of the first impurity doped layer, the second impurity doped layer and the third impurity doped layer is a LDD region.

4. The semiconductor device of claim 1, wherein a junction depth of the first impurity doped layer is larger than respective junction depths of the second impurity doped layer and the third impurity doped layer.

5. The semiconductor device of claim 1, wherein the second impurity doped layer and the third impurity doped layer are formed by the same ion implantation.

6. The semiconductor device of claim 1, wherein the first threshold control layer and the second threshold control layer are formed by the same ion implantation.

7. The semiconductor device of claim 1, further comprising; a memory cell; anda sense amplifier,wherein the second MIS transistor is a shared switch transistor located between the memory cell and the sense amplifier.

8. The semiconductor device of claim 1, further comprising: a memory cell; anda sense amplifier,wherein the second MIS transistor is a precharge transistor located between the memory cell and the sense amplifier.

9. The semiconductor device of claim 1, further comprising: a memory cell; anda sense amplifier,wherein the second MIS transistor is an equalizing transistor located between the memory cell and the sense amplifier.

10. The semiconductor device of claim 1, wherein the first MIS transistor is an input/output transistor.

11. The semiconductor device of claim 1, wherein the third MIS transistor is a logic transistor.

12. The semiconductor device of claim 1, wherein a gate length of the second gate electrode is smaller than a gate length of the first gate electrode and larger than a gate length of the third gate electrode.

13. A method for fabricating a semiconductor device which includes a first MIS transistor formed in a first region of a semiconductor substrate; a second MIS transistor formed in a second region of the semiconductor substrate; and a third MIS transistor formed in a third region of the semiconductor substrate, the method comprising the steps of: a) forming a first threshold control layer in the first region and forming a second threshold control layer in the second region;b) forming, in the third region, a third threshold control layer having a smaller impurity concentration than an impurity concentration of the second threshold control layer;c) forming, after the step a) and the step b), a first gate insulating film on the first region;d) forming, after the step a) and the step b), a second gate insulting film having a thickness that is substantially the same as or smaller than a thickness of the first gate insulating film on the second region;e) forming, after the step a) and the step b), a third insulating film having a smaller thickness than a thickness of the second gate insulating film on the third region;f) forming a first gate electrode on the first gate insulating film, a second gate electrode on the second gate insulating film and a third gate electrode on the third gate insulating film;g) forming a first impurity doped layer in part of the first region located at each side of the first gate electrode; andh) forming a second impurity doped layer in part of the second region located at each side of the second region and forming a third impurity doped layer in part of the third region located at each side of the third gate electrode,wherein in the step h), an impurity concentration of the second impurity doped layer is made higher than an impurity concentration of the first impurity doped layer.

14. The method of claim 13, further comprising the steps of: i) forming, after the step h), first sidewalls on side surfaces of the first gate electrode, respectively, second sidewalls on side surfaces of the second gate electrode, respectively, and third sidewalls on side surfaces of the third gate electrode, respectively; andj) forming, after the step i), first source/drain regions so that each said first source/drain region is located in part of the first region outwardly extending from an associated one of the first sidewalls, second source/drain regions so that each said second source/drain region is located in part of the second region outwardly extending from an associated one of the second sidewalls, and third source/drain regions so that each said third source/drain region is located in part of the third region outwardly extending from an associated one of the third sidewalls.

15. The method of claim 13, wherein in the step g), the first impurity doped layer is formed so as to have a larger junction depth than respective junction depths of the second impurity doped layer and the third impurity doped layer.

16. The method of claim 1, wherein in the step f), a gate length of the second gate electrode is made smaller than a gate length of the first gate electrode and larger than a gate length of the third gate electrode.