Semiconductor device and method for fabricating the same

Abstract

A trench isolation surrounding the lateral sides of an active region of a P-channel MIS transistor PTr and a trench isolation surrounding the lateral sides of an active region of an N-channel MIS transistor NTr have different film qualities.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a view illustrating the planar structure of a semiconductor device according to a first embodiment of the present invention, while FIG. 1B is a cross-sectional view taken along the line A-A in FIG. 1A.

FIGS. 2A through 2E are cross-sectional views illustrating process steps for fabricating the semiconductor device according to the first embodiment of the present invention.

FIGS. 3A through 3D are cross-sectional views illustrating process steps for fabricating the semiconductor device according to the first embodiment of the present invention.

FIG. 4A is a view illustrating the planar structure of a semiconductor device according to a second embodiment of the present invention, while FIG. 4B is a cross-sectional view taken along the line B-B in FIG. 4A.

FIGS. 5A through 5D are cross-sectional views illustrating process steps for fabricating the semiconductor device according to the second embodiment of the present invention.

FIGS. 6A through 6D are cross-sectional views illustrating process steps for fabricating the semiconductor device according to the second embodiment of the present invention.

FIGS. 7A and 7B are cross-sectional views illustrating process steps for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 8A is a view illustrating the planar structure of a semiconductor device according to a modified example of the second embodiment, while FIG. 8B is a cross-sectional view taken along the line C-C in FIG. 8A.

FIG. 9A is a view illustrating the planar structure of a semiconductor device according to a third embodiment of the present invention, while FIG. 9B is a cross-sectional view taken along the line D-D in FIG. 9A.

FIGS. 10A through 10D are cross-sectional views illustrating process steps for fabricating the semiconductor device according to the third embodiment of the present invention.

FIGS. 11A through 11D are cross-sectional views illustrating process steps for fabricating the semiconductor device according to the third embodiment of the present invention.

FIGS. 12A through 12D are cross-sectional views illustrating process steps for fabricating the semiconductor device according to the third embodiment of the present invention.

FIGS. 13A and 13B illustrate the directions and magnitudes of stresses for increasing driving forces of MIS transistors.

FIG. 14 is a cross-sectional view illustrating the structure of a conventional semiconductor device.

Claims

1. A semiconductor device, comprising: a first semiconductor region in which a first MIS transistor is formed;a second semiconductor region in which a second MIS transistor is formed;a first trench isolation region surrounding lateral sides of the first semiconductor region; anda second trench isolation region surrounding lateral sides of the second semiconductor region,wherein at least part of the first trench isolation region and part of the second trench isolation region have different film qualities.

2. The semiconductor device of claim 1, wherein direction or magnitude of stress that the first trench isolation region applies to a channel of the first MIS transistor is different from direction or magnitude of stress that the second trench isolation region applies to a channel of the second MIS transistor.

3. The semiconductor device of claim 1, wherein the first MIS transistor is an N-channel MIS transistor, and the second MIS transistor is a P-channel MIS transistor.

4. The semiconductor device of claim 1, wherein direction or magnitude of stress applied to a channel of the first MIS transistor by parts of the first trench isolation region located at both sides of the first semiconductor region in a gate width direction is different from direction or magnitude of stress applied to a channel of the second MIS transistor by parts of the second trench isolation region located at both sides of the second semiconductor region in a gate width direction.

5. The semiconductor device of claim 1, wherein compressive stress in parts of the first trench isolation region located at both sides of the first semiconductor region in a gate width direction is greater than compressive stress in parts of the second trench isolation region located at both sides of the second semiconductor region in a gate width direction.

6. The semiconductor device of claim 1, wherein density in parts of the first trench isolation region located at both sides of the first semiconductor region in a gate width direction is different from density in parts of the second trench isolation region located at both sides of the second semiconductor region in a gate width direction.

7. The semiconductor device of claim 1, wherein parts of the second trench isolation region located at both sides of the second semiconductor region in a gate width direction include a multilayer film of a silicon oxide film and a silicon film, while parts of the first trench isolation region located at both sides of the first semiconductor region in a gate width direction include a silicon oxide film but do not include a silicon film.

8. The semiconductor device of claim 1, wherein direction or magnitude of stress applied to a channel of the first MIS transistor by parts of the first trench isolation region located at both sides of the first semiconductor region in a gate length direction is different from direction or magnitude of stress applied to a channel of the second MIS transistor by parts of the second trench isolation region located at both sides of the second semiconductor region in a gate length direction.

9. The semiconductor device of claim 1, wherein compressive stress in parts of the second trench isolation region located at both sides of the second semiconductor region in a gate length direction is greater than compressive stress in parts of the first trench isolation region located at both sides of the first semiconductor region in a gate length direction.

10. The semiconductor device of any one of claims 1 to 3, and 8 and 9, wherein density in parts of the first trench isolation region located at both sides of the first semiconductor region in a gate length direction is different from density in parts of the second trench isolation region located at both sides of the second semiconductor region in a gate length direction.

11. The semiconductor device of any one of claims 1 to 3 and 8 to 10, wherein parts of the first trench isolation region located at both sides of the first semiconductor region in a gate length direction include a multilayer film of a silicon oxide film and a silicon film, while parts of the second trench isolation region located at both sides of the second semiconductor region in a gate length direction include a silicon oxide film but do not include a silicon film.

12. The semiconductor device of any one of claims 1 to 11, wherein the first trench isolation region and the second trench isolation region are formed so as to be adjacent to each other.

13. The semiconductor device of claim 12, wherein part of the first trench isolation region and part of the second trench isolation region that are located between the first semiconductor region and the second semiconductor region are formed in a single trench.

14. A method for fabricating a semiconductor device that includes a first semiconductor region in which a first MIS transistor is formed and a second semiconductor region in which a second MIS transistor is formed, the method comprising the steps of; (a) forming a first trench in part of a semiconductor layer that surrounds lateral sides of the first semiconductor region, and forming a second trench in part of the semiconductor layer that surrounds lateral sides of the second semiconductor region; and(b) filling the first trench to thereby form a first trench isolation region and filling the second trench to thereby form a second trench isolation region,wherein, in the step (b), at least part of the first trench isolation region and part of the second trench isolation region are formed so as to have different film qualities.

15. The method of claim 14, wherein, in the step (b), direction or magnitude of stress that the first trench isolation region applies to a channel of the first MIS transistor is different from direction or magnitude of stress that the second trench isolation region applies to a channel of the second MIS transistor.

16. The method of claim 14, wherein, in the step (b), the first and second trenches are filled with insulating films of different densities.

17. The method of claim 14, wherein the step (b) includes the sub-steps of: (b1) forming a silicon oxide film that covers a surface of the first trench and a surface of the second trench by performing thermal oxidation;(b2) forming, on the silicon oxide film, a silicon film with which the first and second trenches are filled; and(b3) subjecting part of the silicon film located in the first trench to oxidation, and leaving part of the silicon film located in the second trench without subjecting that part to oxidation.

18. The method of claim 14, wherein, in the step (a), the first and second trenches are formed as a single trench between the first and second semiconductor regions.