The invention relates in general to a semiconductor device and a method for fabricating the same, and more particularly to a three-dimensional semiconductor device and a method for fabricating the same.
Recently, as the demand for more excellent memory devices has gradually increased, various three-dimensional (3D) memory devices have been provided. However, in order for such three-dimensional memory devices to achieve higher storage capacity and higher performance, there is still a need to provide an improved three-dimensional memory device and a method for fabricating the same.
The present invention relates to a semiconductor device. Compared with the comparative example in which the channel layer is arranged outside the first conductive pillar and the second conductive pillar and surrounds the first conductive pillar and the second conductive pillar, since the channel layer of the semiconductor device of the present invention is disposed between the first conductive pillar and the second conductive pillars, it can have a shorter channel length, which not only improves the performance of the semiconductor device, but also increases the density of the chip.
According to an embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings penetrate along a first direction, and each of the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are electrically isolated from each other. The channel layer extends along the first direction, wherein the channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar and the channel layer.
According to another embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings penetrate the stack along a first direction, and each of the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are electrically isolated from each other. The channel layer extends along the first direction, wherein the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar and the channel layer. The conductive layer includes a first bottom conductive layer, and the first bottom conductive layer is disposed under the first conductive pillar and the second conductive pillar.
According to yet another embodiment of the present invention, a method for fabricating a semiconductor device is provided. The method includes the following steps. First, a stack is formed on a substrate. The stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. After that, a plurality of memory strings are formed. The memory strings penetrate the stack along a first direction, and each of the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are electrically isolated from each other. The channel layer extends along the first direction, wherein the channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar and the channel layer.
The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.
Referring to
Each of the memory strings MS includes a first conductive pillar 118a and a second conductive pillar 118b, a channel layer 120, an insulating pillar 124, and a memory structure 122. The insulating pillar 124 may include a second oxide layer 146 and an oxide material 148. The first conductive pillar 118a and the second conductive pillar 118b respectively extend along the first direction and are electrically isolated from each other. The channel layer 120 and the insulating pillar 124 extend along the first direction, and penetrate the first bottom conductive layer 105, the second bottom insulating layer 107, the second bottom conductive layer 112, the third bottom insulating layer 110, and the other layers of the stack ST. The channel layer 120 is disposed between the first conductive pillar 118a and the second conductive pillar 118b as shown in
In
In
The memory structure 122 surrounds a portion of the first conductive pillar 118a, a portion of the second conductive pillar 118b, and a portion of the channel layer 120 in
In some embodiments, the substrate 101 is, for example, a dielectric layer (for example, a silicon oxide layer). For example, the insulating layers IL may be a silicon oxide layer, and the silicon oxide layer may include silicon dioxide, for example. The material of the insulating pillar 124 is, for example, an oxide. The insulating pillar 124 may include a second oxide layer 146 and an oxide material 148. The materials of the second oxide layer 146 and the oxide material 148 may be the same as each other, for example, both are silicon dioxide. The conductive layers CL may be formed of conductive materials, such as polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSiX), cobalt silicide (CoSiX) or other suitable materials. In the present embodiment, the material of the first bottom conductive layer 105 is different from the material of the conductive layers CL (that is, the second bottom conductive layer 112 and the upper conductive layer 116) disposed above the first bottom conductive layer 105. For example, the material of a bottom conductive layer 105 is P-type doped polysilicon, and the material of the second bottom conductive layer 112 and the upper conductive layers 116 is tungsten, but the present invention is not limited thereto. In some embodiments, the material of the first bottom conductive layer 105 may be the same as the materials of the second bottom conductive layer 112 and the upper conductive layer 116.
In the present embodiment, the memory structure 122 includes a charge storage material, such as a charge storage material formed of an oxide layer, a nitride layer, and an oxide layer, but the invention is not limited thereto. The material of the channel layer 120 is, for example, undoped polysilicon, but the invention is not limited thereto. The material of the first conductive pillar 118a and the second conductive pillar 118b is, for example, N-type doped polysilicon, but the invention is not limited thereto.
In the present embodiment, only 7 insulating layers IL and 6 conductive layers CL are exemplarily shown, but the present invention is not limited to this. The number of insulating layers IL can be greater than 7, and the number of conductive layers CL can be greater than 6, and the number and configuration of the insulating layers IL and the conductive layers CL can be adjusted as required.
As shown in
In the present embodiment, there may be residual oxide between a bottom structure 18a of the first conductive pillar 118a and the channel layer 120 and between a bottom structure 18b of the second conductive pillar 118b and the channel layer 120. The second bottom conductive layer 112 may serve as a dummy gate. In addition, a voltage of 0 V or smaller than 0 V (such as a negative voltage) can be applied to the second bottom conductive layer 112 to prevent leakage current. However, the present invention is not limited thereto. In some embodiments, there may be no oxide between the first conductive pillar 118a and the channel layer 120 and between the second conductive pillar 118b and the channel layer 120.
In some embodiments, the first bottom conductive layer 105 can be used as a dummy gate, and a voltage of 0V or smaller than 0 V (such as a negative voltage) can be applied to the first bottom conductive layer 105 to prevent leakage current from the channel layer 120.
In some embodiments, the semiconductor device 100 of the present invention can be applied to three-dimensional AND flash memory (3D AND flash memory), three-dimensional NOR memory (3D NOR memory) or other suitable memory.
Referring to
Referring to
In some embodiments, after the third bottom insulating layer 110 with recesses is removed, a third bottom insulating layer 110 can be deposited again on the bottom sacrificial layer 109 and the bottom structures 18a and 18b. In some embodiments, an insulating material may be filled in the recesses of the third bottom insulating layer 110. In some embodiments, a chemical mechanical polishing (CMP) process can be used to allow the third bottom insulating layer 110 to have a flat upper surface. However, the present invention is not limited thereto.
Referring to
Referring to
Thereafter, referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Thereafter, the memory material and the conductive material are filled in the positions where the upper sacrificial layers 111 and the bottom sacrificial layer 109 are removed (that is, the fourth openings 140), to form a plurality of memory structures 122 and a plurality of upper conductive layers 116 and the second bottom conductive layer 112, respectively. The upper conductive layers 116 and the second bottom conductive layer 112 correspond to the positions where the upper sacrificial layers 111 and the bottom sacrificial layer 109 are removed, respectively. The memory structures 122 are formed on the sidewalls of the fourth openings 140. The memory structures 122 extend along the first direction and the second direction, so that the memory structures 122 surround each of the upper conductive layers 116 and the second bottom conductive layer 112, respectively, and the semiconductor device 100 shown in
In the subsequent manufacturing process, a plurality of input lines and a plurality of output lines (not shown) may be formed on the semiconductor device 100, and the input lines and output lines may be electrically connected to the first conductive pillars 118a and the second conductive pillars 118b, respectively.
According to an embodiment of the present invention, a semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings penetrate the stack along a first direction, and each of the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction, respectively, and are electrically isolated from each other. The channel layer extends along the first direction, wherein the channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar and the channel layer.
Compared with the comparative example in which the channel layer is disposed outside the first conductive pillar and the second conductive pillar and surrounds the first conductive pillar and the second conductive pillar, since the channel layer of the semiconductor device in the present application is disposed between the first conductive pillar and the second conductive pillar, the channel length can be greatly shortened, so the size of the memory cell can be reduced, and the memory cells can be stacked more densely. Therefore, the semiconductor device of the present invention can improve the performance of the semiconductor device on the one hand, and can increase the density of the chip on the other hand.
While the invention has been described by way of example and in terms of the preferred embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Number | Name | Date | Kind |
---|---|---|---|
7696559 | Arai | Apr 2010 | B2 |
7982260 | Fukuzumi | Jul 2011 | B2 |
8030700 | Sakamoto | Oct 2011 | B2 |
8072024 | Ishikawa | Dec 2011 | B2 |
8211811 | Matsushita | Jul 2012 | B2 |
8236673 | Son | Aug 2012 | B2 |
8338876 | Kito | Dec 2012 | B2 |
8349681 | Alsmeier | Jan 2013 | B2 |
8415242 | Mizushima | Apr 2013 | B2 |
8552489 | Eom | Oct 2013 | B2 |
8658499 | Makala | Feb 2014 | B2 |
8829595 | Lee | Sep 2014 | B2 |
8928061 | Chien | Jan 2015 | B2 |
8994091 | Lee | Mar 2015 | B2 |
9018682 | Izumida | Apr 2015 | B2 |
9076879 | Yoo | Jul 2015 | B2 |
9099496 | Tian | Aug 2015 | B2 |
9159739 | Makala | Oct 2015 | B2 |
9219070 | Thimmegowda | Dec 2015 | B2 |
9219073 | Chen | Dec 2015 | B2 |
9236396 | Koka | Jan 2016 | B1 |
9263462 | Eom | Feb 2016 | B2 |
9305849 | Tsutsumi | Apr 2016 | B1 |
9312008 | Nam | Apr 2016 | B2 |
9406694 | Ikeno | Aug 2016 | B1 |
9634024 | Kanamori | Apr 2017 | B2 |
9659958 | Lee | May 2017 | B2 |
10068917 | Kanamori | Sep 2018 | B2 |
10141326 | Oh | Nov 2018 | B1 |
10243000 | Sohn | Mar 2019 | B2 |
10276583 | Sharangpani | Apr 2019 | B2 |
10340286 | Goda | Jul 2019 | B2 |
10490567 | Choi | Nov 2019 | B2 |
10566346 | Lee | Feb 2020 | B2 |
10910402 | Hu | Feb 2021 | B1 |
11037947 | Lai | Jun 2021 | B2 |
11133329 | Lue | Sep 2021 | B2 |
20080173928 | Arai | Jul 2008 | A1 |
20090097321 | Kim | Apr 2009 | A1 |
20090296476 | Shin | Dec 2009 | A1 |
20100019310 | Sakamoto | Jan 2010 | A1 |
20100038699 | Katsumata | Feb 2010 | A1 |
20100202206 | Seol | Aug 2010 | A1 |
20100320528 | Jeong | Dec 2010 | A1 |
20120012920 | Shin | Jan 2012 | A1 |
20120091521 | Goda | Apr 2012 | A1 |
20120098050 | Shim | Apr 2012 | A1 |
20120140562 | Choe | Jun 2012 | A1 |
20120211820 | Komori | Aug 2012 | A1 |
20120267702 | Jee | Oct 2012 | A1 |
20130134492 | Yang | May 2013 | A1 |
20130134493 | Eom | May 2013 | A1 |
20130270643 | Lee | Oct 2013 | A1 |
20140203442 | Yun | Jul 2014 | A1 |
20140326939 | Yamato | Nov 2014 | A1 |
20150104916 | Lee | Apr 2015 | A1 |
20150155297 | Eom | Jun 2015 | A1 |
20150206896 | Chen | Jul 2015 | A1 |
20150340369 | Lue | Nov 2015 | A1 |
20150340371 | Lue | Nov 2015 | A1 |
20160064498 | Liu | Mar 2016 | A1 |
20160099254 | Park | Apr 2016 | A1 |
20160126252 | Tsuda | May 2016 | A1 |
20170221921 | Kanamori | Aug 2017 | A1 |
20170229475 | Yasuda | Aug 2017 | A1 |
20180114794 | Jang | Apr 2018 | A1 |
20190244971 | Harari | Aug 2019 | A1 |
20200091180 | Seki | Mar 2020 | A1 |
20200258897 | Yan et al. | Aug 2020 | A1 |
20200286875 | Nishida et al. | Sep 2020 | A1 |
20200295043 | Nishida et al. | Sep 2020 | A1 |
20200365611 | Chiu | Nov 2020 | A1 |
20200381450 | Lue | Dec 2020 | A1 |
20200402996 | Cheon | Dec 2020 | A1 |
20210225863 | Wu | Jul 2021 | A1 |
20210408034 | Lee | Dec 2021 | A1 |
20210408036 | Lee | Dec 2021 | A1 |
20220037305 | Lee | Feb 2022 | A1 |
20220068957 | Yeh | Mar 2022 | A1 |
Number | Date | Country | |
---|---|---|---|
20220165746 A1 | May 2022 | US |