This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-283535, filed on Sep. 29, 2005, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device having a double-diffused metal oxide semiconductor (DMOS) transistor structure and to a method for manufacturing such a semiconductor device. More particularly, the present invention relates to an improvement in the structure and a manufacturing method for reducing influence from a parasitic bipolar transistor formed in the DMOS transistor structure.
In recent years, power semiconductor devices used in portable electronics devices or consumer electronics devices, more particularly, power semiconductor devices capable of withstand voltages of up to 100 V, are required to be further downsized. One example of such a semiconductor device is a double-diffused metal oxide semiconductor field effect transistor (DMOS FET), which is easily highly integrated.
The DMOS transistor 100 forms a parasitic bipolar transistor in which the source diffusion layer 102 functions as an emitter E, the body region 101 functions as a base B, and the first conduction type epitaxial silicon layer 100b functions as a collector C. When the DMOS transistor 100 is operating, impact ionization may cause carriers to be generated in the body region 101. In this case, the potential of the body region 101, which should be clamped to the source potential, may change to generate a base current. This may cause the parasitic bipolar transistor to operate. As a result, unintended current may flow between the source electrode S and the drain electrode D thereby destabilizing the operation of the DMOS transistor 100.
Japanese Laid-Open Patent Publication No. 62-39069 and R&D Review (Vol.35, No.2, 2000.6, pp.3-10) of Toyota Central Labs., Inc. describe techniques for preventing such a parasitic bipolar transistor from operating. More specifically, the conventional techniques use lifetime killers, such as a gold diffusion layer and a lattice defect layer, formed in and near the body region 101 of the DMOS transistor 100.
The ON resistance of the DMOS transistor 100 is effectively reduced by miniaturizing elements. However, when the junction depth of the body region 101 and the source diffusion layer 102 is reduced to miniaturize elements, the base layer becomes thin. This increases the current gain of the parasitic bipolar transistor. When the junction depth of the body region 101 and the source diffusion layer 102 is reduced, the contact resistance between the source electrode S and the source diffusion layer 102 and the diffusion layer resistance of the body region 101 increase. This increases a parasitic resistance Rp formed between the base B (the body region 101) of the parasitic bipolar transistor and the source electrode S. As a result, carriers generated in the body region 101 cause the potential of the body region 101 to change over a long period of time. Further, when the junction depth of the body region 101 and the source diffusion layer 102 is reduced, a gold diffusion layer or a lattice defect layer described in the above publications may be difficult to form in the body region 101.
As a result, influence from the parasitic bipolar transistor may become significant so that the operation of the DMOS transistor 100 inevitably becomes unstable. It is difficult to satisfy both the need for preventing the parasitic bipolar transistor from operating and the need for reducing the ON resistance of the DMOS transistor.
The present invention provides a semiconductor device that prevents a parasitic bipolar transistor from operating while reducing the ON resistance of a double-diffused transistor. The present invention also provides a manufacturing method for such a semiconductor device.
One aspect of the present invention is a semiconductor device provided with a double-diffused transistor including a semiconductor having a first type of conductivity, a body region formed in the semiconductor and having a second type of conductivity, and a source diffusion layer formed in the body region and having the first type of conductivity. The body region includes a first impurity having the second type of conductivity, and a second impurity having the second type of conductivity, a solid solubility limit and a diffusivity in the semiconductor that are lower than those of the first impurity, and a concentration ratio that is relatively high with respect to the first impurity in the body region.
A further aspect of the present invention is a method for forming a double-diffused transistor. The method includes implanting into a semiconductor having a first type of conductivity a first impurity having a second type of conductivity to form a body region, implanting into the body region an impurity having the first type of conductivity to form a source diffusion layer, and implanting into the body region a second impurity having the second type of conductivity and a solid solubility limit and a diffusivity in the semiconductor that are lower than those of the first impurity.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which:
In the drawings, like numerals are used for like elements throughout.
A semiconductor device according to a preferred embodiment of the present invention will now be described with reference to FIGS. 2 to 5.
In the semiconductor device of the present embodiment, boron B, which has a relatively high solid solubility limit and a relatively high diffusivity in the silicon forming the substrate, and indium In, which has a relatively low solid solubility limit and a relatively low diffusivity in silicon, are diffused into the body region 10 as p-type impurities. In the body region 10, indium In is diffused into the vicinity of the source diffusion layer 12a. The concentration ratio of indium In to boron B is higher in the vicinity of the source diffusion layer 12a than in other portions of the body region 10. Further, the peak concentration of indium In is higher than its solid solubility limit in silicon. Thus, the lifetime of carriers in the body region 10 is reduced, and the parasitic bipolar transistor is prevented from operating. Further, the lateral junction abruptness at the junction between the body region 10 and the source diffusion layer 12a is improved. As a result, the ON resistance of the DMOS transistor 200 is reduced.
A method for manufacturing the semiconductor device including the DMOS transistor 200 shown in
Referring to
Next, a sacrificial oxide film 3 having a film thickness of about 200 Å is formed on the upper surface of the n-type epitaxial silicon layer 2. Ion implantation into the p-type silicon substrate 1 and the n-type epitaxial silicon layer 2 through the sacrificial oxide film 3 is then performed to adjust the threshold voltage or the withstand voltage.
Afterward, the sacrificial oxide film 3 is removed. Referring to
After the phosphor glass generated by the doping of phosphor P is removed, referring to
Next, referring to
After the body region 10 is formed, referring to
Further, referring to
During the indium In implantation, indium In is also implanted in the drain diffusion layer 12b. If indium In is implanted near a drain end of the drain diffusion layer 12b, which is located in a main current passage between the source and the drain of the DMOS transistor 200, this would increase the ON resistance of the DMOS transistor 200. To prevent this, the implanting direction of indium In is inclined as described above to limit the formation area for an indium diffusion layer 13a. More specifically, indium In is implanted at a predetermined inclination angle in a manner that an area in the junction between the silicon layer 2 and the drain diffusion layer 12b that faces the source diffusion layer 12a vicinity of left side of the indium diffusion layer 13a in
The peak concentration of indium In diffused into each of the indium diffusion layers 13 and 13a is about 1018 ions per square centimeter. The solid solubility limit of indium In in silicon Si is about 2*1017 ions per square centimeter in an equilibrium state and is about 7*1017 ions per square centimeter even in a non-equilibrium state. Thus, some of the implanted indium In does not solidify and remains in the lattice of silicon.
After indium In is implanted, referring to
Afterwards, referring to
In the DMOS transistor 200 of the semiconductor device of the preferred embodiment manufactured through the above method, the indium diffusion layer 13 is locally formed at the source end of the source diffusion layer 12a. The solid solubility limit and the diffusivity of indium In, which is diffused into the indium diffusion layer 13, in the silicon substrate (silicon) are lower than those of boron B. The indium diffusion layer 13 contains indium In that does not solidify and remains between the crystals of silicon. Such indium In that does not solidify functions as a lifetime killer that reduces the lifetime of carriers. When the DMOS transistor 200 is operating, carriers generated by impact ionization or the like are prevented from changing the potential at the body region 10. As a result, the indium diffusion layer 13 prevents the parasitic bipolar transistor from operating and improves the operation stability of the DMOS transistor 200.
Further, the indium diffusion layer 13 improves the lateral junction abruptness of impurities at the interface between the source diffusion layer 12a and the body region 10. The lateral junction abruptness of impurities indicates the steepness of the gradient of the curve representing the concentration of impurities in the lateral direction of the silicon substrate, or in the direction in which the substrate surface extends.
Only arsenic As is diffused into the substrate represented by curve L1. Only boron B is diffused into the substrate represented by curve L2. Boron B and indium In are diffused into the substrate represented by curve L3. Arsenic As and boron B are diffused to form a pn junction in the substrate represented by curve L4. The pn junction corresponds to a junction of the body region 10 and the source diffusion layer 12a when the indium diffusion layer 13 is not formed. In addition to arsenic As and boron B, indium In is diffused into the substrate represented by curve L5. Further, in this substrate, a pn junction is formed by arsenic As, boron B, and indium In. The pn junction corresponds to a junction between the body region 10 and the source diffusion layer 12a in a portion at which the indium diffusion layer 13 is formed in the present embodiment.
As indicated by curve L2 in
As apparent from the comparison between curve L4 and curve L5, the carrier concentration of impurities in the lateral direction at the pn junction formed by arsenic As, born B, and indium In decreases at a gradient steeper than that at the pn junction formed only by arsenic As and boron B.
The semiconductor device and the manufacturing method for the semiconductor device of the first embodiment have the advantages described below.
(1) The indium diffusion layer 13 is formed locally in the vicinity of the source diffusion layer 12a in the body region 10. Thus, the lifetime of carriers in the body region 10 is reduced, and the parasitic bipolar transistor is prevented from operating. Further, the lateral junction abruptness at the junction between the body region 10 and the source diffusion layer 12a is improved. As a result, the ON resistance of the DMOS transistor 200 is reduced.
(2) The indium diffusion layer 13 is formed using the same mask 11 that is also used to form the source diffusion layer 12a. This eliminates the need for additional processes of forming a mask and removing the mask, and enables the DMOC transistor 200 to be easily manufactured.
(3) The source diffusion layer 12a and the drain diffusion layer 12b are formed simultaneously by performing a single implantation of arsenic As. This simplifies the manufacturing processes.
(4) Indium In is implanted at a predetermined inclination angle in a manner that the drain distal end of the drain diffusion layer 12b is hidden behind the mask 11. This prevents indium In from being implanted in the vicinity of the drain distal end of the drain diffusion layer 12b that is on the main current passage when the DMOS transistor 200 is operating. Thus, the ON resistance of the DMOS transistor 200 is prevented from increasing unnecessarily.
It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, it should be understood that the present invention may be embodied in the following forms.
In the preferred embodiment, a mask for preventing indium In from being implanted in the vicinity of the source end of the source diffusion layer 12a and the drain end of the drain diffusion layer 12b may be used when indium In is implanted. More specifically, a mask, which differs from the mask used when arsenic As is implanted, may be used when indium In is implanted at a right angle into the substrate.
In the above embodiment, the indium diffusion layer 13 may be formed to cover the entire junction between the body region 10 and the source diffusion layer 12a as shown in
In the above embodiment, the first type of conductivity may be p-type and the second type of conductivity may be n-type in a DMOS transistor 300 shown in
The two impurities forming the body region 10 should not be limited to boron B and indium In or should phosphor P and antimony Sb. Other combinations of impurities having a suitable solid solubility limit and diffusivity may be used to form the body region 10.
The present invention should not be limited to the semiconductor device including the DMOS transistor in which both the source electrode and the drain electrode are arranged on the substrate surface (horizontal DMOS transistor). For example, as shown in
As shown in
The present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.
Number | Date | Country | Kind |
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2005-283535 | Sep 2005 | JP | national |