Patent Application
20150348871
1. Field of the Invention
The present invention relates generally to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to
2. Description of the Prior Art
Three dimensional (3D) integrated circuits utilizing through silicon via (TSV) structures have become popular these years as driven by the strong demand for high speed, high density, small size, and multifunctional electronic devices. The TSV structures are via openings that extend completely through a semiconductor substrate and enable devices above and below the substrate to be coupled to one another and to devices internal to the substrate.
To address the needs in flip chip packaging technology, silicon interposer with TSV has emerged as a good solution to provide high density interconnection, minimize coefficient of thermal expansion (CTE) mismatch between the die and the interposer, and improve electrical performance due to short interconnection from chip to the substrate.
However, the prior art has some drawbacks. For example, to control copper/oxide protrusion and copper-silicon contamination, a block layer is typically deposited after the CMP step for polishing the TSV oxide. This additional block layer causes delamination and reliability issues after packaging.
One object of the present invention is to provide an improved semiconductor device involving a through silicon via (TSV) structure that is capable of avoiding the abovementioned delamination and reliability problems.
According to one embodiment, a semiconductor device includes a substrate having a first side and a second side opposite to the first side; a through substrate via (TSV) structure protruding from a surface of the substrate on the second side; a block layer conformally covering the surface of the substrate and the TSV structure; a first dielectric layer covering the block layer except for a portion of the block layer that is directly on the TSV structure; a second dielectric layer on the first dielectric layer; and a damascened circuit pattern in the second dielectric layer. The second dielectric layer is indirect contact with the first dielectric layer. The damascened circuit pattern is in direct contact with the TSV structure.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings are exaggerated or reduced in size, for the sake of clarity and convenience. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
In the following description, numerous specific details are given to provide a thorough understanding of the invention. It will, however, be apparent to one skilled in the art that the invention may be practiced without these specific details. Furthermore, some well-known system configurations and process steps are not disclosed in detail, as these should be well-known to those skilled in the art.
Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and some dimensions are exaggerated in the figures for clarity of presentation. Also, where multiple embodiments are disclosed and described as having some features in common, like or similar features will usually be described with like reference numerals for ease of illustration and description thereof.
The terms wafer and substrate used herein include any structure having an exposed surface onto which a layer is deposited according to the present invention, for example, to form the integrated circuit (IC) structure. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.
The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
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Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
