INOTERA MEMORIES INC.

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TAOYUAN COUNTY, TW

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Patents Grantslast 30 patents

Information Patent Grant
Object carrier transport system and method of transporting object c...
- Patent number 9,618,921
- Issue date Apr 11, 2017
- Inotera Memories, Inc.
- Tsan I Chen
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method of forming patterns
- Patent number 9,613,820
- Issue date Apr 4, 2017
- Inotera Memories, Inc.
- Kuo-Yao Chou
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Semiconductor package with double side molding
- Patent number 9,613,895
- Issue date Apr 4, 2017
- Inotera Memories, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip semiconductor package with via components and method for...
- Patent number 9,607,967
- Issue date Mar 28, 2017
- Inotera Memories, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating wafer level package
- Patent number 9,576,931
- Issue date Feb 21, 2017
- Inotera Memories, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out wafer level packaging and manufacturing method thereof
- Patent number 9,576,933
- Issue date Feb 21, 2017
- Inotera Memories, Inc.
- Yi-Jen Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with sidewall-protected RDL interposer and fa...
- Patent number 9,570,369
- Issue date Feb 14, 2017
- Inotera Memories, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-device package and manufacturing method thereof
- Patent number 9,543,270
- Issue date Jan 10, 2017
- Inotera Memories, Inc.
- Shih-Fan Kuan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level package and fabrication method thereof
- Patent number 9,520,333
- Issue date Dec 13, 2016
- Inotera Memories, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and fabrication method therefor
- Patent number 9,496,358
- Issue date Nov 15, 2016
- Inotera Memories, Inc.
- Tzung-Han Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and manufacturing method thereof
- Patent number 9,472,664
- Issue date Oct 18, 2016
- Inotera Memories, Inc.
- Tieh-Chiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Probe unit for test tools and method of manufacturing the same
- Patent number 9,465,048
- Issue date Oct 11, 2016
- Inotera Memories, Inc.
- Wei-Chih Wang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Non-floating vertical transistor structure
- Patent number 9,466,713
- Issue date Oct 11, 2016
- Inotera Memories, Inc.
- Tzung-Han Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon interposer and fabrication method thereof
- Patent number 9,455,243
- Issue date Sep 27, 2016
- Inotera Memories, Inc.
- Shih-Fan Kuan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level package and fabrication method thereof
- Patent number 9,449,935
- Issue date Sep 20, 2016
- Inotera Memories, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package assembly and method for manufacturing the same
- Patent number 9,449,953
- Issue date Sep 20, 2016
- Inotera Memories, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package assembly and method for manufacturing the same
- Patent number 9,437,583
- Issue date Sep 6, 2016
- Inotera Memories, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming cell contact
- Patent number 9,419,001
- Issue date Aug 16, 2016
- Inotera Memories, Inc.
- Sheng-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Split contact structure and fabrication method thereof
- Patent number 9,401,326
- Issue date Jul 26, 2016
- INOTERA MEMORIES, INC.
- Cheng-Yeh Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure and manufacturing method thereof
- Patent number 9,397,048
- Issue date Jul 19, 2016
- Inotera Memories, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recess array device
- Patent number 9,379,197
- Issue date Jun 28, 2016
- INOTERA MEMORIES, INC.
- Tieh-Chiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sample stack structure and method for preparing the same
- Patent number 9,360,401
- Issue date Jun 7, 2016
- Inotera Memories, Inc.
- Jian-Shing Luo
- G01 - MEASURING TESTING
Information Patent Grant
Method for manufacturing high-strength structural stacked capacitor
- Patent number 9,349,736
- Issue date May 24, 2016
- Inotera Memories, Inc.
- Hai-Han Hung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic random access memory unit and fabrication method thereof
- Patent number 9,312,262
- Issue date Apr 12, 2016
- Inotera Memories, Inc.
- Tzung-Han Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing method of capacitor lower electrode and semiconductor...
- Patent number 9,299,710
- Issue date Mar 29, 2016
- Inotera Memories, Inc.
- Regan Stanley Tsui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical transistor and method to form vertical transistor contact...
- Patent number 9,257,553
- Issue date Feb 9, 2016
- Inotera Memories, Inc.
- Tzung-Han Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Overhead hoist transport system
- Patent number 9,257,317
- Issue date Feb 9, 2016
- Inotera Memories, Inc.
- Chi-Ming Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming self-aligned isolation trenches in semiconductor...
- Patent number 9,230,967
- Issue date Jan 5, 2016
- Inotera Memories, Inc.
- Tzung-Han Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Overhead buffer device and wafer transport system
- Patent number 9,209,056
- Issue date Dec 8, 2015
- Inotera Memories, Inc.
- Hang-Hao Feng
- B65 - CONVEYING PACKING STORING HANDLING THIN OR FILAMENTARY MATERIAL
Information Patent Grant
Method for increasing pattern density
- Patent number 9,184,059
- Issue date Nov 10, 2015
- Inotera Memories, Inc.
- Kuo-Yao Chou
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
FAULT ISOLATION SYSTEM AND METHOD FOR DETECTING FAULTS IN A CIRCUIT
- Publication number 20170153289
- Publication date Jun 1, 2017
- Inotera Memories, Inc.
- Wei-Chih Wang
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF
- Publication number 20170141185
- Publication date May 18, 2017
- Inotera Memories, Inc.
- Tieh-Chiang WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE AND METHOD FOR FORMING THE SAME
- Publication number 20170117232
- Publication date Apr 27, 2017
- Inotera Memories, Inc.
- Shing-Yih SHIH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL PACKAGE WITH TSV-LESS INTERPOSER
- Publication number 20170110419
- Publication date Apr 20, 2017
- Inotera Memories, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE AND FABRICATING METHOD THEREOF
- Publication number 20170069632
- Publication date Mar 9, 2017
- Inotera Memories, Inc.
- Tieh-Chiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A WAFER LEVEL PACKAGE
- Publication number 20170062240
- Publication date Mar 2, 2017
- Inotera Memories, Inc.
- Tieh-Chiang WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROSTATIC CHUCK AND TEMPERATURE-CONTROL METHOD FOR THE SAME
- Publication number 20170032989
- Publication date Feb 2, 2017
- Inotera Memories, Inc.
- Yi CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE AND FABRICATING METHOD THEREOF
- Publication number 20170033100
- Publication date Feb 2, 2017
- Inotera Memories, Inc.
- Tieh-Chiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF
- Publication number 20170033078
- Publication date Feb 2, 2017
- Inotera Memories, Inc.
- Shih-Fan KUAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECOVERABLE DEVICE FOR MEMORY BASE PRODUCT
- Publication number 20170012028
- Publication date Jan 12, 2017
- Inotera Memories, Inc.
- Tzung-Han Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF
- Publication number 20160379935
- Publication date Dec 29, 2016
- Inotera Memories, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF
- Publication number 20160372395
- Publication date Dec 22, 2016
- Inotera Memories, Inc.
- Shing-Yih SHIH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20160372475
- Publication date Dec 22, 2016
- Inotera Memories, Inc.
- Tieh-Chiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20160365334
- Publication date Dec 15, 2016
- Inotera Memories, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF
- Publication number 20160358865
- Publication date Dec 8, 2016
- Inotera Memories, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONNECTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
- Publication number 20160358868
- Publication date Dec 8, 2016
- Inotera Memories, Inc.
- Shing-Yih SHIH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
- Publication number 20160358847
- Publication date Dec 8, 2016
- Inotera Memories, Inc.
- Shing-Yih SHIH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF
- Publication number 20160358870
- Publication date Dec 8, 2016
- Inotera Memories, Inc.
- Shih-Fan KUAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FAN-OUT WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF
- Publication number 20160351462
- Publication date Dec 1, 2016
- Inotera Memories, Inc.
- Shih-Fan Kuan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE
- Publication number 20160343715
- Publication date Nov 24, 2016
- Inotera Memories, Inc.
- Tieh-Chiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESS ARRAY DEVICE WITH REDUCED CONTACT RESISTANCE
- Publication number 20160336413
- Publication date Nov 17, 2016
- Inotera Memories, Inc.
- Tieh-Chiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING BURIED WORDLINES
- Publication number 20160284640
- Publication date Sep 29, 2016
- Inotera Memories, Inc.
- Kuo-Chen Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROBE UNIT FOR TEST TOOLS AND METHOD OF MANUFACTURING THE SAME
- Publication number 20160282385
- Publication date Sep 29, 2016
- Inotera Memories, Inc.
- WEI-CHIH WANG
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD OF FABRICATING SOURCE/DRAIN REGION AND SEMICONDUCTOR STRUCTU...
- Publication number 20160133711
- Publication date May 12, 2016
- INOTERA MEMORIES, INC.
- YU NA CHOU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
- Publication number 20160104782
- Publication date Apr 14, 2016
- INOTERA MEMORIES, INC.
- TZUNG-HAN LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-FLOATING VERTICAL TRANSISTOR STRUCTURE
- Publication number 20160093732
- Publication date Mar 31, 2016
- Inotera Memories, Inc.
- TZUNG-HAN LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SAMPLE STACK STRUCTURE AND METHOD FOR PREPARING THE SAME
- Publication number 20160084742
- Publication date Mar 24, 2016
- INOTERA MEMORIES, INC.
- Jian-Shing Luo
- G01 - MEASURING TESTING
Information Patent Application
CYLINDER-SHAPED STORAGE NODE WITH SINGLE-LAYER SUPPORTING STRUCTURE
- Publication number 20150348963
- Publication date Dec 3, 2015
- INOTERA MEMORIES, INC.
- Hai-Han Hung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
- Publication number 20150349072
- Publication date Dec 3, 2015
- INOTERA MEMORIES, INC.
- TZUNG-HAN LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL TRANSISTOR AND METHOD TO FORM VERTICAL TRANSISTOR CONTACT...
- Publication number 20150349118
- Publication date Dec 3, 2015
- INOTERA MEMORIES, INC.
- TZUNG-HAN LEE
- H01 - BASIC ELECTRIC ELEMENTS

Trademarklast 30 trademarks

Information Trademark
76550468 - PL INOTERA MEMORIES
- Serial number 76550468
- Registration number 3199179
- Filing date Oct 9, 2003
- INOTERA MEMORIES, INC.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments

INOTERA MEMORIES INC.

Organization

Patents Grantslast 30 patents

Object carrier transport system and method of transporting object c...

Method of forming patterns

Semiconductor package with double side molding

Multi-chip semiconductor package with via components and method for...

Method for fabricating wafer level package

Fan-out wafer level packaging and manufacturing method thereof

Semiconductor package with sidewall-protected RDL interposer and fa...

Multi-device package and manufacturing method thereof

Wafer level package and fabrication method thereof

Semiconductor device and fabrication method therefor

Semiconductor device and manufacturing method thereof

Probe unit for test tools and method of manufacturing the same

Non-floating vertical transistor structure

Silicon interposer and fabrication method thereof

Wafer level package and fabrication method thereof

Package-on-package assembly and method for manufacturing the same

Package-on-package assembly and method for manufacturing the same

Method for forming cell contact

Split contact structure and fabrication method thereof

Semiconductor structure and manufacturing method thereof

Recess array device

Sample stack structure and method for preparing the same

Method for manufacturing high-strength structural stacked capacitor

Dynamic random access memory unit and fabrication method thereof

Manufacturing method of capacitor lower electrode and semiconductor...

Vertical transistor and method to form vertical transistor contact...

Overhead hoist transport system

Method for forming self-aligned isolation trenches in semiconductor...

Overhead buffer device and wafer transport system

Method for increasing pattern density

Patents Applicationslast 30 patents

FAULT ISOLATION SYSTEM AND METHOD FOR DETECTING FAULTS IN A CIRCUIT

SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF

SEMICONDUCTOR PACKAGE AND METHOD FOR FORMING THE SAME

WAFER LEVEL PACKAGE WITH TSV-LESS INTERPOSER

MEMORY DEVICE AND FABRICATING METHOD THEREOF

METHOD FOR MANUFACTURING A WAFER LEVEL PACKAGE

ELECTROSTATIC CHUCK AND TEMPERATURE-CONTROL METHOD FOR THE SAME

MEMORY DEVICE AND FABRICATING METHOD THEREOF

MULTI-DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF

RECOVERABLE DEVICE FOR MEMORY BASE PRODUCT

WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF

WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

PACKAGE-ON-PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME

WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF

CONNECTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

MULTI-DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF

FAN-OUT WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF

MEMORY DEVICE

RECESS ARRAY DEVICE WITH REDUCED CONTACT RESISTANCE

SEMICONDUCTOR DEVICE HAVING BURIED WORDLINES

PROBE UNIT FOR TEST TOOLS AND METHOD OF MANUFACTURING THE SAME

METHOD OF FABRICATING SOURCE/DRAIN REGION AND SEMICONDUCTOR STRUCTU...

TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

NON-FLOATING VERTICAL TRANSISTOR STRUCTURE

SAMPLE STACK STRUCTURE AND METHOD FOR PREPARING THE SAME

CYLINDER-SHAPED STORAGE NODE WITH SINGLE-LAYER SUPPORTING STRUCTURE

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR

VERTICAL TRANSISTOR AND METHOD TO FORM VERTICAL TRANSISTOR CONTACT...

Trademarklast 30 trademarks

76550468 - PL INOTERA MEMORIES