Patent Application
20240055498
The invention relates to the field of power semiconductor devices. Power semiconductor devices that are able to withstand a blocking voltage of several hundred Volts at high current rating are typically implemented as vertical structures, wherein the semiconductor wafer is based for example on a semiconducting material such as silicon (Si) or silicon carbide (SiC) or diamond or gallium oxide (Ga2O3) or gallium nitride (GaN).
Planar and Trench MOS cell designs exhibit a number of advantages and disadvantages for IGBT and MOSFET designs. For IGBTs, typical Planar and Trench designs are shown in
A planar gate electrode (10) is arranged on top of the emitter side (31). The planar gate electrode (10) is electrically insulated from the planar base layer (9), the planar source region (7) and the drift layer (4) by a planar insulating layer (12). There is a further insulating layer (13) arranged between the planar gate electrode (10) and the emitter electrode (3).
The planar cell concept offers a lateral MOS channel (15) which suffers from non-optimal charge spreading (so called JFET effect) near the cell resulting in low carrier enhancement and higher conduction losses. Furthermore, due to the lateral channel design, the planar cell design suffers also from the PNP bipolar transistor hole drain effect (PNP effect) due to the bad spreading of electrons flowing out of the MOS channel. However, the accumulation layer between the MOS cells offers strong charge enhancement for the PIN diode part (PIN effect). The planar design also requires more area resulting in less cell packing density for reduced channel resistance.
On the other hand, the planar design provides good blocking capability due to low peak fields at the cell and in between. The planar design can also provide good controllability and low switching losses due to the presence of direct path to extract the bipolar charge stored between the MOS cells (50) near the emitter side (31). The cell densities in planar designs are also easily adjusted for the required short circuit currents. Due to the fact that there exist few high peak electric fields in the gate oxide regions, the planar design offers good reliability with respect to parameter shifting during operation under high voltages. Also, the introduction of enhanced layers in planar cells has resulted in lower losses rivalling those achieved with trench designs as explained below.
The trench cell concept for a trench IGBT 300 shown in
Due to the vertical channel design, the trench also offers less hole drain effect (PNP effect) due to the improved electron spreading out of the MOS channel. Modern trench designs adopting mesa widths (trench to trench distance) below 1 μm achieve very low conduction losses since closely packed trenches can provide a strong barrier to hole drainage. Matching such a performance with less complex processes can be of a great advantage. The accumulation layer at the bottom of the trench offers strong charge enhancement for the PIN diode part. Hence wide and/or deep trenches show optimum performance. Furthermore, the trench design offers large cell packing density for reduced channel resistance.
However, the trench design suffers from lower blocking capability near the bottom corners of the trenches due to high peak electric fields. This has also resulted in parameter shifting during operation due to hot carrier injection into the trench gate oxide (12′). The trench design has also a large MOS accumulation region and associated capacitance resulting in bad controllability and high switching losses. The high cell densities in trench designs will also result in high short circuit currents. Finally, gate parameter shifts can occur under normal gate biasing stress conditions due to the trench etch process in relation to the silicon crystal orientation and the critical region at the n-source and p-base junction which is formed at the trench gate oxide (12′) and defines the device MOS parameters.
Hence, optimising the trench design to overcome the above drawbacks has normally resulted in higher losses when compared to the initial loss estimations and potential of trench designs. Many trench designs have been proposed with particular focus on the regions between the active MOS cells for lowering the losses and improving the device controllability.
By way of example,
By way of example,
In further prior art, an alternative approach was disclosed that proposed an arrangement of non-contacting orthogonal first and second gate trenches. This approach has multiple limitations, for example it is difficult to reduce the distance between adjacent gate trenches to submicron dimensions, because additional source regions and base layers must be formed between two adjacent gate trenches (both for first and second gate trenches). A highly doped base layer extends uniformly between the source regions, along the long edge of the second gate trenches. The emitter electrode is extended uniformly over the first main surface of the device, contacting the highly doped base layer, which can lead for example to safe operating area issues or increased hole drainage effect.
It is desirable to find a new MOS cell design concept that can still benefit from the trench cell concept while enabling simple process steps and lower conduction/on-state losses.
It may be an object of the present invention to provide a power semiconductor device with reduced on-state losses, low drainage of holes, stable gate parameters, improved blocking capability, and good controllability such as an Insulated Gate Bipolar Transistor (IGBT) with improved electrical characteristics.
According to a first aspect of the invention we herein describe a power semiconductor device comprising: a drift region of a first conductivity type comprising a first surface and a second surface separated in a first dimension, wherein the first surface and second surface are parallel surfaces; a first electrode located at the first surface; a second electrode located at the second surface; a first base layer of a second conductivity type located between the first electrode and the drift region; a source region of the first conductivity type located within the first base layer and electrically connected to the first electrode via a contact opening, wherein a doping concentration of the source region is greater than a doping concentration of the drift region; a second base layer of the first conductivity type located within the first base layer and electrically connected to the first electrode via the contact opening, wherein a length of the second base layer in the first dimension is greater than a length of the source region in the first dimension, and wherein a doping concentration of the second base layer is greater than a doping concentration of the first base layer; a plurality of first gate electrodes of a heavily doped polycrystalline layer or a metal layer and located within the first base layer and the drift region, wherein: the first gate electrode is electrically insulated from the first base layer, the source region, and the drift layer by a first gate oxide layer; the first gate electrode is configured to form an MOS channel in the first dimension between the first electrode and the drift region; and wherein the first gate electrode extends in a second dimension perpendicular to the first dimension; a plurality of second gate electrodes of a heavily doped polycrystalline layer or a metal layer and located within the first base layer and the drift region, wherein: the second gate electrodes are electrically insulated from the first base layer, the source region, and the drift layer by a second gate oxide layer; the second gate electrodes extend in a third dimension perpendicular to the first dimension, wherein the third dimension is oriented at an angle of greater than or equal to 45 degrees from the second dimension; and the second gate electrodes are separated from the first gate electrode in the third dimension; an interlayer dielectric layer formed between the first electrode and the first gate electrode and formed between the first electrode and the second gate electrodes; and wherein the contact opening is arranged between the first gate electrode and the second gate electrodes.
It will be understood that the first dimension generally relates to the direction of the separation of the first (emitter) and second (collector) electrodes. Similarly, the second dimension relates to the longitudinal direction or length of the first (main) gate electrode, and the third dimension relates to the longitudinal direction or length of the second gate electrodes. Generally, both the second and third dimensions are perpendicular to the first dimension. Additionally, the third dimension may be at an angle of between 45 degrees and 90 degrees to the second dimension.
A separation between adjacent second gate electrodes in the second dimension may be between 5 μm to 0.1 μm. For example, the separation between adjacent second gate electrodes in the second dimension is less than 1 μm. A separation between the first gate electrode and the second gate electrodes in the third dimension may be between 20 μm and 0.5 μm. For example, the separation may be less than 5 μm or less than 2 μm.
In a further embodiment the first gate electrodes may each be located in a respective first trench structure and/or the second gate electrodes may each be located in respective parallel second trench structures. At least two of the second trench structures may be separated in the third dimension by the first trench structure. In other words, at least two of the second trench structures may be formed on opposite sides of the first trench structure.
In a further embodiment, at least two of the second trench structures have an equal length in the third dimension.
In a further embodiment, at least two adjacent second trench structures have different lengths in the third dimension.
In a further embodiment, at least two of the second trench structures have different separations to the first gate electrode in the third dimension.
In a further embodiment, at least two of the second trench structures have an equal depth in the first dimension.
In a further embodiment, at least two adjacent second trench structures have different depths in the first dimension.
In a further embodiment, at least one of the second trench structures has a greater depth in the first dimension than the first trench structure.
In a further embodiment, at least two of the second trench structures have an equal width in the second dimension.
In a further embodiment, at least two adjacent second trench structures have different widths in the second dimension.
In a further embodiment, at least one of the second trench structures has a greater width in the second dimension than a width of the first trench structure in the third dimension.
In some embodiments, the second gate oxide layer may be identical to the first gate oxide layer. Alternatively, the first and second oxide layers may be different. For example, they may have a different thickness and/or chemical composition.
In some embodiments, a MOS channel is formable in the first dimension around the second gate electrodes. Alternatively, the first and second gate electrodes may be electrically connected, and no MOS channel is formable in the first dimension on the surface of the second gate electrodes.
In a further embodiment, all or some of the second gate electrodes may be electrically connected to the first electrodes. Additionally, or alternatively, all or some of the second gate electrodes may be electrically floating.
In another embodiment, some or all of the second gate electrodes may be interconnected on the first side via a third gate electrode located above the first surface. Optionally, the third gate electrode may be located above the drift region and not be in a trench structure. The device may further comprise an insulating layer located beneath the third electrode, wherein at least part of the third electrode is separated from the drift region by only the insulating layer. By forming the third electrode above an N-source region, a planar or horizontal MOS channel may be formed.
The power semiconductor device may further comprise at least one of: a collector layer of the second conductivity type formed between the drift region and the second electrode; and a buffer layer of the first conductivity type formed between the drift region and the second electrode, wherein a doping concentration of the buffer layer is greater than a doping concentration of the drift region. Optionally, if the device comprises both the buffer layer and the collector layer, the buffer layer may be formed between the collector layer and the second electrode.
In some embodiments, the device may further comprise a reverse conducting type device with a shorted collector layer arranged at the second surface between the second electrode and the buffer layer, wherein the shorted collector layer is formed by a pattern of opposite conductivity type regions.
In a further embodiment, an enhancement layer of the first conductivity type may be located between the drift region and the first base layer.
The power semiconductor device may have a stripe layout design or a cellular layout design.
According to a second aspect of the invention, it is described a semiconductor module package comprising one or more power semiconductor devices comprising: a drift region of a first conductivity type comprising a first surface and a second surface separated in a first dimension, wherein the first surface and second surface are parallel surfaces; a first electrode located at the first surface; a second electrode located at the second surface; a first base layer of a second conductivity type located between the first electrode and the drift region; a source region of the first conductivity type located within the first base layer and electrically connected to the first electrode via a contact opening, wherein a doping concentration of the source region is greater than a doping concentration of the drift region; a second base layer of the first conductivity type located within the first base layer and electrically connected to the first electrode via the contact opening, wherein a length of the second base layer in the first dimension is greater than a length of the source region in the first dimension, and wherein a doping concentration of the second base layer is greater than a doping concentration of the first base layer; at least one first gate electrode of a heavily doped polycrystalline layer or a metal layer and located within the first base layer and the drift region, wherein: the first gate electrode is electrically insulated from the first base layer, the source region, and the drift layer by a first gate oxide layer; the first gate electrode is configured to form an MOS channel in the first dimension between the first electrode and the drift region; and wherein the first gate electrode extends in a second dimension perpendicular to the first dimension; a plurality of second gate electrodes of a heavily doped polycrystalline layer or a metal layer and located within the first base layer and the drift region, wherein: the second gate electrodes are electrically insulated from the first base layer, the source region, and the drift layer by a second gate oxide layer; the second gate electrodes extend in a third dimension perpendicular to the first dimension, wherein the third dimension is oriented at an angle of greater than or equal to 45 degrees from the second dimension; and the second gate electrodes are separated from the first gate electrode in the third dimension; an interlayer dielectric layer formed between the first electrode and the first gate electrode and formed between the first electrode and the second gate electrodes; and wherein the contact opening is located between the first gate electrode and the second gate electrodes.
According to a third aspect of the invention, it is described a converter with a plurality of power semiconductor devices comprising: a drift region of a first conductivity type comprising a first surface and a second surface separated in a first dimension, wherein the first surface and second surface are parallel surfaces; a first electrode located at the first surface; a second electrode located at the second surface; a first base layer of a second conductivity type located between the first electrode and the drift region; a source region of the first conductivity type located within the first base layer and electrically connected to the first electrode via a contact opening, wherein a doping concentration of the source region is greater than a doping concentration of the drift region; a second base layer of the first conductivity type located within the first base layer and electrically connected to the first electrode via the contact opening, wherein a length of the second base layer in the first dimension is greater than a length of the source region in the first dimension, and wherein a doping concentration of the second base layer is greater than a doping concentration of the first base layer; at least one first gate electrode of a heavily doped polycrystalline layer or a metal layer and located within the first base layer and the drift region, wherein: the first gate electrode is electrically insulated from the first base layer, the source region, and the drift layer by a first gate oxide layer; the first gate electrode is configured to form an MOS channel in the first dimension between the first electrode and the drift region; and wherein the first gate electrode extends in a second dimension perpendicular to the first dimension; a plurality of second gate electrodes of a heavily doped polycrystalline layer or a metal layer and located within the first base layer and the drift region, wherein: the second gate electrodes are electrically insulated from the first base layer, the source region, and the drift layer by a second gate oxide layer; the second gate electrodes extend in a third dimension perpendicular to the first dimension, wherein the third dimension is oriented at an angle of greater than or equal to 45 degrees from the second dimension; and the second gate electrodes are separated from the first gate electrode in the third dimension; an interlayer dielectric layer formed between the first electrode and the first gate electrode and formed between the first electrode and the second gate electrodes; and wherein the contact opening is located between the first gate electrode and the second gate electrodes.
The embodiments of the invention will be explained in more detail in the following text with reference to the attached drawings, in which:
The reference symbols used in the figures and their meaning are summarized in the list of reference symbols. The drawings are only schematically and not to scale. Generally, alike or alike-functioning parts are given the same reference symbols. The described embodiments are meant as examples and shall not confine the invention.
We herein describe a power semiconductor device having layers of different conductivity types, which layers are arranged between an emitter electrode on an emitter side and a collector electrode on a collector side, which is arranged opposite of the emitter side. The layers comprise:
When a positive voltage is applied on the main and second gate electrodes, a vertical channel can be formable between the emitter electrode, the first source region, the first base layer and the drift layer along the short and long edges of the first and second trench gates.
The second base layer is structured to not fully cover the long edge of the second gate trenches. Instead, the second base layer and the contact openings of the emitter electrode are formed so as to be encompassed roughly within the separation distance between the long edge of the main gate trench recess, and the short edge of its nearest second gate trench recesses. This ensures a particularly robust switching capability for the power semiconductor, while reducing the hole drainage effect.
The semiconductor device improves a Trench MOS cell in order to gain the advantages of both designs in terms of reduced on-state losses, low drainage of holes, stable gate parameters, improved blocking and good controllability.
Due to the fact that the area in between the second trench gate structures does not need to be further structured, very high-density trench patterns can be used, with trench mesa dimensions below 100 nm. This will significantly reduce the hole drainage effect as well known to those experts in the field.
In addition, for discontinued second gate trenches at the main trench cells, the trench mesa dimension can be reduced to 1 μm for further reducing the hole drainage effect while keeping the trench cell dimensions larger than 1 μm.
Some or all of the plurality of second gate electrodes can be directly connected to the main gate electrodes, or can be directly connected to the emitter electrode, or made floating. If the second gate electrodes are shorted to the emitter electrode, there is no voltage differential between the second gate electrodes and effectively no capacitance. Since the second gates do not invert the first base region, the cell containing the second gate is a passive type of cell, as opposed to an active cell controlled by the gate trenches. By controlling the number of passive cells, the input capacitance of the device can be precisely controlled.
Similarly, if the second gate electrodes are floating, resulting in a passive cell, the potential floats up to the emitter voltage so there is effectively no capacitance associated with the second gates.
The new design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability), and processability (very narrow mesa design rules, reliable process compatibility) with the potential of applying enhanced layer structures. The inventive design is suitable for full or part stripes but can also be implemented in cellular designs.
The inventive design is also suitable for reverse conducting structure and can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as Silicon Carbide (SiC).
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and on viewing the accompanying drawings.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same references in the different drawings if not stated otherwise.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, e. g., those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art. However, should the present disclosure give a specific meaning to a term deviating from a meaning commonly understood by one of ordinary skill, this meaning is to be taken into account in the specific context this definition is given herein.
In this specification, N-doped is referred to as first conductivity type while P-doped is referred to as second conductivity type. Alternatively, the semiconductor devices can be formed with opposite doping relations so that the first conductivity type can be P-doped and the second conductivity type can be N-doped.
Specific embodiments described in this specification pertain to, without being limited thereto, insulated gate bipolar semiconductor devices.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e. g. “between” versus “directly between”, “adjacent” versus “directly adjacent,” etc.).
A first exemplary embodiment of a power semiconductor device (1) in form of a punch through insulated gate bipolar transistor (IGBT) with a four-layer structure (pnpn) is shown as top view representation in
An additional P-doped first base layer (9) is arranged between the drift layer (4) and the emitter electrode (3), and a second P-doped base layer (8) is arranged between the first base layer (9) and the emitter electrode (3), which second base layer (8) is in direct electrical contact to the emitter electrode (3), and has a higher doping concentration than the first base layer (9). An N-doped source region (7) is arranged at the emitter side (31) embedded into the first base layer (9), and contacts the emitter electrode (3), which source region has a higher doping concentration than the drift layer (4). The second base layer (8) extends perpendicularly deeper than the source region (7).
A plurality of main gate electrodes is arranged in trench structures (11), which are formed on the surface of the emitter side (31) and extend deeper into the drift layer (4) than the first base layer (9). The main gate electrodes (11) consist of a heavily doped polycrystalline layer or a metal-containing layer and are electrically insulated from the first base layer (9), the source region (7) and the drift layer (4) by a first insulating layer (12′). The first insulating layer (12′) may be a gate oxide layer. A vertical MOS channel (16) is formable between the emitter electrode (3), the source region (7), the first base layer (9) and the drift layer (4) when positive voltage is applied on the gate electrodes (11). The longitudinal direction of the main gate electrodes (11) is along a first horizontal direction (in a top plane view) which can be specific to a geometric axis in the starting material or can be randomly selected. The selection of the longitudinal direction may help to improve other characteristics of the power semiconductor.
According to a first embodiment, a plurality of second gate electrodes embedded in trench structures (18), is also arranged on the surface of the emitter side (31) and extend deeper into the drift layer (4) than the first base layer (9). The second gate electrodes are electrically insulated from the first base layer (9), and the drift layer (4) by a second insulating layer. Similarly to the first insulting layer (12′), the second insulating layer may be a gate oxide layer. The second insulating layer is characterized in that the second gate oxide can be identical with the first gate oxide (12′) or can be different in thickness and/or chemical composition. The second gate electrodes can be geometrically identical to the main gate electrodes, or can have different widths/depth/mesa. In a typical top plane view, the second gate electrodes (18) are arranged with their longitudinal axis at an angle between 45 degrees to 90 degrees compared to the longitudinal direction of the first gate electrodes (11) also defined above as first horizontal direction. Depending on the design, the second gate electrodes can be discontinued in the region of the main gate electrodes (11). A vertical channel can be formable on the surface of the second gate trenches between the emitter electrode (3), source region (7), the first base layer (9) and the drift layer (4), but it is not mandatory to the principle of this invention.
Further, an interlayer dielectric (13) electrically insulates the emitter electrode (3) from the gate electrodes (11) and (18) and may include by way of example one or more dielectric layers from silicon oxide, silicon nitride, silicon oxynitride, doped or undoped silicate glass, for example BSG (boron silicate glass), PSG (phosphorus silicate glass) or BPSG (boron phosphorus silicate glass).
In a first embodiment, a P-doped collector layer (6) is arranged on the collector side (2) in direct electrical contact to the collector electrode (2) and a buffer layer (5) is arranged between the collector layer (6) and the drift region (4). Layers (5) and (6) can also be omitted in other embodiments (e.g., unipolar MOSFET device, non-punch-through power semiconductor devices).
The trench regions can be better viewed in the top cell view shown in
According to the first embodiment, second gate electrodes in second trench gate structures (18) are arranged in between the main gate electrodes trenches (11), at an angle between 45 degrees to 90 degrees with respect to the first horizontal direction (or the longitudinal direction of the main gate electrodes (11)). By means of example, only the 90 degrees case, e.g., trench structures (11) and (18) are orthogonal to each other, is shown in
With respect to the top view shown in
The trenches embedding the main and second gate electrodes (11 and 18) extend in the direction of the drift layer (4) deeper than the first base layer (9). More specifically, the trench extends vertically to a depth approximately in a range from about 2 μm to about 10 μm. The trench width may range from about 4 μm to about 0.5 μm. The length of the second gate electrode trenches (18) can vary on the same structure with some of the trenches being shorter in length than the rest.
As a unique feature of the first embodiment, the second base layer (8) is structured to limit its extension in the direction of the long edge of the second gate trenches. Both the contact openings (14), and the second base layer (8) are encompassed within the distance WMESA. This reduces the hole drainage effect, and improves the safe operating area.
In a second embodiment represented as schematic top view in
In a further fourth embodiment represented as schematic top view in
In a further fifth embodiment shown in
The inventive design is also suitable for a reverse conducting semiconductor device by introducing N-type dopants at the collector side to form shorts in the P-type collector layer (6), and producing an internal anti-parallel diode structure.
A further embodiment includes the use of an enhancement layer of lightly doped N-type conductivity, implanted and diffused in the semiconductor device. The dopants are preferably Phosphorous ions. The dopants are preferably implanted with an energy of 20-100 keV and/or a dose of 5×1012/cm2 to 5×1013/cm2. The dopants are driven into a maximum depth between 2 μm and 8 μm, in particular between 2 and 6 μm and in particular between 2 and 4 μm. With this enhancement layer, the conduction losses of the semiconductor device are improved.
It is possible to apply the invention to a method for the manufacturing of semiconductor devices, in which the conductivity type of all layers is reversed, i.e. with a lightly p doped substrate etc.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1914275.1 | Oct 2019 | GB | national |
This application claims the benefit of PCT Application Serial No. PCT/EP2020/077744, filed Oct. 2, 2020, entitled “SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME”, which claims the benefit of G.B. Application Serial No. 1914275.1, filed Oct. 3, 2019, entitled “SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME”. The entirety of these applications are hereby incorporated by reference for all purposes.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2020/077744 | 10/2/2020 | WO |
