1. Field of the Invention
The present invention relates to a semiconductor device structure having an interlayer dielectric film made of a resinous material. The invention also relates to a method of fabricating such a semiconductor device structure.
2. Description of the Related Art
Techniques for fabricating thin-film transistors (TFTs), using a thin film semiconductor formed on a glass substrate or quartz substrate, have been known.
The prior art steps for fabricating a TFT are shown in
First, a silicon oxide film is formed as a buffer layer 302 on a substrate 301 of glass or quartz to a thickness of 3000 Å by plasma CVD. Then, an amorphous silicon film (not shown) is formed to a thickness of about 500 to 1500 Å by plasma CVD or LPCVD. This amorphous film acts as a starting film in forming an active layer of TFTs. Subsequently, the amorphous silicon film (not shown) is heat-treated or illuminated with laser light to crystallize the amorphous film. In this way, a crystalline silicon film (not shown) is obtained.
Then, this crystalline silicon film is patterned to form regions (303, 304, 305 in
Then, a first dielectric film 308 is formed from silicon nitride or silicon oxide to a thickness of 2000 to 6000 Å by plasma CVD. Subsequently, contact holes are formed. A source electrode and interconnects, 309, extending from it are formed from an appropriate metal material (
Then, a second interlayer dielectric film 310 is formed from silicon oxide or silicon nitride. The thickness of this second interlayer dielectric film is set greater than 7000 Å to assure that the surface is sufficiently flat. Then, a contact hole 311 is formed, thus obtaining a state shown in
Thereafter, an ITO electrode 312 forming a pixel electrode is formed. In consequence, a TFT disposed in the pixel region of the active matrix regions is completed. During these fabrication steps, the formation of the pixel electrode 312 presents the following problems.
In recent years, the sizes of conductor patterns and TFT patterns have tended to diminish, because there is an increasing demand for increased device densities. Furthermore, active matrix liquid crystal displays are required to reduce such patterns to increase the aperture ratio of pixels.
As such patterns are reduced in size, it is, of course, necessary to reduce the size of the window hole 311. However, if the contact hole 311 is reduced in size, the material, or ITO, of the pixel electrode 312 does not form a film with good coverage within the small hole. As a result, it is difficult to make required contacts. In particular, the contact hole is elongated. The material for making a contact may break inside the hole. As a consequence, poor contact takes place.
It is an object of the present invention to provide techniques for solving problems associated with poor contact caused as finer-line patterns are utilized.
An embodiment of the present invention described herein is shown in
The use of this structure permits finer-line geometries. Even if the contact area decreases, it is assured that contact to a source region 110 is made by an electrode 120 consisting of a metallization level. Furthermore, this metallization level 120 is prevented from breaking, by tapering the overetched portion 100.
Moreover, the planarity of the surface is assured by forming the top layer 117 from a resinous material. Therefore, the electric field applied from the pixel electrode is not disturbed.
Another embodiment of the invention is a method of fabricating a semiconductor device. This method is illustrated in
By etching only the resinous material selectively, the window hole 119 is widened and assumes a form which facilitates making a contact. Furthermore, the tapering portion 100 can be formed by the use of isotropic etching. Hence, electrodes and conductors formed over the tapering portion 100 do not break. The aforementioned silicide (silicon-containing dielectric) can be silicon oxide, silicon nitride, or silicon oxynitride.
The present example pertains to steps for fabricating TFTs arranged in pixel regions of an active matrix liquid crystal display.
Then, the amorphous silicon film (not shown) is crystallized by illuminating it with laser light or heat-treating it. Thus, a crystalline silicon film is obtained. This crystalline silicon film will form the active layer of the TFT later.
Thereafter, the crystalline silicon film (not shown) is patterned to form the active layer 103 of the TFT. In this way, a state shown in
Then, a silicon oxide film 104 acting as a gate-insulating film is formed to a thickness of 1000 Å by plasma CVD as shown in
The subsequent steps will be described by referring to
After the formation of the aluminum film 105, an extremely thin anodic oxide film (not shown) about 100 Å thick is formed on the surface of the aluminum film, using an electrolytic solution prepared by neutralizing 3% ethylene glycol solution with aqueous ammonia. The thickness of this anodic oxide film can be controlled by controlling the applied voltage.
Then, as shown in
Then, a dense anodic oxide film is again formed. That is, an electrolytic solution prepared by neutralizing 3% ethylene glycol solution with aqueous ammonia is used. Anodization is effected, using the gate electrode 106 as an anode.
As a result of this anodization step, a dense anodic oxide film 108 is formed to a thickness of 500 Å. During this step, the electrolytic solution enters into the porous anodic oxide film 107 and so the dense anodic oxide film 108 is formed so as to cover the surface of the gate electrode 106. The anodic oxide film 108 prevents formation of hillocks and whiskers and will contribute to formation of offset gate regions. In this way, a state shown in
Then, the porous anodic oxide film 107 is removed, giving rise to a state shown in
Subsequently, as shown in
Then, contact holes leading to the source region 109 are formed. A source electrode and conductive interconnects 115 extending from the source electrode are formed from an appropriate metal material.
Thereafter, a third dielectric film 117 is formed from a resinous material to a thickness of 3 μm. It is important that the third interlayer dielectric film 117 is made from a resinous material, because it is necessary that the surface be flat and that the material have a low relative dielectric constant.
The necessity of the above-described flatness is associated with the fact that pixel electrodes are formed on the surface. Specifically, where the pixel electrodes are formed on a planar surface, the electric field applied to the liquid crystal material is made uniform, whereby the image is displayed without any disturbance. For this purpose, the aforementioned third interlayer dielectric film must be flat.
Since a resinous material having a relative dielectric constant lower than those of silicon oxide and silicon nitride can be selected, the effect of capacitances created between each pixel electrode and TFT formed later can be reduced. This also makes the usage of a resinous material important. After the third interlayer dielectric film 117 of the resinous material is formed, a contact hole or window hole 119 is formed by dry etching, using photoresist 118 as a mask (
For example, it is necessary that the contacts have a diameter of 1 μm or less. However, the contact hole 119 is elongated. This renders it difficult to make a direct contact with the drain region 110. Accordingly, in the present example, during the step shown in
In the present example, it is to be noted that this isotropic etching is done after the photoresist 118 is removed. That is, the fact that the resinous material can be easily etched selectively in an oxygen ambient is utilized.
As a result of this step, only the portion of the third interlayer dielectric film 117 of the resinous material which is located over the contact hole 119 is etched away, thus enlarging the entrance to the hole. As a result, a widened contact hole 201 is created (
At this time, the third interlayer dielectric film 117 of the resinous material decreases in thickness. Since the interlayer dielectric film 117 is recessed isotropically, the edge portion 100 of the opening is tapered or rounded. Because of this geometry, a metallization or electrode level which will be formed for making contacts does not become discontinuous around their edges. The diameter of the contact hole 201 can be set to 2 μm, for example. In this way, a state shown in
Then, as shown in
The opening in the contact hole 201 can be enlarged and, consequently, even if the pattern is made finer, the contact between the pixel electrode 202 and the drain region 110 can be rendered more reliable. In this manner, a TFT arranged in a pixel region of an active matrix liquid crystal as shown in
The present example is similar to Example 1 described already except that the buffer layer 102 and the gate-insulating film 104 are both made of silicon oxynitride (SiOxNy). The state of the interface between the active layer 103 of semiconductor and the surrounding portion (i.e., the buffer layer 102 and the gate-insulating film 104) greatly affects the operation of the TFT.
Generally, a silicon oxide film or the like is used as a buffer layer. However, any special attention is not paid to the quality of the film. On the other hand, with respect to a gate-insulating film, much attention has been given to it, because it is considered that the gate-insulating film greatly affects the characteristics of the TFT.
Our findings reveal that it is necessary to pay much attention to the quality of the buffer layer underlying an active layer, as well as to the gate-insulating film, because the quality of the buffer layer materially affects the long-term reliability of the TFT.
In the present example, the buffer layer and the gate-insulating film are made of silicon oxynitride which is electrically stable. As a result, reliable TFTs can be obtained.
The silicon oxynitride films can be formed by plasma CVD, using TEOS gas to which N2O gas is added. Furthermore, the silicon oxynitride films can also be formed by plasma CVD, using mixture gas of oxygen and ammonia.
The present example pertains to separate technical means for widening window holes formed in an interlayer dielectric film made of a resinous material.
A method of forming window holes in accordance with the present example is illustrated in
After forming the first dielectric film 401, a second interlayer dielectric film 402 is formed from a resinous material on the first dielectric film. Then, a mask 403 of photoresist is formed on the second interlayer dielectric film 402. This resist mask 403 is provided with a window hole 404 to expose the second interlayer dielectric film 402 of the resinous material (
Then, the first interlayer dielectric film 401 and the second interlayer dielectric film 402 are etched, using the resist mask 403, to form a window hole 405. This etching is performed by dry etching making use of RIE. During this etching step, vertically anisotropic etching takes place and so the window hole 405 is formed (
Then, oxygen plasma ashing which is an isotropic etching technique is carried out to ash the resist mask 403 and the second interlayer dielectric film 402. At this time, the resist mask decreases in thickness. At the same time, the window hole is tapered or rounded. Furthermore, the window hole in the second dielectric film is also tapered or rounded as indicated by 406, since it is made from a resinous material.
At this time, unlike the method described in Example 1, the second interlayer dielectric film made from a resinous material does not decrease in thickness. Instead, the resist mask 403 is thinned. In this way, a state shown in
The present example relates to another technical means for widening a window hole formed in an interlayer dielectric film made from a resinous material.
Referring to
Then, as shown in
Then, the thin metal film 606 is selectively etched while masking it with photoresist 607. This etching is performed by dry etching techniques, using SiCl4, Cl2, and BCl3 as etchant gases. The gas pressure is 80 mtorr. The applied electric power is 1400 W. As a result of these steps, a state shown in
Then, as shown in
In this way, contacts of the active layer 601 are exposed, as shown in
Under the condition of
At this time, the thin metal film 606 adheres well to the third interlayer dielectric film 605. Preferably, the selectivity of the third interlayer dielectric film 605 with respect to the underlying other dielectric films (i.e., the gate-insulating film 602, the first interlayer dielectric film 603, and the second interlayer dielectric film 604) is 5 or more.
Where the above-described condition is satisfied, a shape as shown in
Conversely, if the selectivity is small although the adhesion is good, then the sidewalls of all the dielectric films are simultaneously etched, as shown in
After obtaining the state of
The present example is characterized in that a window hole shaped so as to facilitate making contacts is formed, by utilizing the side etching of the third interlayer dielectric film 605 made from a resinous material. The present example is also characterized in that these steps beginning with the step of etching the third interlayer dielectric film 605 of the resinous material under the condition of
More specifically, if these steps are all performed by dry etching techniques, contact holes can be formed without exposing the system to atmosphere by automatically modifying the etchant gas conditions and other conditions by a computer program. This is of importance, because the throughput is improved and, at the same time, the production yield is improved.
The present example is similar to EXAMPLE 4 except that a dielectric film of silicide (a dielectric film containing silicon) is formed instead of the thin metal film. The dielectric film of silicide (the dielectric film containing silicon) is easier to etch off and handle than the thin metal film. Therefore, the dielectric film of silicide (the dielectric film containing silicon) can find wider application.
Examples of the silicide of the dielectric film include silicon oxide, silicon nitride, and silicon oxynitride (SiOxNy). These dielectric films are formed by plasma CVD, LPCVD, or other means. Furthermore, the films may be formed by spin coating, using a silicon oxide-based liquid applied to form a coating, typified by PSG and BSG. The spin coating is carried out in the sequence described below.
First, the liquid is applied to a base. Then, a stage holding the base is rotated. As a result of this step, excess liquid is fully removed. A thin uniform film is formed on the base. The thickness of the film can be set to a desired value by changing the rotational speed of the stage.
Then, the film is baked at about 150° C. to crystallize the applied film. At this time, the quality of the film can be adjusted by varying the baking temperature and baking time. As described thus far, where spin coating is utilized, a silicon oxide film can be formed with relative ease. That is, the throughput can be enhanced greatly.
In the present example, an integrated circuit having multilevel metallization is built by making use of the present invention. Integrated circuits using single-crystal silicon wafers are required to have multilevel devices and multilevel metallization to increase the device density. This multilayer structure is also required to make contacts certainly. The invention assures making contacts even in fine-line multilevel integrated circuits.
Then, a dielectric film 802 made of a silicide (a dielectric film containing silicon) is formed over the first metallization layer 801. A dielectric film 803 is formed from a resinous material on the dielectric film 802. The lamination of the dielectric films 802 and 803 acts as a first interlayer dielectric film.
Thereafter, a contact hole 804 is formed in the first dielectric film, thus obtaining a state shown in
Then, a second metallization layer 805 is formed, thus obtaining a state shown in
Subsequently, contact holes 808 are formed in the second interlayer dielectric film, thus obtaining a state shown in
Then, a third metallization layer 809 is formed, resulting in a state shown in
As described thus far, every layer can be planarized by utilizing the present invention described herein. Furthermore, contacts can be made reliably. In addition, the reliability of wiring can be enhanced.
The present example is an example in which an integrated circuit having multilevel metallization is built, by exploiting the present invention. This example is similar to Example 5 except that different metallization levels are partially connected to each other by making use of selective growth of tungsten (W). Tungsten (W) selective growth technology has attracted attention in recent years as a metallization formation technique, especially as a microlithography technique for it. Briefly, this technique consists of selectively forming a thin film of W by a thermal CVD process, using WF6 and SiH4 as main gaseous raw materials. This technique has the feature that the thin film is not readily formed on a silicon oxide film. That is, only the inside of the contact holes formed in the silicon oxide film can be selectively filled with W. Therefore, this technique has the advantage that greater margin can be imparted to the contact holes in integrated circuit design.
However, this process is carried out at relatively high temperatures and so it is often difficult to fabricate interlayer dielectric films from resinous materials. Furthermore, where deep contact holes are filled with W, the throughput deteriorates. Accordingly, where the present invention is practiced, using a resin as the material of an interlayer dielectric film after the final high-temperature heating step, the circuit is built advantageously. For example, shallow contact holes are filled by selective growth of W. If deep contact holes are necessary, the present invention may be exploited, by previously using a resin finding wide application as the material of an interlayer dielectric film.
The present example relates to a further technical means for widening window holes formed in an interlayer dielectric film made from a resinous material. This method is illustrated in
Then, a second interlayer dielectric film 402 made of a resinous material is formed on the first interlayer dielectric film 401. A mask 403 of photoresist is formed on the second interlayer dielectric film 402. The resist mask 403 has a window hole 404 to expose the second interlayer dielectric film 402 in this portion (
Thereafter, the first interlayer dielectric film 401 and the second interlayer dielectric film 402 are etched, using the resist mask 403, thus obtaining a window hole 405. This etching is performed by dry etching making use of RIE. During this etching step, vertically anisotropic etching takes place and so the window hole 405 is formed (
Then, oxygen plasma ashing which is an isotropic etching technique is carried out to ash the resist mask 403 and the second interlayer dielectric film 402. At this time, the resist mask decreases in thickness. At the same time, the window hole is tapered or rounded. Furthermore, the window hole in the second dielectric film is also tapered or rounded as indicated by 406, since the second dielectric film is made from a resinous material.
At this time, unlike the method described in Example 1, the second interlayer dielectric film made from a resinous material does not decrease in thickness. Instead, the resist mask 403 is thinned. After the ashing, a dry etching step is again carried out to widen the window hole in the first interlayer dielectric film 401 of silicon oxide or silicon nitride. The widened window hole assumes a tapering shape as indicated by 901. In this way, a state shown in
According to the present invention, the opening in the contact hole is widened as indicated by 201 in
The invention disclosed herein is applied not only to active matrix liquid crystal displays but also to active matrix EL displays and active matrix plasma displays. The invention can also be applied with sufficient utility to multilevel structures such as used in integrated circuits (ICs) consisting of components which have been down-sized.
Number | Date | Country | Kind |
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7-332630 | Nov 1995 | JP | national |
7-345631 | Dec 1995 | JP | national |
Number | Date | Country | |
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Parent | 09946733 | Sep 2001 | US |
Child | 10819964 | US |
Number | Date | Country | |
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Parent | 11275021 | Dec 2005 | US |
Child | 12764528 | US | |
Parent | 10819964 | Apr 2004 | US |
Child | 11275021 | US | |
Parent | 08755735 | Nov 1996 | US |
Child | 09946733 | US |