Semiconductor device and method of fabricating the same

Abstract

A method of fabricating a transistor of a semiconductor device comprises forming first and second trenches for gates in a substrate; forming a liner layer on innerwalls of the first and second trenches; forming first and second epitaxial gate electrodes by performing an epitaxial growth on the first and second trenches comprising the liner layers therein; forming isolation structures in the substrate, wherein the isolation structures contact the first and second epitaxial gate electrodes, respectively; forming a gate insulation layer and a gate electrode over a region of the substrate between the first and second epitaxial gate electrodes; and forming source and drain regions in the substrate disposed in respective edge regions of the gate electrode and overlapping the gate electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a sectional view of a typical MOS transistor;

FIG. 2 illustrates a layout of a transistor in accordance with an embodiment of the present invention; and

FIGS. 3 to 8 illustrate sectional views to describe a method of fabricating a transistor of a semiconductor device in accordance with an embodiment of the present invention.

Claims

1. A method of fabricating a transistor of a semiconductor device, the method comprising: forming first and second trenches for gates in a substrate, wherein the trenches are spaced apart from each other by a predetermined distance;forming a liner layer on innerwalls of the first and second trenches;forming first and second epitaxial gate electrodes by performing a selective epitaxial growth on the first and second trenches comprising the liner layers therein;forming isolation structures in the substrate, wherein the isolation structures are formed to contact the first and second epitaxial gate electrodes, respectively;forming a gate insulation layer and a gate electrode over a region of the substrate between the first and second epitaxial gate electrodes; andforming source and drain regions in the substrate disposed in respective edge regions of the gate electrode and overlapping the gate electrode.

2. The method of claim 1, wherein forming the first and second trenches comprises: sequentially forming a first pad layer and a second pad layer over the substrate;forming a mask for a trench over the second pad layer;forming the first and second trenches by performing a photolithography process and an etching process on the second pad layer, the first pad layer and the substrate by using the mask.

3. The method of claim 1, wherein forming the isolation structures comprises: forming a third pad layer over the substrate comprising the first and second epitaxial gate electrodes formed therein;forming an isolation mask over the third pad layer;forming isolation trenches while leaving portions of the first and second epitaxial gate electrodes by performing a photolithography process and an etching process using the isolation mask, wherein the portions nearly facing each other remain; andfilling an insulation layer into the isolation trenches.

4. The method of claim 1, wherein the forming a liner layer comprises forming the liner layer comprising an oxide-based material.

5. The method of claim 1, wherein the forming a gate insulation layer comprises forming the gate insulation layer comprising an oxide-based material.

6. A transistor of a semiconductor device, the transistor comprising: at least one isolation structure formed in an isolation region of a substrate;a gate insulation layer formed over an active region of the substrate;a gate electrode formed over the gate insulation layer;first and second epitaxial gate electrodes formed in the substrate and spaced apart from each other and comprising the gate electrode disposed on the substrate therebetween, wherein the gate electrode is arranged overlapped with the first epitaxial gate electrode and the second epitaxial gate electrode; andsource and drain regions formed in the substrate disposed in respective edge regions of the gate electrode and overlapping the gate electrode.

7. The transistor of claim 6, wherein the first and second epitaxial gate electrodes are formed by an epitaxial growth in first and second trenches for gates, respectively, the first and second trenches being formed spaced apart from each other by a predetermined distance and comprising a liner layer formed over innerwalls thereof.

8. The transistor of claim 7, wherein the isolation structure faces the first and second epitaxial gate electrodes formed by an epitaxial growth in first and second trenches while leaving portions of the first and second epitaxial gate electrodes, wherein the portions nearly face each other.

9. The method of claim 6, wherein the liner layer comprises an oxide-based material.

10. The method of claim 6, wherein the gate insulation layer comprises an oxide-based material.