This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-324850, filed on Nov. 9, 2005; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a super junction structure and a method of manufacturing the same.
2. Background Art
Conventionally, as a semiconductor device suitable for power electronics applications, semiconductor devices having a “super junction structure” have been known. The super junction structure is such that n-type pillar regions and p-type pillar regions are alternately arranged on a semiconductor substrate. For example, in a proposed technique (e.g., JP 2002-170955A), n-type and p-type impurities are injected by ion implantation into the side face of the trenches provided in an epitaxial layer on the semiconductor substrate, and then diffused into the epitaxial layer to form n-type pillar regions and p-type pillar regions.
However, in such semiconductor devices, crystal defects such as slip dislocations are likely to occur at the trench end under the influence of stress during thermal oxidation of the trench inner wall or oxidation for burying a filling, as well as stress due to the filling.
According to an aspect of the invention, there is provided a semiconductor device including: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided on the major surface of the semiconductor layer, the second semiconductor pillar region being adjacent to the first semiconductor pillar region; and a dielectric filled inside a trench, the trench being provided adjacent to the first semiconductor pillar region and away from the second semiconductor pillar region, wherein the first semiconductor pillar region, the second semiconductor pillar region, and the trench are extending along a first direction, the first direction is substantially perpendicular to the depth direction of the trench, and at least both ends of the first semiconductor pillar region in the first direction are provided more inside than both ends of the trench in the first direction.
According to other aspect of the invention, there is provided a semiconductor device including: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; and a second semiconductor pillar region of a second conductivity type filled inside a trench, the trench being provided adjacent to the first semiconductor pillar region, wherein the first semiconductor pillar region and the trench are extending along a first direction, the first direction is substantially perpendicular to the depth direction of the trench, and both ends of the first semiconductor pillar region in the first direction are provided more inside than both ends of the trench in the first direction.
According to other aspect of the invention, there is provided a method of manufacturing a semiconductor device, including: forming a trench in a second semiconductor layer formed on a major surface of a first semiconductor layer of a first conductivity type; injecting impurities of the first conductivity type into a sidewall of the trench while both ends of the trench are covered with a mask; forming a first semiconductor pillar region of the first conductivity type adjacent to the trench by diffusing the impurities of the first conductivity type; and forming a second semiconductor pillar region of the second conductivity type adjacent to the first semiconductor pillar region.
FIGS. 7 is a process cross section along the line A-A in
FIGS. 11 to 14 are process cross sections subsequent to
FIGS. 20 to 22 are process cross sections subsequent to
Embodiments of the invention will now be described with reference to the drawings. While the following embodiments are described assuming the first conductivity type as N-type and the second conductivity type as P-type, the invention also encompasses embodiments that assume the first conductivity type as P-type and the second conductivity type as N-type.
First Embodiment
In the semiconductor device 11 according to this embodiment, on a major surface of an N+-type silicon substrate (first semiconductor layer) 2 having a high impurity concentration, first pillar regions 4 of N-type silicon (hereinafter also simply referred to as “N-type pillar regions”) and second pillar regions 6 of P-type silicon (hereinafter also simply referred to as “P-type pillar regions”) are provided in parallel.
A trench T is adjacent to the surface of the N-type pillar region 4 on the opposite side of the surface adjacent to the P-type pillar region 6. The inside of the trench T is filled with a dielectric 8 made of silica, for example, via a silicon oxide film 14 and a silicon nitride film 16. The trench T and the dielectric 8 are sandwiched between the N-type pillar regions 4. Note that the dielectric 8 is not limited to silica, but may be other dielectrics such as silicon nitride (example of nitride), oxide.
As shown in the cross-sectional structure of
On the plane shown in
The N-type pillar region 4 and the P-type pillar region 6 have a substantially equal length along the first direction X1. The length of the N-type pillar region 4 and the P-type pillar region 6 along the first direction X1 is shorter than length of the trench T along the first direction X1. Both ends of the N-type pillar region 4 and the P-type pillar region 6 in the first direction X1 are located more inside than both ends of the trench T in the first direction X1. For example, the trench T has a length of 2.5 to 4 millimeters along the first direction X1. Both ends 4e, 6e of the N-type pillar region 4 and the P-type pillar region 6, respectively, are located more inside than both ends Te of the trench T by about 10 to 50 micrometers, for example. Conversely, both ends Te of the trench T protrude from both ends 4e, 6e of the N-type pillar region 4 and the P-type pillar region 6 by about 10 to 50 micrometers.
An active region (base region 18, source region 22) described below is formed on the P-type pillar region 6. The active region does not extend to both ends Te of the trench T. Preferably, the ends of the active region in the first direction X1 slightly extend out from the ends 6e of the P-type pillar region 6.
Referring again to
An insulating film 26 is provided on the surface of the portion extending from the N-type pillar region 4 via the base region 18 to the source region 22. This insulating film 26 is gate insulating film. An insulating film 24 is provided also on the dielectric 8. A control electrode (gate electrode) 30 is provided on the insulating films 24, 26. The periphery and the upper surface of the control electrode 30 are covered with an interlayer insulating film 28. A first main electrode (source electrode) 32 is provided on the portion of the source region 22 not covered with the interlayer insulating film 28, on the base region 19, and on the interlayer insulating film 28. The source region 22 is connected to the first main electrode 32. The base region 18 is connected to the first main electrode 32 via the base contact region 19. A second main electrode (drain electrode) 34 is provided on the surface opposite to the major surface of the substrate 2.
In the semiconductor device 11 configured as above, a prescribed control voltage is applied to the control electrode 30. Then an N-channel is formed in the vicinity of the surface of the P-type base region 18 immediately below the control electrode 30, and the N+-type source region 22 becomes conductive to the N-type pillar region 4. As a result, a main current path is formed between the first main electrode 32 and the second main electrode 34 via the N+-type source region 22, the N-type pillar region 4, and the N+-type substrate 2. Thus the path between these electrodes 32, 34 is turned on.
The device withstand voltage can be maintained by the depletion layer laterally extending from the PN junction between the N-type pillar region 4 and the P-type base region 18 and from the PN junction between the N-type pillar region 4 and the P-type pillar region 6, and by the dielectric 8 buried in the trench T.
In the semiconductor device 11 according to this embodiment, as described above with reference to
In contrast, as described above, this embodiment has a structure such that the vicinity of the trench end, where crystal defects are likely to occur, is not used as an operating region of the device. Therefore, even if any crystal defects occur in the vicinity of the trench end, they do not affect the product quality. This results in products with high yield and good quality.
In contrast, in the semiconductor device 11 according to this embodiment, as shown in
Next, an example method of manufacturing a semiconductor device according to this embodiment is described.
FIGS. 7 to 14 are process cross sections illustrating the relevant part of a process of manufacturing a semiconductor device according to this embodiment.
First, as shown in
Next, an etching mask (not shown) is formed on the surface of the N−-type silicon layer 3. For example, after a thermal oxide film is formed on the surface of the N−-type silicon layer 3, openings are selectively formed in the oxide film. Then the N−-type silicon layer 3 is anisotropically etched through the openings. Thus, as shown in
Next, on the surface of the N−-type silicon layer 3 is formed a stopper film 38 (see
In the state where both ends of the trench T are thus covered with the stencil mask 36, P-type impurities such as boron (B) are injected into the sidewall of the trench T in an oblique direction (e.g., at an angle of 3 to 7° with respect to the depth direction) as shown in
Next, likewise, in the state where both ends of the trench T are covered with the stencil mask 36, N-type impurities such as arsenic (As) are injected into the sidewall of the trench T in an oblique direction (e.g., at an angle of 3 to 70 with respect to the depth direction) as shown in
After the ion implantation step described above, heat treatment is conducted to diffuse and activate arsenic and boron injected into the N−-type silicon layer 3.
Here, as described above, because N-type impurities and P-type impurities are not injected into the sidewall in the vicinity of both ends of the trench T, the N-type pillar region 4 and the P-type pillar region 6 are not formed in the vicinity of both ends of the trench T as shown in the planar structure of
After the foregoing heat treatment step, a dielectric 8 is buried inside the trench T as shown in
Next, as shown in
Next, an interlayer insulating film 28 is formed so as to cover the control electrode 30. A contact hole is formed for source contact in the interlayer insulating film 28. Part of the base contact region 19 and the source region 22 is exposed through the contact hole. A first main electrode 32 is formed on the interlayer insulating film 28 so as to fill the contact hole. A second main electrode 34 is formed on the surface opposite to the major surface of the substrate 2. Thus a semiconductor device 11 shown in
Second Embodiment
Next, a second embodiment of the invention is described Elements similar to those in the first embodiment described above are marked with the same reference numerals and not described in detail.
Like the first embodiment, the semiconductor device 41 according to this embodiment has N-type pillar regions 44 and P-type pillar regions 46 formed on a silicon substrate 2 in parallel. The difference from the first embodiment is that the inside of the trench T is filled with the P-type pillar region 46 by epitaxial growth.
As shown in the cross-sectional structure of
The length of the N-type pillar region 44 along the first direction X1 is shorter than the length of the P-type pillar region 46 (trench T) along the first direction X1. Both ends 44e of the N-type pillar region 44 in the first direction X1 are located more inside than both ends Te of the P-type pillar region 46 (trench T) in the first direction X1. For example, the P-type pillar region 46 (trench T) has a length of 2.5 to 4 millimeters along the first direction X1. Both ends 44e of the N-type pillar region 44 in the first direction X1, respectively, are located more inside than both ends Te of the P-type pillar region 46 (trench T) by about 10 to 50 micrometers, for example. Conversely, both ends Te of the P-type pillar region 46 (trench T) protrude from both ends 44e of the N-type pillar region 44 by about 10 to 50 micrometers.
An active region (base region 18, source region 22) described below is formed on the P-type pillar region 46. The ends of the active region in the first direction X1 do not extend to both ends Te of the P-type pillar region 46 (trench T). Preferably, the ends of the active region in the first direction X1 slightly extend out from the ends 44e of the N-type pillar region 44.
Referring again to
An insulating film 56 is provided on the surface of the portion extending from the N-type pillar region 44 via the base region 18 to the source region 22. This insulating film 56 is gate insulating film. A control electrode (gate electrode) 50 is provided on the insulating film 56. The periphery and the upper surface of the control electrode 50 are covered with an interlayer insulating film 58. A first main electrode (source electrode) 52 is provided on the portion of the source region 22 not covered with the interlayer insulating film 58, on the base contact region 19, and on the interlayer insulating film 58. The source region 22 is connected to the first main electrode 52. The base region 18 is connected to the first main electrode 32 via the base contact region 19. A second main electrode (drain electrode) 34 is provided on the surface opposite to the major surface of the substrate 2.
In the semiconductor device 41 configured as above, a prescribed control voltage is applied to the control electrode 50. Then an N-channel is formed in the vicinity of the surface of the P-type base region 18 immediately below the control electrode 50, and the N+-type source region 22 becomes conductive to the N-type pillar region 44. As a result, a main current path is formed between the first main electrode 52 and the second main electrode 34 via the N+-type source region 22, the N-type pillar region 44, and the N+-type substrate 2. Thus the path between these electrodes 52, 34 is turned on.
The device withstand voltage can be maintained by the depletion layer laterally extending from the PN junction between the N-type pillar region 44 and the P-type base region 18 and from the PN junction between the N-type pillar region 44 and the P-type pillar region 46.
In the semiconductor device 41 according to this embodiment, as described above with reference to
As described above, this embodiment also has a structure such that the vicinity of the bottom near the trench end, where crystal defects are likely to concentrate, is not at all used as a main current path of the device. Therefore, even if any crystal defects occur in the vicinity of the trench end, they do not affect the product quality. This results in products with high yield and good quality.
Next, an example method of manufacturing a semiconductor device according to this embodiment is described.
FIGS. 17 to 23 are process cross sections illustrating the relevant part of a process of manufacturing a semiconductor device according to this embodiment.
Like the first embodiment, on a major surface of an N+-type silicon substrate (first semiconductor layer) 2 having a high impurity concentration, an N−-type silicon layer (second semiconductor layer) 3 having a low impurity concentration is epitaxially grown. Then trenches T are formed in the N−-type silicon layer 3.
Next, on the surface of the N−-type silicon layer 3 is formed a stopper film for preventing ion implantation into this surface. Then, as shown in
In the state, oxygen or nitrogen is injected into the bottom of the sidewall of the both ends Te of the trench T in an oblique direction (e.g., at an angle of 3 to 7° with respect to the depth direction) by ion-implantation technique. For example, dose amount in this ion implantation is 1×1013 to 1×1015/cm2. Thus, the bottom of the sidewall of the both ends Te of the trench T is electrically inactivated. Leakage current easily occurs in the bottom of the sidewall of the both ends of the trench while operating. However, the leakage current can be suppressed because the bottom of the sidewall of the both ends Te of the trench T is electrically inactivated in this embodiment.
Next, on the surface of the N−-type silicon layer 3 is formed a stopper film 38 for preventing ion implantation into this surface. Then, as shown in
In the state where both ends of the trench T are thus covered with the stencil mask 36, N-type impurities such as arsenic (As) are injected into the sidewall of the trench T in an oblique direction (e.g., at an angle of 3 to 7° with respect to the depth direction) as shown in
After the ion implantation step described above, heat treatment is conducted to diffuse and activate arsenic injected into the N−-type silicon layer 3.
Next, as shown in
Next, for example, it is annealed in the presence of nitrogen gas at 1150 to 1200 degrees centigrade for nine hours. The annealing ambient is not limited nitrogen gas, but can be argon gas or vacuum.
Crystal defects are observed inside of the trench T before the annealing. But crystal defects are not observed after the annealing. Only microscopic void are observed after the annealing. However, crystal defects in the vicinity of the surface are observed after the annealing.
After the above annealing, the P-type pillar region 46 grown above than an open end of the trench T is polished by CMP (chemical mechanical polishing) process. Then the P-type pillar region 46 is planarized as shown in
Next, as shown in
Next, an interlayer insulating film 58 is formed so as to cover the control electrode 50. A contact hole is formed for source contact in the interlayer insulating film 58. Part of the base contact region 19 and the source region 22 is exposed through the contact hole. A first main electrode 52 is formed on the interlayer insulating film 58 so as to fill the contact hole. A second main electrode 34 is formed on the surface opposite to the major surface of the substrate 2. Thus a semiconductor device 41 shown in
Third Embodiment
The invention can be applied not only to MOSFETS, but also to other semiconductor devices having the so-called super junction structure such as IGBTs (Insulated Gate Bipolar Transistors), which are also encompassed within the scope of the invention.
The vertical IGBT illustrated in this figure has a P+-collector layer 40 formed on the backside of the N+-type layer 2. An emitter electrode 32 is provided as a first main electrode, and a collector electrode 34 is provided as a second main electrode. Although the nomenclature of individual elements and part of the structure are different from the MOSFET described above with reference to
Third semiconductor pillar regions 61 of the first conductivity type (N-type pillar region) and fourth pillar regions 62 of the second conductivity type (P-type pillar region) are provided in parallel on the major surface of the semiconductor layer 2 in a termination. The termination is outside of the base region 18. The N-type pillar region 61 is adjacent to the P-type pillar region 62 to form a PN junction.
A RESURF (reduced surface field) region 64 of the second conductivity type (P-type) is provided in the surface layer of the termination. The RESURF region 64 is provided on the N-type pillar region 61 and the P-type pillar region 62. A field plate electrode 65 is provided on the surface of the termination via an insulating layer 58. The field plate electrode 65 is connected to the control electrode 50. The field plate electrode 65 can be connected to the source electrode 52.
The alignment pitch of the N-type pillar region 61 and the P-type pillar region 62 in the termination is shorter than that of the N-type pillar region 44 and the P-type pillar region 46 in the cell. Alternatively, the impurity concentration of the portion aligned the N-type pillar region 61 and the P-type pillar region 62 in the termination is lower than that of the portion aligned the N-type pillar region 44 and the P-type pillar region 46 in the cell. Thus, the depletion layer easily extends in the termination where the withstand voltage can be hard to maintain than the cell. Accordingly, the reduction of the withstand voltage in the termination can be suppressed.
Embodiments of the invention have been described with reference to specific examples. However, the invention is not limited thereto, but can be variously modified on the basis of the spirit of the invention.
Material of the semiconductor is not limited to silicon, but may be other materials such as silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), aluminum nitride (AlN), boron nitride (BN), indium nitride (InN), germanium (Ge), silicon germanium (SiGe), for example.
In the structures described above, the conductivity type of each element can be reversed.
Furthermore, in the first embodiment, the combination of the two types of impurities, that is, P-type and N-type impurities, injected into the sidewall of the trench T is not limited to the above-described one. For example, in the case of N-channel devices, any combination can be used as long as the diffusion coefficient of P-type impurities is larger than the diffusion coefficient of N-type impurities.
As shown in
Number | Date | Country | Kind |
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2005-324850 | Nov 2005 | JP | national |