Patent Application
20160027695
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device and, in particular, to a semiconductor device that has a Panel scale Fan-out package structure in which a thin film wiring step and an assembling step are performed on a large panel scale, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
With demand for the high functionality and the miniaturization of electronic equipment in recent years, electronic components have been increasingly integrated and mounted with higher density. Thus, semiconductor devices used in the electronic equipment have been reduced in size than ever before.
As a method of manufacturing semiconductor devices such as LSI units and IC modules, the following method has been known (see, for example, Japanese Patent Publication No. 2003-197662). First, a plurality of semiconductor chips determined to be nondefective according to an electrical characteristics test is arranged and bonded onto a retention plate in a prescribed arrangement with the element circuit surfaces thereof directed downward. After that, a resin sheet is, for example, arranged on the semiconductor chips and heated and pressed to be molded. Thus, the plurality of semiconductor chips is sealed in a lump by a resin. Next, after the retention plate is separated and the resin sealed body is cut off and processed into a prescribed shape (for example, a circular shape), an insulation material layer is formed on the element circuit surfaces of the semiconductor chips embedded in the resin sealed body. Then, openings are formed in the insulation material layer so as to suit the electrode pads of the semiconductor chips. After that, a wiring layer is formed on the insulation material layer, while conduction portions (via portions) are formed in the openings so as to be connected to the electrode pads of the semiconductor chips. Next, a solder resist layer and solder balls that serve as external electrode terminals are sequentially formed. Then, the semiconductor chips are cut off one by one and segmented into pieces to complete the semiconductor devices.
However, in the conventional semiconductor devices thus obtained, the resin is cured to shrink when the plurality of semiconductor chips is sealed at the same time by the resin and its shrinking amount is not necessarily equal to one as designed. Therefore, after the resin is cured, the semiconductor chips are likely to be deviated from designed positions depending on the arrangement positions thereof. In the semiconductor chips in which a positional deviation occurs, the via portions formed in the openings of the insulation material layer and the electrode pads of the semiconductor chips are deviated from each other, which results in the problem that connection reliability is reduced.
Japanese Patent Publication No. 2010-219489 describes a semiconductor device that addresses the problem.
A semiconductor device 20 has a support plate 1 constituted by a resin cured body or metal. A semiconductor chip 2 is arranged on one principal surface of the support plate 1 with the element circuit surface (front side surface) thereof directed upward, and the surface (rear side surface) opposite to the element circuit surface is bonded onto the support plate 1 via an adhesive 3. Further, an insulation material layer 4 is singly formed on the entire principal surface of the support plate 1 so as to cover the element circuit surface of the semiconductor chip 2. A wiring layer 5 made of conductive metal such as copper is formed on the single insulation material layer 4 and partially withdrawn to the peripheral region of the semiconductor chip 2. In addition, conduction portions (via portions) 6 that electrically connect the electrode pads (not shown) of the semiconductor chip 2 and the wiring layer 5 to each other are formed in the insulation material layer 4 formed on the element circuit surface of the semiconductor chip 2. The conductive portions 6 are formed in a lump to be integrated with the wiring layer 5. Moreover, a plurality of external electrodes 7 such as solder balls is formed at the prescribed positions of the wiring layer 5. Further, a wiring protection layer (solder resist layer) 8 is formed on the insulation material layer 4 and the wiring layer 5 that does not include the connection parts of the external electrodes 7 such as solder balls.
The device greatly contributes to the high density and the miniaturization of electronic equipment for which demand has been further increased in recent years.
Meanwhile, it is described in Japanese Patent Publication No. 2010-219489 that a resin cured body made of a cured rein or a flat plate that has a uniform thickness and is made of metal such as stainless steel and a 42 alloy is used as the support plate 1 of the semiconductor device 20. However, the support plate integrated with the semiconductor device plays a role as a product conveyance carrier in a manufacturing step while functioning as a stiffener, a radiation plate, and an electromagnetic shield, and thus a thick stainless steel is generally used to facilitate the handling of a panel, reduce warpage, and facilitate segmentation. This results in the problem that the semiconductor device as a final product is thickened and radiation becomes poor since a material excellent in heat conduction cannot be selected as a material of the support plate 1. Therefore, it has been difficult to lower (thin) the semiconductor device.
When SUS304 is, for example, used as the support plate (radiation plate) 1, the heat conductivity (16.7 [W/mK]) of the SUS304 is 1/20 or lower the heat conductivity (about 400 W/mK) of copper generally used as a radiation plate. Therefore, the radiation of the SUS304 is poor, and the effect of reducing PKG heat resistance is small. Further, when SUS that has a thickness of 0.3 mm is used to reduce the warpage of the support plate, it cannot be applied to a mobile product since its attachment height becomes high.
In addition, it is described in Japanese Patent Publication No. 2010-219489 that the thickness of the semiconductor devices may be reduced by, for example, the mechanical polishing of the surface opposite to the semiconductor-chip mounting surface of the support plate before cutting off and segmenting the semiconductor devices into pieces. However, a specific manufacturing method is not described in Japanese Patent Publication No. 2010-219489, and there are concerns about fluctuations in the polishing and quality reduction due to stress loads to the semiconductor devices. Therefore, it is difficult to put the method of the reduction in the thickness of the semiconductor devices into practical use.
An object of the present invention is to provide a semiconductor device low in height and a method of manufacturing the semiconductor device.
Another object of the present invention is to provide a semiconductor device low in heat resistance and a method of manufacturing the semiconductor device.
After an intensive study, the present inventors have come to the conclusion that the above problems can be addressed by thinning a support plate on which a semiconductor chip is mounted to obtain a semiconductor device low in height and by using a combined support plate in which flat plates low in heat conduction are combined with each other to obtain a semiconductor device low in heat resistance and thus have completed the present invention.
That is, the details of the present invention are as follows.
(1) A semiconductor device including:
(2) A method of manufacturing the semiconductor device according to (1), the method including:
(3) The method of manufacturing the semiconductor device according to (2), wherein
(4) The method of manufacturing the semiconductor device according to (3), wherein
(5) The method of manufacturing the semiconductor device according to (4), wherein
(6) The method of manufacturing the semiconductor device according to (2), wherein
(7) The method of manufacturing the semiconductor device according to (2), wherein
(8) The method of manufacturing the semiconductor device according to (3), wherein
(9) A semiconductor device including:
(10) A method of manufacturing the semiconductor device according to (9), the method including:
The semiconductor device of the present invention can produce the following effects:
Hereinafter, embodiments for carrying out the present invention will be described. Note that although the embodiments will be described based on the drawings in the following description, the drawings are given for illustration purposes and the present invention is not limited to the drawings.
A semiconductor device 20 shown in
The semiconductor chip 2 is arranged on the principal surface of the support plate 1 with the element circuit surface thereof having an electrode (not shown) directed upward and bonded via an adhesive 3 onto the support plate 1 at the surface (rear surface) thereof opposite to the element circuit surface.
On the entire principal surface of the support plate 1, the insulation material layer 4 is formed so as to cover the element circuit surface of the semiconductor chip 2. The wiring layer 5 that constitutes wiring made of conductive metal such as copper is formed on the insulation material layer 4 and partially withdrawn to the peripheral region of the semiconductor chip 2. The insulation material layer on the electrode of the semiconductor chip 2 has openings, and conductive portions 6 are formed in the openings to electrically connect the wiring layer 5 and the electrode to each other. In addition, the plurality of external electrodes 7 such as solder balls is formed at the prescribed positions of the wiring layer 5.
On the insulation material layer 4 and the wiring layer 5 that does not include the bonding parts of the external electrodes 7, a wiring protection layer 8 is formed. The wiring protection layer 8 may be made of a material the same as or different from the insulation material of the insulation material layer 4.
In the process of manufacturing the semiconductor device of the embodiment, a combined support plate in which a plurality of flat plates is laminated to each other is used as the support plate. In the semiconductor device, warpage occurs due to a difference in the heat expansion coefficient between members when the semiconductor device is heated in the manufacturing process. The support plate requires a certain degree of stiffness to prevent the warpage. Therefore, when SUS is, for example, employed as a material of the support plate, the support plate that has a thickness of about 0.3 mm has been conventionally used. However, when the support plate has a thickness of about 0.3 mm, the mounting height of the semiconductor device becomes high as a product and thus the semiconductor device is not suitably used as a mobile product.
In view of this, in the embodiment, the thick combined support plate in which the plurality of flat plates is laminated to each other is used as the support plate in the process of manufacturing the semiconductor device, and a flat plate other than a flat plate (called a first flat plate) on which the semiconductor chip is mounted is finally separated from the first flat plate to make only the first flat plate remain in the semiconductor device. Thus, the semiconductor device that is free from the warpage and low in height can be obtained.
Since other flat plates laminated on the first flat plate are responsible for the stiffness that the support plate is required to have in order to prevent the warpage, the first flat plate may be thin. Therefore, the finally-obtained semiconductor device can be thinned. The first flat plate may be made of a material the same as or different from those of other flat plates. For example, when a flat plate other than the first flat plate is made of SUS, the first flat plate may be made of a material excellent in conduction such as copper. The first flat plate made of a material excellent in conduction such as copper effectively functions as the radiation plate of the semiconductor device.
A semiconductor device 20 of the embodiment has a structure in which two semiconductor chips 2 (a first semiconductor chip 2a and a second semiconductor chip 2b) are laminated and arranged. The first semiconductor chip 2a is bonded onto one principal surface of a flat plate 1 the same as that of the first embodiment with the element circuit surface thereof directed upward, an insulation material layer (first insulation material layer) 4a is formed on the first semiconductor chip 2a so as to cover the same, and a first wiring layer 5a that has conductive portions 6a on the electrode of the first semiconductor chip 2a is formed on the insulation material layer 4a. Further, an interlayer insulation protection layer 18 is formed on the first insulation material layer 4a and the first wiring layer 5a that does not include the connection parts (interlayer via connection parts) of interlayer via portions 16 that will be described later.
Moreover, the second semiconductor chip 2b is bonded onto the interlayer insulation protection layer 18 with the element circuit surface thereof directed upward, and an insulation material layer (second insulation material layer) 4b is formed so as to cover the second semiconductor chip 2b. Note that the second insulation material may be the same as or different from the first insulation material.
Further, a second wiring layer 5b is formed on the second insulation material layer 4b, and conductive portions 6b that electrically connect the second wiring layer 5b and the electrode of the second semiconductor chip 2b to each other are formed. In addition, in the peripheral region of the second semiconductor chip 2b, openings are formed in the second insulation material layer 4b so as to suit via connection parts opened and formed in the interlayer insulation protection layer 18, and the interlayer via portions 16 that electrically connect the first wiring layer 5a and the second wiring layer 5b to each other are formed in the openings. Moreover, external electrodes 7 such as solder balls are formed at the prescribed positions of the second wiring layer 5b, and a wiring protection layer 8 is formed on the second insulation material layer 4b and the second wiring layer 5b that does not include the connection parts of the external electrodes 7.
In the second embodiment thus configured, the semiconductor device that has the structure in which the two semiconductor chips 2a and 2b are laminated and arranged, has the high connection reliability between the electrodes of the respective semiconductor chips 2 and the wiring layers, and is capable of responding to the miniaturization of the electrodes can be obtained at a high yield and a low cost.
Note that although the second embodiment shows the structure in which the two semiconductor chips 2 are laminated and arranged, a structure in which three or more semiconductor chips are laminated and arranged may be employed. In the case of the structure in which three or more semiconductor chips are laminated to each other, the same structures as the structure in which the second semiconductor chip 2b, the second insulation material layer 4, the second wiring layer 5b, and the interlayer via portions 16 are laminated to each other are laid one on another by the number of the semiconductor chips. Further, a wiring protection layer is formed on the outermost wiring layer, and the external electrodes 7 are formed at prescribed positions. In this way, the semiconductor device is completed.
The method of manufacturing the semiconductor device 20 of the first embodiment will be described below as an embodiment.
In the manufacturing method that will be described below, the support plate 1 is extremely greater in size than the semiconductor chips 2 of the present invention, and the plurality of semiconductor chips 2 is mounted on the support plate 1 with an interval placed therebetween and subjected to prescribed treatment steps to simultaneously manufacture the plurality of semiconductor devices. The plurality of semiconductor devices is finally segmented into separate semiconductor devices. As a result, the plurality of semiconductor devices can be obtained.
Since the plurality of semiconductor devices is simultaneously manufactured in this way, it becomes possible to remarkably reduce a manufacturing cost.
In addition, although the semiconductor device that has one semiconductor chip on the support plate will be described in the following embodiment, a case in which a plurality of semiconductor chips is formed on the support plate is also an embodiment of the present invention.
A third embodiment of the method of manufacturing the semiconductor device shown in the first embodiment will be described based on
The combined support plate 1 is laminated in such a way that a first flat plate 1a and a second flat plate 1b are bonded together via an adhesive 3c. As shown in the left part of FIG. 3, the adhesive 3c is provided along cut lines CL used for the segmentation of the semiconductor devices.
The first flat plate 1a and the second flat plate 1b are flat plates that have a uniform thickness and constituted by a resin cured body made of a cured insulation resin or metal such as stainless steel and 42 alloy. The combined support plate 1 should be such that the total thickness of the first flat plate 1a and the second flat plate 1b is a thickness at which warpage does not occur due to the formation of the insulation material layer that will be described later. Since only the first flat plate 1a among the flat plates that constitute the combined support plate 1 is used as a component of the semiconductor device, the thickness of the first flat plate is preferably thin.
First, as shown in
Next, as shown in
As an insulation material, an insulative resin such as a heat curable resin can be, for example, used. The insulation material can be supplied based on a coating method using a spin coater, a printing method using a squeegee, a method of laminating a film-like resin, or the like. In addition, it is possible to use a photosensitive resin as the insulative resin.
Then, as shown in
As shown in
Note that the conductive portions 6 may be filled with a conductive material or an insulation material to form the insulation material layer 4 that will be described later may be formed on the plated film of the side walls. When the conductive portions 6 are filled with a conductive material, they may be filled in a lump at the plating or a conductive paste may be filled after the plated film is formed on the side walls.
The patterning by photolithography described above is not particularly limited, and the wiring layer 5 can be formed based on, for example, a subtractive method that will be described below. The subtractive method can be performed in such a way that a photosensitive resist layer is formed on the metal thin film layer, exposed and developed with a mask having a prescribed pattern, and the metal thin film layer is etched. In addition, the base (seed layer) described above is removed based on etching after the formation of the wiring layer 5.
Next, as shown in
After the formation of the wiring protection layer 8, opening parts are formed in the wiring protection layer 8 to provide the external electrodes 7, and a conductive material is provided in the opening parts to form the external electrodes 7. As the conductive material, a solder ball, a conductive paste, a solder paste, or the like is used.
When at least the upper part of the adhesive is cut off along the cut lines CL shown in
Since the adhesive 3c that bonds the first flat plate 1a and the second flat plate 1b together is provided along the cut lines CL, the bonding surface part of the adhesive 3c that contributes to the bonding between the first flat plate 1a and the second flat plate 1b is removed at the cutting, whereby the first flat plate 1a and the second flat plate 1b are separated from each other. Thus, the semiconductor devices 20 with the support plate 1 that has a desired thickness shown in
For example, when the support plate that has a total thickness of 300 μm is realized by a SUS plate that has a thickness of 50 μm to serve as the first flat plate 1a and a flat plate that has a thickness of 250 μm to serve as the second flat plate 1b, the same anti-warpage effect as that of one flat plate having a thickness of 300 μm is obtained. In addition, since only the first flat plate 1a that has a thickness of 50 μm remains in the semiconductor devices when the second flat plate 1b is separated fr.om the semiconductor devices, the semiconductor devices can be thinned.
Moreover, when the first flat plate is made of a material excellent in heat conduction such as copper, the semiconductor devices that are low in height and excellent in radiation can be obtained.
Furthermore, since the second flat plate 1b is not cut off, it is reusable.
A fourth embodiment will be described based on
The embodiment is one obtained by modifying a part of the third embodiment. In the embodiment, as shown in
Thus, the semiconductor devices 20 with the support plate 1 that has a desired thickness shown in
In addition, since the second flat plate 1b is not cut off, it is reusable.
In the embodiment, as shown in
A fifth embodiment will be described based on
In the embodiment, as shown in
The second flat plate 1b and the third flat plate 1c are bonded together via the adhesive 3c.
The first flat plate 1a and the third flat plate 1c come into direct contact with each other without the adhesive.
Further, a regional part on the periphery of the second flat plate 1b in which the third flat plate does not exist and a regional part on the periphery of the first flat plate in which the third flat plate does not exist are bonded together via the adhesive 3c, whereby the third flat plate 1c comes into intimate contact with the first flat plate 1a.
The combined support plate 1 of the embodiment has the laminated structure as described above. Therefore, when the combined support plate 1 is cut off together with the insulation material layer 4 at a part on the periphery of the combined support plate 1 in which the first flat plate 1a, the third flat plate 1c, and the second flat plate 1b exist in order to segment the semiconductor devices that include one or a plurality of semiconductor chips into pieces, a part in which the first flat plate 1a and the second flat plate 1b are bonded together is removed and also the first flat plate can be separated from the third flat plate and the second flat plate since the first flat plate 1a and the third flat plate 1c are not bonded together via the adhesive.
A sixth embodiment will be described based on
In the embodiment, as shown in
As shown in
In addition, since the welding width of the welded part 32 is only required to be about 1 mm, the combined support plate 1 is locally heated. Therefore, distortion caused by the welding can be made smaller than that caused by TIG welding or laser welding.
However, since the first flat plate 1a may be bored at the welding due to the gap between the flat plates when the first flat plate 1a is extremely thin, a jig by which the flat plates are caused to come into full contact with each other is required to prevent the flat plates from being bored.
Since the steps of forming the structures are the same as those described based on
In the aggregate of the semiconductor devices shown in
Thus, the semiconductor devices 20 with the support plate 1 that has a desired thickness shown in
An embodiment will be described based on
In the embodiment, the combined support plate 1 is constituted by the first flat plate 1a, the second flat plate 1b, and a temporary fixation film 11.
First, as shown in
Next, as shown in
Then, as shown in
The temporary fixation film 11 is one obtained by providing adhesive layers on both front and rear surfaces of a substrate film and is commercially available.
Since the steps of forming the structures are the same as those described based on
As shown in
When the semiconductor devices are segmented into the pieces along the cut lines CL using a blade 10 as shown in
An embodiment will be described based on
A semiconductor device 20 shown in
The semiconductor chip 2 is arranged on the principal surface of the support plate 1 with the element circuit surface thereof having an electrode (not shown) directed upward, and the surface (rear surface) opposite to the element circuit surface of the semiconductor chip 2 is bonded onto the support plate 1 via an adhesive 3.
On the entire principal surface of the support plate 1, an insulation material layer 4 is formed so as to cover the element circuit surface of the semiconductor chip 2. A wiring layer 5 that constitutes wiring made of conductive metal such as copper is formed on the insulation material layer 4 and partially withdrawn to the peripheral region of the semiconductor chip 2. The insulation material layer on the electrode of the semiconductor chip 2 has openings, and conductive portions 6 are formed in the openings to electrically connect the wiring layer 5 and the electrode to each other. In addition, the plurality of external electrodes 7 such as solder balls is formed at the prescribed positions of the wiring layer 5.
On the insulation material layer 4 and the wiring layer 5 that does not include the bonding parts of the external electrodes 7, the wiring protection layer 8 is formed. The wiring protection layer 8 may be made of a material the same as or different from the insulation material of the insulation material layer 4.
In the semiconductor device of the embodiment, a combined support plate in which a plurality of flat plates (a first flat plate 1a and a second flat plate 1b) is laminated to each other is used as the support plate 1. In the semiconductor device, warpage occurs due to a difference in the heat expansion coefficient between members when the semiconductor device is heated in a manufacturing process. The support plate requires a certain degree of stiffness to prevent the warpage. Therefore, when SUS is, for example, employed as a material of the support plate, the support plate that has a thickness of about 0.3 mm has been conventionally used. However, since the SUS is poor in heat conduction, it is not suitable as the radiation plate of the semiconductor device.
In addition, although it is expected to use a support plate made of copper excellent in heat conduction, a thick copper plate is required to enhance stiffness. However, the copper plate cannot be employed due to its poor workability.
Therefore, in the embodiment, the combined support plate in which the plurality of flat plates is laminated to each other to have stiffness to prevent the warpage is used as the support plate of the semiconductor device, and the first flat plate 1a on which the semiconductor chip is mounted is made of a material high in heat conduction such as copper. With this configuration, the semiconductor device that is free from the warpage during the manufacturing process and excellent in radiation can be obtained.
A semiconductor device 20 of the embodiment has a structure in which two semiconductor chips 2 (a first semiconductor chip 2a and a second semiconductor chip 2b) are laminated and arranged. The first semiconductor chip 2a is bonded onto one principal surface of a support plate 1 the same as that of the eighth embodiment with the element circuit surface thereof directed upward, an insulation material layer (first insulation material layer) 4a is formed on the first semiconductor chip 2a so as to cover the same, and a first wiring layer 5a that has conductive portions 6a on the electrode of the first semiconductor chip 2a is formed on the insulation material layer 4a. Further, an interlayer insulation protection layer 18 is formed on the first insulation material layer 4a and the first wiring layer 5a that does not include the connection parts (interlayer via connection parts) of interlayer via portions 16 that will be described later.
Moreover, the second semiconductor chip 2b is bonded onto the interlayer insulation protection layer 18 with the element circuit surface thereof directed upward, and an insulation material layer (second insulation material layer) 4b is formed so as to cover the second semiconductor chip 2b. Note that the second insulation material may be the same as or different from the first insulation material.
Further, a second wiring layer 5b is formed on the second insulation material layer 4b, and conductive portions 6b that electrically connect the second wiring layer 5b and the electrode of the second semiconductor chip 2b to each other are formed. In addition, in the peripheral region of the second semiconductor chip 2b, openings are formed in the second insulation material layer 4b so as to suit via connection parts opened and formed in the interlayer insulation protection layer 18, and the interlayer via portions 16 that electrically connect the first wiring layer 5a and the second wiring layer 5b to each other are formed in the openings. Moreover, external electrodes 7 such as solder balls are formed at the prescribed positions of the second wiring layer 5b, and a wiring protection layer 8 is formed on the second insulation material layer 4b and the second wiring layer 5b that does not include the connection parts of the external electrodes 7.
In the embodiment thus configured, the semiconductor device that has the structure in which the two semiconductor chips 2a and 2b are laminated and arranged, has the high connection reliability between the electrodes of the respective semiconductor chips 2 and the wiring layers, and is capable of responding to the miniaturization of the electrodes can be obtained at a high yield and a low cost.
Note that although the ninth embodiment shows the structure in which the two semiconductor chips 2 are laminated and arranged, a structure in which three or more semiconductor chips are laminated and arranged may be employed. In the case of the structure in which three or more semiconductor chips are laminated to each other, the same structures as the structure in which the second semiconductor chip 2b, the second insulation material layer 4, the second wiring layer 5b, and the interlayer via portions 16 are laminated to each other are laid one on another by the number of the semiconductor chips. Further, a wiring protection layer is formed on the outermost wiring layer, and the external electrodes 7 are formed at prescribed positions. In this way, the semiconductor device is completed.
The embodiment of the method of manufacturing the semiconductor device of the eighth embodiment will be described based on
In the manufacturing method that will be described below, the support plate 1 is extremely greater in size than the semiconductor chips 2 of the present invention, and the plurality of semiconductor chips 2 is mounted on the support plate 1 with an interval placed therebetween and subjected to prescribed treatment steps to simultaneously manufacture the plurality of semiconductor devices. The plurality of semiconductor devices is finally segmented into separate semiconductor devices. As a result, the plurality of semiconductor devices can be obtained.
Since the plurality of semiconductor devices is simultaneously manufactured in this way, it becomes possible to remarkably reduce a manufacturing cost.
In addition, although the semiconductor device that has one semiconductor chip on the support plate will be described in the following embodiment, a case in which a plurality of semiconductor chips is formed on the support plate is also an embodiment of the present invention.
The combined support plate 1 is laminated in such a way that a first flat plate 1a and a second flat plate 1b are bonded together via an adhesive 3c.
The first flat plate 1a and the second flat plate 1b are flat plates that have a uniform thickness. The first flat plate 1a is made of a material higher in heat conduction than the second flat plate 1b and preferably made of copper. The second flat plate 1b is preferably made of a resin cured body made of a cured insulation resin or metal such as stainless steel and 42 alloy. The combined support plate 1 should be such that the total thickness of the first flat plate 1a and the second flat plate 1b is a thickness at which warpage does not occur due to the formation of an insulation material layer that will be described later.
The details are the same as those described based on
When being cut off along cut lines CL as shown in
| Number | Date | Country | Kind |
|---|---|---|---|
| 2014-149989 | Jul 2014 | JP | national |
