Patent Application
20160133702
A claim of priority under 35 U.S.C. §119 is made to Korean Patent Application No. 10-2014-0153739, filed on Nov. 6, 2014, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
The inventive concepts described herein relate to semiconductor devices and methods of manufacturing semiconductor devices, and more particularly, to semiconductor devices including a lateral diffused metal oxide semiconductor (LDMOS) transistor and methods of manufacturing such semiconductor devices.
Responsive to the recent increase in use of mobile devices such as cellular phones, notebooks, PCs, etc., the demand for power semiconductor devices is rapidly increasing. Power semiconductor devices may be divided into power switching devices and control integrated circuits (ICs). An ideal power switching device used in a power semiconductor device should have a high breakdown voltage that is endurable when switched off, a large allowable current, a small on-resistance, a small amount of switch driving power, and short switching time when switched on. To implement an ideal power switching device for use in a power semiconductor device, it is necessary to secure an extended safe operating area (SOA).
The inventive concept herein relates to a semiconductor device capable of securing an extended safe operating area (SOA), providing excellent electrical performance, and having a structure capable of being employed in a highly scaled high integrated semiconductor device.
The inventive concept also relates to a method of manufacturing a semiconductor device capable of securing an SOA, providing excellent electrical performance, and being employed in a highly scaled high integrated semiconductor device by using a simplified process.
Embodiments of the inventive concept provide a semiconductor device including a substrate having an active region of a first conductive type; a drift region of a second conductive type in the active region; a gate covering the active region and in the drift region; a gate insulating film disposed between the active region and the gate; a drain region of the second conductive type in the drift region, spaced apart from the gate, and having a higher doping concentration than the drift region; a shallow well region of the first conductive type between the gate and the drain region and spaced apart from the drain region, and in the drift region; and a source region of the second conductive type in the shallow well region between the gate region and the drain region and having a higher doping concentration than the shallow well region.
In some embodiments, the semiconductor device may further include an insulating spacer covering side surfaces of the gate. The source region is adjacent to the insulating spacer and spaced apart from the gate, and the gate insulating film and the insulating spacer are between the source region and the gate.
In some embodiments, the semiconductor device may further include a body contact region of the first conductive type in the shallow well region of the first conductive type between the source region and the drain region, and spaced apart from the drain region.
In some embodiments, the substrate may include a main surface; and a fin type semiconductor region protruding from the main surface and extending in a first direction parallel to the main surface of the substrate. The active region is defined in the fin type semiconductor region.
In some embodiments, the gate may extend in a second direction crossing the active region on the substrate.
In some embodiments, the gate may include a first vertical gate unit and a second vertical gate unit facing two side surfaces of the active region. The gate insulating film is between the first vertical gate unit and one of the two side surfaces of the active region, and between the second vertical gate unit and an other of the two side surfaces of the active region.
In some embodiments, the gate may include a first vertical gate unit, a second vertical gate unit, and a horizontal gate unit integrally connected to the first vertical gate unit and the second vertical gate unit. The first vertical gate unit and the second vertical gate unit face two side surfaces of the active region, with the gate insulating film therebetween. The horizontal gate unit faces an upper surface of the active region, and the gate insulating film is between the horizontal gate unit and the upper surface of the active region.
In some embodiments, the substrate may be a bulk substrate, and the gate is a planar type gate on the bulk substrate.
Embodiments of the inventive concept provide a semiconductor device including a substrate having an active region of a first conductive type; a drift region of a second conductive type in the active region; a gate region including at least one gate covering the active region and on the drift region; at least one gate insulating film disposed between the active region and the at least one gate; a first shallow well region and a second shallow well region of the first conductive type in the drift region and spaced apart from each other, the gate region is between the first shallow well region and the second shallow well region. The semiconductor device further includes a first source region of the second conductive type in the first shallow well region and having a higher doping concentration than the first shallow well region; a second source region of the second conductive type in the second shallow well region and having a higher doping concentration than the first shallow well region; and a first drain region and a second drain region of the second conductive type in the drift region and spaced apart from each other and the gate region. The first shallow well region and the second shallow well region are between the first drain region and the second drain region, and the first drain region and the second drain region have a higher doping concentration than the drift region.
In some embodiments, the gate region may include a common gate and the semiconductor device may include a first lateral diffused metal oxide semiconductor (LDMOS) transistor including the first source region and the first drain region in the drift region, and a second LDMOS transistor including the second source region and the second drain region in the drift region. The common gate is shared by the first LDMOS transistor and the second LDMOS transistor.
In some embodiments, the semiconductor device may further include a first insulating spacer and a second insulating spacer covering side surfaces of the common gate. The first source region is formed adjacent to the first insulating spacer and the second source region is formed adjacent to the second insulating spacer.
In some embodiments, the semiconductor device may further include a first body contact region of the first conductive type in the first shallow well region, between the first source region and the first drain region, and spaced apart from the first drain region; and a second body contact region of the first conductive type in the second shallow well region, between the second source region and the second drain region, and spaced apart from the second drain region.
In some embodiments, the gate region may include a first gate and a second gate spaced apart from each other, and the semiconductor device may include a first LDMOS transistor including the first gate region, the first source region, and the first drain region in the drift region; and a second LDMOS transistor including the second gate region, the second source region, and the second drain region in the drift region.
In some embodiments, the semiconductor device may further include a first insulating spacer covering side surfaces of the first gate and a second insulating spacer covering side surfaces of the second gate. The first source region is adjacent to the first insulating spacer and the second source region is adjacent to the second insulating spacer.
In some embodiments, the semiconductor device may further include a first body contact region of the first conductive type in the first shallow well region, between the first source region and the first drain region, and spaced apart from the first drain region; and a second body contact region of the first conductive type in the second shallow well region, between the second source region and the second drain region, and spaced apart from the second drain region.
In some embodiments, the semiconductor device may further include a device isolation film in the drift region, between the first gate and the second gate.
In some embodiments, the semiconductor device may further include a first body contact region of the first conductive type in the first shallow well region, between the first source region and the first drain region, and spaced apart from the first drain region; a second body contact region of the first conductive type in the second shallow well region, between the second source region and the second drain region, and spaced apart from the second drain region; and a third body contact region in the drift region, between the first gate and the second gate.
In some embodiments, the semiconductor device may further include a first body contact region of the first conductive type in the first shallow well region, between the first source region and the first drain region, and spaced apart from the first drain region; a second body contact region of the first conductive type in the second shallow well region, between the second source region and the second drain region, and spaced apart from the second drain region; and an impurity region of the first conductive type in the drift region between the first gate and the second gate. The impurity region is electrically floating.
In some embodiments, the substrate may include a main surface and a fin type semiconductor region protruding from the main surface of the substrate and extending in a first direction parallel to the main surface of the substrate. The active region is defined in the fin type semiconductor region.
In some embodiments, the at least one gate may extend in a second direction crossing the active region on the substrate.
In some embodiments, the at least one gate may be line shaped and covers two side surfaces of the fin type semiconductor region. The at least one gate insulating film may be between the at least one gate and both side surfaces of the fin type semiconductor region.
In some embodiments, the substrate may be a bulk substrate, and the at least one gate may be a planar type gate on the bulk substrate.
Embodiments of the inventive concept provide a semiconductor device including a fin type active region of a first conductive type on a substrate and extending in a first direction; a gate region on the substrate, extending in a direction crossing the fin type active region, and including at least one gate covering two side surfaces of the fin type active region; a first source region and a second source region of a second conductive type in the fin type active region at two side surfaces of the gate region; a first drain region of the second conductive type in the fin type active region and spaced apart from the gate region, wherein the first source region is between the first drain region and the gate region; a second drain region of the second conductive type in the fin type active region and spaced apart from the gate region, wherein the second source region is between the second drain region and the gate region; and a drift region of the second conductive type in the fin type active region and surrounding the gate region, the first source region, the second source region, the first drain region, and the second drain region.
In some embodiments, the semiconductor device may further include a first well of the first conductive type in the drift region and surrounding the first source region; and a second well of the first conductive type in the drift region and surrounding the second source region.
In some embodiments, the semiconductor device may further include a first body contact region of the first conductive type adjacent to the first source region and in the first well, wherein the first body contact region has a higher doping concentration than the first well; and a second body contact region of the first conductive type adjacent to the second source region and in the second well, wherein the second body contact region has a higher doping concentration than the second well.
In some embodiments, the gate region may include a common gate, and the semiconductor device may include a first LDMOS transistor including the first source region and the first drain region in the drift region; and a second LDMOS transistor including the second source region and the second drain region in the drift region. The common gate may be shared by the first LDMOS transistor and the second LDMOS transistor.
In some embodiments, the gate region may include a first gate and a second gate spaced apart from each other, and the semiconductor device may include a first LDMOS transistor including the first gate region, the first source region, and the first drain region in the drift region; and a second LDMOS transistor including the second gate region, the second source region, and the second drain region in the drift region.
In some embodiments, the semiconductor device may further include a first conductive type body contact region between the first gate and the second gate.
In some embodiments, the semiconductor device may further include a device isolation film between the first gate and the second gate.
Embodiments of the inventive concept provide a semiconductor device including a fin type active region of a first conductive type on a substrate and extending in a first direction; a gate on the substrate, extending in a direction crossing the fin type active region, and covering two side surfaces of the fin type active region; a drift region in the fin type active region; a drain region of a second conductive type in the drift region and spaced apart from the gate by a first distance; a shallow well region of the first conductive type in the fin type active region; and a source region of the second conductive type in the shallow well region and spaced apart from the gate by a second distance smaller than the first distance.
Embodiments of the inventive concept provide a semiconductor device including a substrate including an active region of a first conductive type; a drift region of a second conductive type in the active region; and two LDMOS transistors sharing the drift region and disposed symmetrically within the drift region.
In some embodiments, the two LDMOS transistors may include one common gate shared by the two LDMOS transistors. The two LDMOS transistors are disposed symmetrically with respect to the common gate.
In some embodiments, the two LDMOS transistors may include a first LDMOS transistor including a first gate and a second LDMOS transistor including a second gate spaced apart from the first gate. The two LDMOS transistors are disposed symmetrically with respect to the first gate and the second gate.
Embodiments of the inventive concept provide a method of manufacturing a semiconductor device, the method including forming a drift region of a second conductive type in an active region of a substrate, wherein the active region is of a first conductive type; forming a shallow well region of a first conductive type in the drift region; sequentially forming a gate insulating film and a gate, the gate including a corner portion overlapping with the shallow well region in the active region; forming a drain region of a second conductive type in the drift region, adjacent to and spaced apart from the gate and the shallow well region; and forming a source region in the shallow well region, between the gate and the drain region.
In some embodiments, the method may further include forming a body contact region of a first conductive type in the shallow well region, between the source region and the drain region.
In some embodiments, the active region may be configured as a fin type active region including two side walls and an upper surface. The forming of the gate includes forming the gate to cover the two side walls and the upper surface of the fin type active region.
Embodiments of the inventive concept provide a method of manufacturing a semiconductor device, the method including forming a second conductive type drift region in a first conductive type active region of a substrate; and forming two LDMOS transistors in the drift region.
In some embodiments, the forming of the two LDMOS transistors may include forming a common gate shared by the two LDMOS transistors. The two LDMOS transistors are disposed symmetrically with respect to the common gate.
In some embodiments, the forming of the two LDMOS transistors may include forming two gates shared by the two LDMOS transistors. The two LDMOS transistors are disposed symmetrically with respect to the two gates.
Embodiments of the inventive concept provide a method of manufacturing a semiconductor device, the method including forming a second conductive type drift region in a first conductive type active region of a substrate; forming a first shallow well region and a second shallow well region both of a first conductive type in the drift region; forming at least one gate in the active region between the first shallow well region and the second shallow well region; forming a first drain region and a second drain region in the drift region, wherein the first shallow well region and the second shallow well region are between the first drain region and the second drain region; and forming a first source region in the first shallow well region and a second source region in the second shallow well region.
In some embodiments, the forming of the first drain region and the second drain region may include forming the first drain region in a location spaced apart from the first shallow well region, wherein the first shallow well region is between the first drain region and the at least one gate; and forming the second drain region in a location spaced apart from the second shallow well region, wherein the second shallow well region is between the second drain region and the at least one gate.
In some embodiments, the forming of the at least one gate may include forming one common gate including a first corner portion overlapping with the first shallow well region and a second corner portion overlapping with the second shallow well region.
In some embodiments, the forming of the at least one gate may include forming a first gate including a corner portion overlapping with the first shallow well region; and forming a second gate including a corner portion overlapping with the second shallow well region and spaced apart from the first gate.
In some embodiments, the forming of the first gate and the forming of the second gate are simultaneously performed.
Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
Hereinafter, the inventive concept will be described in detail by explaining exemplary embodiments of the inventive concept with reference to the attached drawings. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.
The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, lengths and sizes of layers and regions may be exaggerated for clarity.
Also, though terms like ‘first’ and ‘second’ are used to describe various elements, components, regions, layers, and/or portions in various embodiments of the inventive concept, the elements, components, regions, layers, and/or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another. Thus, a first element, component, region, layer or portion discussed below could be termed a second element, component, region, layer or portion without departing from the teachings of the inventive concept.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
When a certain embodiment can be embodied in a different manner, a specified process order may be performed in a different manner in order to be described. For example, two processes to be described sequentially may be substantially performed at the same time or may be performed in an order opposite to the order to be described.
As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the inventive concept should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
In the present specification, the term MOS (metal-oxide-semiconductor) is a term widely used in the field of semiconductors. “M” is not limited to only metal, and “M” may refer to conductors of various types and various shapes. “S” may refer to a substrate or a semiconductor structure. “O” is not limited to an oxide, and “O” may refer to various types of inorganic materials or organic materials. The term “semiconductor” may include a monocrystal, a polycrstyal, an amorphous semiconductor, a Group IV semiconductor, or a compound semiconductor. Conductive types of elements or doping regions may be defined as “P type” or “N type” according to a characteristic of a main carrier, but this is merely for convenience of description and the inventive concept is not limited to the descriptions above. For example, “P type” or “N type” may be used as a more general term “first conductive type” or “second conductive type”. In this regard, the first conductive type may be P type or N type, and the second conductive type may be N type or P type. In reference numerals, an element denoted by a reference numeral with a prime ′ may correspond to an element denoted by a reference numeral without the prime ′, except that the element denoted by the reference numeral with a prime ′ has conductive type opposite to that of the element denoted by the reference numeral without the prime ′.
Hereinafter, N-channel lateral diffused metal oxide semiconductor (LDMOS) devices are described as an example of semiconductor devices according to the inventive concept. However, the example is only for convenience of description and the inventive concept is not limited to the descriptions above. Various semiconductor devices and circuits including a combination of not only P-channel LDMOS devices but also a combination of P-channel LDMOS and N-channel LDMOS devices may be provided through various modifications and changes within the scope of the inventive concept.
Referring to
The substrate 102 may include a semiconductor such as Si or Ge or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. In other example embodiments, the substrate 102 may have a silicon-on-insulator (SOI) structure.
The active region AC may be defined in a fin type semiconductor region limited in a line shape extending in a direction (X direction) parallel to a main surface 102A of the substrate 102 by a device isolation layer 104. The active region AC includes a lower fin active region ACL having a first width W1 and an upper fin active region ACU integrally connected to the lower fin active region ACL and having a second width W2 smaller than the first width W1. Each of the lower fin active region ACL and the upper fin active region ACU may have the line shape extending in the direction (X direction) parallel to the main surface 102A of the substrate 102.
The device isolation layer 104 has an upper surface of a higher level than that of an upper surface of the lower fin active region ACL. The upper fin active region ACU protrudes upward in a Z direction from the lower fin active region ACL to a level higher than that of the upper surface of the device isolation layer 104. In
The device isolation layer 104 may be formed as an oxide layer, a nitride layer, or a combination of these but is not limited thereto.
The gate 120 has a line shape extending in a direction (Y direction) crossing the active region AC on the substrate 102. The gate 120 includes a first vertical gate unit 120A and a second vertical gate unit 120B facing both sides of the upper fin active region ACU with the gate insulating layer 122 therebetween, and a horizontal gate unit 120C facing an upper surface of the upper fin active region ACU with the gate insulating layer 122 therebetween. Accordingly, a triple gate structure in which channels are formed in both sides and the upper surface of the upper fin active region ACU is implemented. In other embodiments, differently then as shown in
A gate contact terminal GCT is connected to the gate 120. A metal silicide layer, for example a nickel silicide layer, may be disposed between the gate 120 and the gate contact terminal GCT. An ohmic contact may be formed between the gate 120 and the gate contact terminal GCT.
The gate 120 may be formed of conductive polysilicon, metal, conductive metal nitride, or a combination of these. Each of the metal and the conductive metal nitride may include at least one selected from the group consisting of Ti, Ta, W, Ru, Nb, MO, and Hf, while not limited thereto. The metal nitride may be formed of TiN, TaN, or a combination of these, while not limited thereto. The gate 120 may be formed through chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), metal organic ALD (MOALD), or metal organic CVD (MOCVD)
The gate insulating layer 122 may be formed of silicon oxide film, a high dielectric film, or a combination of these. The high dielectric film may be formed of a material having a higher dielectric constant than that of silicon oxide film. For example, the gate insulating layer 122 may have a dielectric constant from about 10 and to about 25. The high dielectric film may be formed of a material selected from the group consisting of hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, while not limited thereto. The gate insulating layer 122 may be formed through ALD, CVD, or PVD.
Both sides of each of the gate 120 and the gate insulating layer 122 may be covered by an insulating spacer 126. The insulating spacer 126 may be formed as an oxide film, a nitride film, or a combination of these.
To implement the semiconductor device 100 formed of the N-channel LDMOS, the drift region 110 is formed as an N type doping region. A drain region 112 is formed in a position spaced apart from the gate 120 in the drift region 110. The drain region 112 is formed as an N+ type doping region having a higher doping concentration than that of the drift region 110. Side surfaces and the bottom surface of the drain region 112 are surrounded by the drift region 110.
The drain contact terminal DCT is connected to the drain region 112. In some embodiments, a metal silicide film, for example a nickel silicide film, may be disposed between the drain region 112 and the drain contact terminal DCT. An ohmic contact may be formed between the drain region 112 and the drain contact terminal DCT.
A first conductive type shallow well region 130 is formed spaced apart from the drain region 112 in the drift region 110. The shallow well region 130 is formed to overlap with a corner portion CN indicated in a broken line in
A source region 132 is formed in the shallow well region 130 between the gate 120 and the drain region 112. The source region 132 is formed as an N+ type doping region having a higher doping concentration than that of the shallow well region 130. Side surfaces and the bottom surface of the source region 132 are surrounded by the shallow well region 130. In other embodiments the source region 132 may be formed at a position spaced apart from the gate 120 with the gate insulating layer 122 and the insulating spacer 126 therebetween.
An extension region 134 formed as an N type doping region having a lower doping concentration than that of the source region 132 is formed in a lower portion of the gate 120 in one side of the source region 132 in the active region AC. A source region of a lightly doped drain (LDD) structure is formed by the source region 132 and the extension region 134. The extension region 134 may be formed in a position arranged by the gate 120. The source region 132 may be formed in a position arranged by the insulating spacer 126.
A source contact terminal SCT is formed in the source region 132. In some embodiments, a metal silicide layer, for example a nickel silicide layer, may be disposed between the source region 132 and the source contact terminal SCT. An ohmic contact may be formed between the source region 132 and the source contact terminal SCT.
A body contact region 136 is formed in a position adjacent to the source region 132 in the shallow well region 130. The body contact region 136 is formed between the source region 132 and the drain region 112 in the shallow well region 130. The body contact region 136 has a higher doping concentration than that of the shallow well region 130. The body contact region 136 is formed as a P+ type doping region.
A body contact terminal BCT is connected to the body contact region 136. In some embodiments, a metal silicide layer, for example a nickel silicide layer, may be disposed between the body contact region 136 and the body contact terminal BCT. An ohmic contact may be formed between the body contact region 136 and the body contact terminal BCT.
The source region 132 and the body contact region 136 are adjacent to each other in
In the semiconductor device 100 described with reference to
When the semiconductor device 100 is in a stand-by state, a high voltage may be applied to the drain region 112 while the gate 120, the body contact region 132, and the source region 132 are grounded. To operate the semiconductor device 100, a voltage may be applied to the gate 120 when in the stand-by state. When a voltage higher than a limit voltage of the semiconductor device 100 is applied to the gate 120, electrons move to the drain region 112 from the source region 132 through a channel path inside the upper fin active region ACU. As indicated by the arrow AR shown in
The source region 132 and the body contact region 136 are formed in the drift region 110, and thus not only is the specific on-resistance Rsp reduced, but an area occupied by one LDMOS transistor may be dramatically reduced compared to a case where the source region 132 and the body contact region 136 are formed outside the drift region 110. That is, as a comparative example, when the source region 132 and the body contact region 136 are formed outside the drift region 110 at an opposite side of the drift region 110 with respect to the gate 120, the specific on-resistance Rsp may be undesirably increased between the gate 120 and the drain region 112 in the drift region 110. However, the source region 132 and the body contact region 136 occupy a part of the drift region 110 that may cause the specific on-resistance Rsp, and thus the semiconductor device 100 according to the inventive concept where the source region 132 and the body contact region 136 are formed in the drift region 110 may reduce the specific on-resistance Rsp between the gate 120 and the drain region 112 in the drift region 110. When compared to the structure of the comparative example in which the source region 132 and the body contact region 136 are formed outside the drift region 110 and occupy a separate area, the separate area outside the drift region 110 is unnecessary, and thus an area occupied by one LDMOS transistor may be dramatically reduced. Thus, the semiconductor device 100 may be preferably employed in a highly scaled high integrated semiconductor device.
The semiconductor device 200 generally includes the same elements as those of the semiconductor device 100 of
The body contact terminal BCT is connected to the body contact region 236. However, according to other embodiments, the body contact terminal BCT connected to the body contact region 236 may be omitted. In some embodiments, the body contact region 236 may include an electrically floating well region.
The semiconductor device 300 generally includes the same elements as those of the semiconductor device 100 of
Referring to
A buried layer 404 is formed on the substrate 402. The buried layer 404 is configured as a buried layer doped with a second conductive type, for example, N type, impurity.
An epitaxial layer 406 is formed on the buried layer 404. The epitaxial layer 406 is doped with the second conductive type, for example N type impurity. However, a doping concentration of the epitaxial layer 406 may be lower than that of the buried layer 404.
An LDMOS transistor including a planar type gate 420 and having a similar structure as that described with reference to
The drain region 112 spaced apart from the planar type gate 420 is formed in the drift region 110.
The shallow well region 130 is formed between the gate 420 and the drain region 112 in the drift region 110. The shallow well region 130 is formed to overlap with one side corner portion CNP of the gate 420. The source region 132 configured as an N+ type doping region is formed in a position adjacent to the planar type gate 420 in the shallow well region 130. The body contact region 136 is formed in the shallow well region 130 between the source region 132 and the drain region 112.
In the semiconductor device 400 illustrated in
Referring to
The common gate 520 has have a line shape extending in a direction (Y direction) crossing the active region AC on the substrate 102. The common gate 520 includes a first vertical gate unit 520A and a second vertical gate unit 520B facing both sides of the upper fin active region ACU with the gate insulating film 522 therebetween, and a horizontal gate unit 520C integrally connected to the first vertical gate unit 520A and the second vertical gate unit 520B and facing an upper surface of the upper fin active region ACU with the gate insulation film 522 therebetween. Accordingly, a triple gate structure in which channels are formed in both sides and the upper surface of the upper fin active region ACU is implemented. Unlike the triple gate structure, in other embodiments a double gate structure in which a channel is not formed in the upper surface of the upper fin active region ACU and channels are formed in both sides of the upper fin active region ACU may be implemented, the double gate structure having first and second vertical gate units without a horizontal gate unit.
The gate contact terminal GCT is connected to the common gate 520. In some embodiments, a metal silicide layer, for example a nickel silicide layer, may be disposed between the common gate 520 and the gate contact terminal GCT. An ohmic contact may be formed between the common gate 520 and the gate contact terminal GCT. Both sides of the common gate 520 and the gate insulating film 522 may be covered with an insulating spacer 526.
For more details with respect to the common gate 520 and the gate insulating film 522, the descriptions of gate 120 and the gate insulating film 122 provided with reference to
A P type first shallow well region 130A and a second shallow well region 130B that are spaced apart from each other with the common gate 520 therebetween are formed in the drift region 110. An N+ type first source region 132A is formed in the first shallow well region 130A. An N+ type second source region 132B is formed in the second shallow well region 130B.
A first drain region 112A and a second drain region 112B that are spaced apart from each other with the common gate 520, the first shallow well region 130A, and the second shallow well region 130B therebetween are formed in the drift region 110. The first drain region 112A and the second drain region 112B are configured as N+ type doping regions having a higher doping concentration than that of the drift region 110. The first drain region 112A and the second drain region 112B have side surfaces and bottom surfaces surrounded by the drift region 110.
The first source region 132A is formed between the common gate 520 and the first drain region 112A. Side surfaces and the bottom surface of the first source region 132A are surrounded by the first shallow well region 130A. The second source region 132B is formed between the common gate 520 and the second drain region 112B. Side surfaces and the bottom surface of the second source region 132B is surrounded by the second shallow well region 130B.
The first source region 132A and the second source region 132B are formed in a position spaced apart from the common gate 520 with the gate insulating film 522 and the insulating spacer 526 therebetween.
The source contact terminals SCT are formed in the first source region 132A and the second source region 132B. In some embodiments, a metal silicide layer, for example a nickel silicide layer, may be disposed between the first source region 132A and the second source region 132B and the source contact terminals SCT. An ohmic contact may be formed between the first source region 132A and the second source region 132B and the source contact terminals SCT.
The drain contact terminals DCT are connected to each of the first drain region 112A and the second drain region 112B. In some embodiments, a metal silicide layer, for example a nickel silicide layer, may be disposed between the first drain region 112A and the second drain region 112B and the drain contact terminals DCT. An ohmic contact may be formed between the first drain region 112A and the second drain region 112B and the drain contact terminals DCT.
The first shallow well region 130A and the second shallow well region 130B are respectively formed to partially overlap with both side corner portions CN1 and CN2 of the common gate 520, as indicated in broken line regions in
The first shallow well region 130A and the second shallow well region 130B are configured as P type doping regions. The first shallow well region 130A and the second shallow well region 130B are formed as having smaller depth than that of the drift region 110 in the active region AC. Accordingly, each of the first shallow well region 130A and the second shallow well region 130B have side surfaces and bottom surfaces surrounded by the drift region 110.
A first extension region 134A and a second extension region 134B configured as N type doping regions having a lower doping concentration than that of the first source region 132A and the second source region 132B are disposed at lower parts of the common gate 520 in one side of each of the first source region 132A and the second source region 132B respectively, in the active region AC. A first source region having an LDD structure is thus formed by the first source region 132A and the first extension region 134A. A second source region having an LDD structure is thus formed by the second source region 132B and the second extension region 134B.
A first body contact region 136A is formed in a position adjacent to the first source region 132A in the first shallow well region 130A. A second body contact region 136B is formed in a position adjacent to the second source region 132B in the second shallow well region 130B. The first body contact region 136A is formed between the first source region 132A and the first drain region 112A in the first shallow well region 130A, and has a higher doping concentration than that of the first shallow well region 130A. The second body contact region 136B is formed between the second source region 132B and the second drain region 112B in the second shallow well region 130B, and has a higher doping concentration than that of the second shallow well region 130B. The first body contact region 136A and the second body contact region 136B are configured as P+ type doping regions.
The body contact terminals BCT are connected to each of the first body contact region 136A and the second body contact region 136B. In some embodiments, a metal silicide layer, for example a nickel silicide layer, may be disposed between the first body contact region 136A and the second body contact region 136B and the body contact terminals BCT. An ohmic contact may be formed between the first body contact region 136A and the second body contact region 136B and the body contact terminals BCT.
In the semiconductor device 500 described with reference to
In a stand-by status of the semiconductor device 500, a high voltage may be applied to the first drain region 112A and the second drain region 112B in a state in which the common gate 520, the first source region 132A, the first body contact region 136A, the second source region 132B, and the second body contact region 136B are grounded. To operate the semiconductor device 500, a voltage may be applied to the common gate 520 when in the stand-by status. When a voltage more than a limit voltage of the semiconductor device 500 is applied to the common gate 520, electrons move to the first drain region 112A and the second drain region 112B through each of channel paths inside the upper fin active region ACU from the first source region 132A and the second source region 132B. Current flows to the first drain region 112A and the second drain region 112B from the first source region 132A and the second source region 132B through the channel paths, and via lower portions of the upper fin active region ACU and the drift region 110 in the lower fin active region ACL. In this regard, since the first LDMOS transistor TR1 and the second LDMOS transistor TR2 have reciprocally symmetrical shape with respect to the common gate 520, in addition to a main current flow path starting from the first source region 132A and the second source region 132B as indicated in arrows AR1 and AR2, an auxiliary current flow path crossing to the first drain region 112A and to the second drain region 112B included in the first LDMOS transistor TR1 and the second LDMOS transistor TR2 is additionally formed as indicated by dotted line arrows AR3 and AR4. Accordingly, resistance is further reduced in the drift region 110.
As described above, since the first source region 132A and the first body contact region 136A, and the second source region 132B and the second body contact region 136B are formed in the drift region 110 in the semiconductor device 500, the specific on-resistance Rsp formed between the common gate 520 and the first drain region 112A, and between the common gate 520 and the second drain region 112B, is reduced in the drift region 110. The first shallow well region 130A and the second shallow well region 130B are present between the corner portion of the common gate 520 and the drift region 110 so that the common gate 520 and the drift region 110 do not directly contact each other. Thus, as indicated by the arrows AR1, AR2, AR3, and AR4 in
In the semiconductor device 500, since the first source region 132A and the first body contact region 136A, and the second source region 132B and the second body contact region 136B, are formed in the drift region 110, the specific on-resistance Rsp formed between the common gate 520 and the first drain region 112A and between the common gate 520 and the second drain region 112B is reduced in the drift region 110, compared to a case where the first source region 132A and the first body contact region 136A, and the second source region 132B and the second body contact region 136B, are formed outside the drift region 110. Compared to a structure in which the first source region 132A and the first body contact region 136A, and the second source region 132B and the second body contact region 136B are formed outside the drift region 110 and occupy a separate area, an area occupied by one LDMOS transistor is dramatically reduced. Thus, the semiconductor device 500 may be preferably employed in a highly scaled high integrated semiconductor device.
Referring to
A fifth shallow well region 630C is formed in the active region AC under the common gate 520 in the drift region 110. The fifth shallow well region 630C is configured as an N type impurity doping region. The fifth shallow well region 630C is disposed between the first shallow well region 130A and the second shallow well region 130B. Resistance in a part of the drift region 110 providing a main current flow path and an auxiliary current flow path as indicated in the arrows AR1, AR2, AR3, and AR4 of
The semiconductor device 700 generally includes the same configuration as that of the semiconductor device 500 described with reference to
A first gate insulating film 722A is disposed between the active region AC and the first gate 720A. Both side walls of the first gate 720A and the first gate insulating film 722A are covered by a first insulating spacer 726A.
A second gate insulating film 722B is disposed between the active region AC and the second gate 720B. Both side walls of the second gate 720B and the second gate insulating film 722B are covered by a second insulating spacer 726B.
A third body contact region 736 is further provided in a region between the first gate 720A and the second gate 720B in the drift region 110. The body contact terminal BCT is connected to the third body contact region 736.
In the semiconductor device 700 illustrated in
The semiconductor device 800 generally includes the same configuration as that of the semiconductor device 700 described with reference to
The semiconductor device 900 illustrated in
The semiconductor device 1000 generally includes the same configuration as that of the semiconductor device 900 described with reference to
Referring to
Similarly to the semiconductor device 500 illustrated in
In the semiconductor device 1100 illustrated in
The semiconductor device 1200 generally includes similar elements to those of the semiconductor device 500 described with reference to
The semiconductor device 1300 includes generally similar elements to those of the semiconductor device 700 illustrated in
The semiconductor device 1400 includes generally similar elements to those of the semiconductor device 900 illustrated in
The semiconductor device 1500 includes generally similar elements to those of the semiconductor device 1000 illustrated in
The CMOS inverter 1600 is configured as an inversion circuit including an N-channel LDMOS transistor 1610 and a P-channel LDMOS transistor 1620. When an input signal Vin of the CMOS inverter 1600 is high, the P-channel LDMOS transistor 1620 is turned off, and the N-channel LDMOS transistor 1610 is turned on, a low signal is output as an output signal Vout. To the contrary, when the input signal Vin of the CMOS inverter 1600 is low, the P-channel LDMOS transistor 1620 is turned on, and the N-channel LDMOS transistor 1610 is turned off, a high signal is output as the output signal Vout.
The common gate 520 of the N-channel LDMOS transistor 1610 and a common gate 520′ of the P-channel LDMOS transistor 1620 are connected to the gate contact terminals GCT, and an input signal terminal 1652 through a wiring M11 connected to the gate contact terminals GCT.
The first source regions 132A, the second source regions 132B, the first body contact regions 136A, and the second body contact regions 136B of the N-channel LDMOS transistor 1610 are connected to the source contact terminals SCT, the body contact terminals BCT, and a reference electric potential terminal 1654 through a wiring M12 connected to the source contact terminals SCT and the body contact terminals BCT.
The first source regions 132A′, second source regions 132B′, first body contact regions 136A′, and second body contact regions 136B′ of the P-channel LDMOS transistor 1620 are connected to the source contact terminals SCT, the body contact terminals BCT, and a supply terminal 1656 through a wiring M13 connected to the source contact terminals SCT and the body contact terminals BCT.
The first drain regions 112A and the second drain regions 112B of the N-channel LDMOS transistor 1610, and the first drain regions 112A′ and the second drain regions 112B′ of the P-channel LDMOS transistor 1620 are connected to the drain contact terminals DCT and an output terminal 1658 through a wiring M14 connected to the drain contact terminals DCT.
Similarly to the inverter 1600A illustrated in
The first source regions 132A, the second source regions 132B, the first body contact regions 136A, and the second body contact regions 136B of the N-channel LDMOS transistor 1610 are connected to the source contact terminals SCT, the body contact terminals BCT, and the reference electric potential terminal 1654 through a wiring M22 connected to the source contact terminals SCT and the body contact terminals BCT.
The first source regions 132A′, the second source regions 132B′, the first body contact regions 136A′, and the second body contact regions 136B′ of the P-channel LDMOS transistor 1620 are connected to the source contact terminals SCT, the body contact terminals BCT, and the supply terminal 1656 through a wiring M23 connected to the source contact terminals SCT and the body contact terminals BCT.
The first drain regions 112A and the second drain regions 112B of the N-channel LDMOS transistor 1610, and the first drain regions 112A′ and the second drain regions 112B′ of the channel LDMOS transistor 1620 are connected to the drain contact terminals DCT and the output terminal 1658 through a wiring M24 connected to the drain contact terminals DCT.
The CMOS inverters 1600, 1600A, and 1600B illustrated in
Referring to
The active region AC includes the lower fin active region ACL having the first width W1 illustrated in
The insulating film 106 may act to protect the substrate 102 when an ion injection process is performed on the substrate 102. In some embodiments, the insulation film 106 may be formed as an oxide film but is not limited thereto.
In some embodiments, an N type impurity may be doped to form the drift region 110 necessary for an N-channel LDMOS transistor.
Referring to
In some embodiments, a P type impurity may be doped in a partial region of the drift region 110 to form the first shallow well region 130A and the second shallow well region 130B. The first shallow well region 130A and the second shallow well region 130B may be formed to have a smaller depth than that of the drift region 110.
Referring to
The dummy gate 108 may have a line shape extending in a direction crossing the active region AC.
In some embodiments, to form the dummy gate 108, after a dummy gate layer is formed on the insulating film 106 and a mask pattern 109 is formed on the dummy gate layer, a process of etching the dummy gate layer may be performed by using the mask pattern 109 as an etching mask. During the process of etching the dummy gate layer, the insulating film 106 may be removed around the dummy gate 108 and the active region AC may be exposed around the dummy gate 108.
The dummy gate 108 may be formed of polysilicon, and the mask pattern 109 may be formed of silicon nitride but the inventive concept is not limited thereto.
To form the first extension region 134A and the second extension region 134B, a tilt ion injection process may be used to dope the active region AC with the N type impurity. In some embodiments, an ion injection for forming a halo ion injection region (not shown) in the active region AC may be performed during the ion injection process for forming the first extension region 134A and the second extension region 134B.
Referring to
To form the insulating spacer 526, after a spacer insulating film covering an upper surface and both side walls of the dummy gate 108 and the insulating film 106 are formed, the spacer insulating film is etched until the upper surface of the dummy gate 108 is exposed so that the insulating spacer 526 covering both side walls of the dummy gate 108 remains.
The insulating spacer 526 may be formed of silicon nitride, silicon oxynitride, or a combination of these.
Referring to
To form the first drain region 112A, the second drain region 112B, the first source region 132A, and the second source region 132B, after a plurality of source/drain forming trenches are formed by etching some regions of the active region AC, a source/drain forming semiconductor layer may be formed in the plurality of source/drain forming trenches through an epitaxial growth process. The source/drain forming semiconductor layer may be formed of Si or SiC, but is not limited thereto. N+ doping may be simultaneously performed during an epitaxial growth of the source/drain forming semiconductor layer. Accordingly, the first drain region 112A, the second drain region 112B, the first source region 132A, and the second source region 132B may be formed as N+ type semiconductor layers.
Each of the first drain region 112A, the second drain region 112B, the first source region 132A, and the second source region 132B may have a raised source/drain (RSD) structure having an upper surface at a higher level than that of the upper surface of the active region AC.
Referring to
To form the first body contact region 136A and the second body contact region 136B, after a plurality of body contact forming trenches are formed by etching some regions of the active region AC, a body contact forming semiconductor layer may be formed in the plurality of body contact forming trenches through the epitaxial growth process. The body contact forming semiconductor layer may be formed of SiGe, but is not limited thereto. P+ doping may be simultaneously performed during an epitaxial growth of the body contact forming semiconductor layer. Accordingly, the first body contact region 136A and the second body contact region 136B may be formed as P+ type semiconductor layers.
The first body contact region 136A and the second body contact region 136B may have an RSD structure having an upper surface at a higher level than that of the upper surface of the active region AC.
In some embodiments, a process of additionally doping the first drain region 112A, the second drain region 112B, the first source region 132A, and the second source region 132B with the N+ impurity may be selectively performed, and a process of additionally doping the first body contact region 136A and the second body contact region 136B with the P+ impurity may be selectively performed. Such additional doping processes are performed, thereby reducing resistances in the first drain region 112A, the second drain region 112B, the first source region 132A, the second source region 132B, the first body contact region 136A, and the second body contact region 136B.
Referring to
As an example of forming the inter-gate insulating film 115, an insulating film having a sufficient thickness to cover the dummy gate 108 and the insulating spacer 526 may be formed on the active region AC. Thereafter, the inter-gate insulating film 115 having a planarized upper surface may be formed by planarizing the formed insulating film so that the dummy gate 108 may be exposed. In some embodiments, the inter-gate insulating film 115 may be formed of an oxide film, a nitride film, or a combination of these. In some embodiments, the inter-gate insulating film 115 may be formed as a tetra ethyl ortho silicate (TEOS) film. In other embodiments, the inter-gate insulating film 115 may be formed as an ultra low K (ULK) having an ultra low dielectric constant K of about 2.2˜about 2.4, for example, one selected from an SiOC film and an SiCOH film.
Referring to
In some embodiments, before the gate insulating film 522 is formed in the gate space GS, a process of forming an interface film (not shown) on a surface of the active region AC exposed through the gate space GS may be further performed. To form the interface film, a process of oxidizing a part of the active region AC exposed in the gate space GS may be performed. The interface film may act to prevent an interface defect between the gate insulating film 522 formed on the interface film and an active region ACT below the interface film. In some embodiments, the interface film may be formed of a silicon oxide film, a silicon oxynitride film, a silicate film, or a combination of these.
The gate insulating film 522 may be formed of a silicon oxide film, a high dielectric film, or a combination of these. The high dielectric film may be formed of a material having a higher dielectric constant than that of the silicon oxide film. For example, the gate insulting film 522 may have a dielectric constant in the range of about 10 through about 25.
The common gate 520 may be formed of metal, conductive metal nitride, or a combination of these. In some embodiments, the common gate 520 may have a structure in which a conductive metal nitride layer, a metal layer, a conductive capping layer, and a gap-fill metal layer are sequentially stacked. Each of the metal nitride layer and the metal layer may include at least one metal selected from Ti, Ta, W, Ru, Nb, and Hf. The metal nitride layer and the metal layer may be formed by ALD, MOALD, or MOCVD. The conductive capping layer may act as a protection film preventing a surface of the metal layer from being oxidized. The conductive capping layer may act as a wetting layer used to easily deposit another conductive layer on the metal layer. The conductive capping layer may be formed of metal nitride, for example, TiN, TaN, or a combination of these but is not limited thereto. The gap-fill metal layer may be formed of a W film. The gap-fill metal layer may be formed through ALD, CVD, or PVD process.
Referring to
Although not shown, the plurality of contact holes 119 may include a contact hole exposing the common gate 520.
In some embodiments, the insulating film 117 may be formed of an oxide film, a nitride film, or a combination of these. In some embodiments, the insulating film 117 may include the same material as that of the material of the inter-gate insulating film 115.
Referring to
Although not shown, a metal silicide film such as metal silicide film 125 may be formed covering the surface of the common gate 520 in contact holes such as contact holes 119 exposing the common gate 520, and contact plugs such as contact plugs 127 may be formed filling such contact holes exposing the common gate 520.
In some embodiments, the metal silicide film 125 may be formed of nickel silicide, cobalt silicide, or a combination of these, but is not limited thereto.
In some embodiments, the plurality of contact plugs 127 may include a conductive bather film and a metal plug. The conductive bather film may be formed of Ti, Ta, TiN, TaN, or a combination of these. The metal plug may be formed of W.
Thereafter, devices performing a desired function may be implemented by forming wirings (not shown) selectively connected to the plurality of contact plugs 127.
Referring to
Thereafter, in the same manner as described with reference to
The plurality of dummy gates 208 may have a line shape extending in a direction crossing the active region AC.
In some embodiments, to form the plurality of dummy gates 208, after a dummy gate layer is formed on the insulating film 106 and a plurality of mask patterns 209 are formed on the dummy gate layer, a process of etching the dummy gate layer may be performed by using the mask pattern 209 as an etching mask. During the process of etching the dummy gate layer, the insulating film 106 may be removed around the plurality of dummy gates 208 and the active region AC may be exposed around the plurality of dummy gates 208.
The plurality of dummy gates 208 may be formed of polysilicon, and the plurality of mask patterns 209 may be formed of silicon nitride, but the inventive concept is not limited thereto.
Referring to
The first insulating spacer 726A and the second insulating spacer 726B may be formed of silicon nitride, silicon oxynitride, or a combination of these.
Referring to
However, during the formation of the first body contact region 136A and the second body contact region 136B, a third body contact region 736 is further formed between the first shallow well region 130A and the second shallow well region 130B in the drift region 110.
Referring to
Referring to
Referring to
Thereafter, in the same manner as described with reference to
The metal silicide film 225 and the plurality of contact plugs 227 may have the configurations as described with respect to the metal silicide film 125 and the plurality of contact plugs 127 with reference to
Thereafter, devices performing a desired function may be implemented by forming wirings (not shown) selectively connected to the plurality of contact plugs 127 and 227.
Referring to
However, in the present embodiment, a process of forming the third body contact region 736 between the first shallow well region 130A and the second shallow well region 130B in the drift region 110 is omitted. Accordingly, a resultant structure in which the drift region 110 is exposed through a space between the two adjacent dummy gates 208 is obtained.
Referring to
Thereafter, devices performing a desired function may be implemented by forming wirings (not shown) selectively connected to the plurality of contact plugs 127.
The processes for manufacturing the semiconductor device 500 illustrated in
In more detail, embodiments 1, 2, and 3 correspond to an N-channel LDMOS transistor including the same elements as those of the semiconductor device 500 having a structure in which the first source region 132A and the first body contact region 136A, and the second source region 132B and the second body contact region 136B, are respectively surrounded by the first shallow well region 130A and the second shallow well region 130B in the drift region 110 as illustrated in
Referring to embodiment 1 and comparative example 1 of
The evaluation results of
In more detail, embodiment 4 of the inventive concept relates to an evaluation result regarding an N-channel LDMOS transistor having the same structure as those of embodiments 1 through 3 used for the evaluation of
For evaluation of
The evaluation results of
Referring to
The PMIC 2120 may receive a voltage from the battery 2110, convert the voltage into a voltage level necessary for each of the plurality of modules 2130, and provide the voltage to the first through fourth modules 2132, 2134, 2136, and 2138. The PMIC 2120 may include a semiconductor device having a structure of one of the semiconductor devices 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, and 1500 according to the embodiments described with reference to
Referring to
A keypad 2280 includes a plurality of keys for inputting numbers and/or character information and a plurality of function keys for setting various functions.
The signal processing unit 2240 may perform a wireless communication function of a portable terminal and may include an RF unit and a modem. The RF unit may include an RF transmitter that modulates and amplifies a frequency of a transmitted signal and an RF receiver that performs low pass filtering on and demodulates a received signal. The modem may include a transmitter that encodes and modulates a signal that is to be transmitted and a receiver that demodulates and decodes the signal received from the RF unit.
The audio processing unit 2250 may be configured as a codec that includes a data codec and an audio codec. The data codec may process packet data. The audio codec may process an audio signal such as voice and a multimedia file. The audio processing unit 2250 performs a function of converting and reproducing a digital audio signal received from the modem into an analog signal through the audio codec or converting an analog audio signal generated from a microphone into the digital audio signal through the audio codec and transmitting the digital audio signal to the modem. The codec may be separately provided or may be included in the control unit 2210 of the portable terminal.
The memory unit 2260 may be configured as a ROM and a RAM. The memory unit 2260 may be configured as a program memory and data memories, and may store programs for controlling an operation of the portable terminal and booting data.
The display unit 2270 may display an image signal and user data on a screen or may display data related to making a call. The display unit 2270 may be formed as a liquid crystal display (LCD) or an organic light emitting diode (OLED). When the LCD or the OLED is implemented as a touch screen, the display unit 2270 may operate as an input unit for controlling the portable terminal along with the keypad 2280.
The control unit 2210 may perform a function of controlling a general operation of the portable terminal. The control unit 2210 may include the PMIC 2220. The PMIC 2220 receives a voltage from the battery 2230 and converts the voltage into a desired voltage level. The PMIC 2220 may include a semiconductor device having a structure of one of the semiconductor devices 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, and 1500 according to the embodiments described with reference to
Referring to
Referring to
While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2014-0153739 | Nov 2014 | KR | national |
