The above and other features and advantages of example embodiments will become more apparent by describing them in detailed with reference to the accompanying drawings.
a illustrates a cross-sectional view at line I-I′ of
b illustrates a cross-sectional view at line II-II′ of
c illustrates a cross-sectional view at line III-III′ of
a illustrates a cross-sectional view of a charge trap type NAND flash memory cells in accordance with example embodiments.
b illustrates a magnified view of area S2 of
c illustrates the relationship between an upper surface of an active region and the channel width in the conventional art.
d illustrates the relationship between an upper surface of an active region, a bottom surface of the groove, and the channel width in example embodiments.
e illustrates a flat bottom groove profile in accordance with example embodiments.
f illustrates an obtuse or rounded bottom groove profile in accordance with example embodiments.
a-5m illustrate a process for manufacturing memory cells in accordance with example embodiments.
Detailed example embodiments are disclosed herein. However, specific structural and/or functional details disclosed herein are merely representative for purposes of describing example embodiments. The claims may, however, may be embodied in many alternate forms and should not be construed as limited to only example embodiments set forth herein.
It will be understood that when a component is referred to as being “on,” “connected to” or “coupled to” another component, it can be directly on, connected to or coupled to the other component or intervening components may be present. In contrast, when a component is referred to as being “directly on,” “directly connected to” or “directly coupled to” another component, there are no intervening components present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one component or feature's relationship to another component(s) or feature(s) as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components.
Unless otherwise defined, all terms (including technical and/or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Reference will now be made to example embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like components throughout. Example embodiments should not be construed as limited to the particular shapes of regions illustrated in these figures but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the claims.
a illustrates a cross-sectional view at line I-I′ of
Each word line (or gate pattern) 180W may further include a floating gate 155, a blocking insulation layer 165, and/or a control gate 175. Each control gate 175 may further include a lower control gate 171 and/or upper control gate 172.
In example embodiments, a bottom of the groove 99 may be lower than an upper face of an active region ACT. In example embodiments, the groove 99 may be formed along an active region ACT. In example embodiments, a channel width of the transistor is proportional of a depth of the groove 99.
In example embodiments, an active region ACT may include a source, a drain and a channel disposed between the source and drain. The gate patterns 180W may include floating gate 155, blocking insulation layer 165, and/or control gate 175. The groove 99 may be filled with gate patterns 180W.
In example embodiments, the tunneling insulation layer 140 may be between the active regions ACT and gate patterns 180W. The tunneling insulation layer 140 may be selected from silicon oxide, silicon nitride and high-k dielectric material, for example, aluminum oxide, hafnium oxide, etc.
In example embodiments, the spacer patterns 135 may remain on the pad oxide 115. In other words, the spacer patterns 135 may be disposed between the active regions ACT and gate patterns 180W. The pad oxide 115 and the spacer patterns 135 may be silicon oxide.
In example embodiments, the width of the channel is no longer the linear distance between adjacent isolation regions 120 or the linear width of each active region ACT. Because the width of the channel is increased by virtue of the depth of the groove, the width of the channel may be increased and the ‘narrow width effect’ may be reduced or minimized.
b illustrates a cross-sectional view at line II-II′ of
c illustrates a cross-sectional view at line III-III′ of
a illustrates a cross-sectional view of charge trap type NAND flash memory cells in accordance with example embodiments. As shown, gate patterns may include an oxide-nitride-oxide (ONO) layer 145 and control gate 187.
b illustrates a magnified view of area S2 of
As described above, in example embodiments, a channel region may be recessed with respect to the active regions. In example embodiments, a bottom surface of the groove 99 may be below an upper surface of an active region, as shown, for example, in
c illustrates the relationship between an upper surface of an active region and the channel width in the conventional art.
a-5m illustrate a process for manufacturing memory cells in accordance with example embodiments. As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
In example embodiments, a floating gate layer may be formed.
As shown in
As shown in
As shown in
In example embodiments, a charge trap layer may be formed.
As shown in
As shown in
In example embodiments, the control gate 175 may be a poly or poly to metal layer.
As shown in
In example embodiment as described above the gate structure may be a floating gate structure, as illustrated in
In example embodiments, the charge trap gate structure may be an ONO structure. In example embodiments, the ONO structure may include a first oxide layer in one or more of the plurality of grooves 99 and on one or more of the plurality of isolation regions 120, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer.
In other example embodiments, the charge trap gate structure may include a tunnel insulating layer in one or more of the plurality of grooves 99 and on one or more of the plurality of isolation regions 120, a charge storage layer on the tunnel insulating layer, a blocking insulating layer on the charge storage layer, the blocking insulating layer having a second dielectric constant which is greater than a first dielectric constant of the tunnel insulating layer; and a gate electrode on the blocking insulating layer, wherein the gate electrode comprises a metal layer.
The tunnel insulating layer may comprise one or more of silicon oxide, silicon oxynitride, and silicon nitride. The charge storage layer may comprise one or more of silicon nitride, silicon oxynitride, silicon-rich oxide, metallic oxynitride and other metallic oxide materials. The blocking insulating layer may comprise metallic oxide or metallic oxynitride of a group III element or group VB element in the Mendeleef Periodic Table.
According to example embodiments, the blocking insulating layer may comprise doped metal oxide or doped metal oxynitride in which metal oxide is doped with a group IV element in the Mendeleef Periodic Table. The blocking insulating layer may also comprise one of more of HfO2, Al2O3, La2O3, Hf1-XAlXOY, HfXSi1-XO2, Hf—Si-oxynitride, ZrO2, ZrXSi1-XO2, Zr—Si-oxynitride, and combinations thereof.
The metal layer of the gate electrode may have a work-function of, for example, at least 4 eV. The metal layer may be one of titanium, titanium nitride, tantalum nitride, tantalum, tungsten, hafnium, niobium, molybdenum, ruthenium dioxide, molybdenum nitride, iridium, platinum, cobalt, chrome, ruthenium monoxide, titanium aluminide (Ti3Al), Ti2AlN, palladium, tungsten nitride (WNx), tungsten silicide (WSi), nickel silicide, or combinations thereof.
While example embodiments have been particularly shown and described with reference to the example embodiments shown in the drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims.
Number | Date | Country | Kind |
---|---|---|---|
10-2006-0044832 | May 2006 | KR | national |
This application is a continuation-in-part of U.S. patent application Ser. No. 11/657,650, filed Jan. 25, 2007, the content of which is herein incorporated by reference in its entirety.
Number | Date | Country | |
---|---|---|---|
Parent | 11657650 | Jan 2007 | US |
Child | 11798947 | US |