Patent Application
20080023707
In the following, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.
For ease of understanding, the following description will contain various directional terms, such as left, right, upper, lower, forward, rearward and the like. However, such terms are to be understood with respect to only a drawing or drawings on which the corresponding part of element is illustrated.
Hereinafter, a superscript “+” in N+ denotes a relatively high impurity density while a superscript “−” in N− denotes a relatively low impurity density.
In
On a fist main face 100-1 side of the N silicon carbide semiconductor substrate 100, in other words, on the N− silicon carbide epitaxial layer 2 side, there is formed an N− polycrystalline silicon layer 3A made of a second semiconductor material which is an N− polycrystalline silicon. The N− polycrystalline silicon (second semiconductor material) is different from the silicon carbide (first semiconductor material) in band gap. Between the N− silicon carbide epitaxial layer 2 and the N− polycrystalline silicon layer 3A, there is formed a hetero junction HJ.
In addition, on the first main face 100-1 side of the N silicon carbide semiconductor substrate 100, in other words, on the N− silicon carbide epitaxial layer 2 side, there is formed an electric field relaxing area 5 including an impurity introducing area 4 (to which an impurity is introduced) so formed as to contact the hetero junction HJ. On a back face (lower in
In other words, the silicon carbide semiconductor device 20 shown in
Hereinafter described referring to
At first, as shown in
Then, as shown in
Herein, conditions of the above ion implantation include, for example, acceleration voltage of 70 KeV and dose quantity of 1×1014 cm−2. Under the above conditions, the thus implanted phosphor 8 has a range 8R larger than the first thickness 3T1 of the polycrystalline silicon layer 3. Therefore, the phosphor 8 (impurity) is implanted also in the N− silicon carbide epitaxial layer 2 side via the polycrystalline silicon layer 3, to thereby form the impurity introducing area 4, thus forming the electric field relaxing area 5 including i) the hetero junction HJ between the N− silicon carbide epitaxial layer 2 and the polycrystalline silicon layer 3 and ii) the impurity introducing area 4.
Then, as shown in
Then, as shown in
In the method of producing the silicon carbide semiconductor device 20 according to the first embodiment, depositing the polycrystalline silicon layer 3 (made of the second semiconductor material) on the N silicon carbide substrate 100 (made of the first semiconductor material) can form the hetero junction HT. In addition, the ion implantation is used for introducing the impurity (the phosphor 8) in the polycrystalline silicon layer 3, thereby accurately introducing the impurity (the phosphor 8).
Moreover, the polycrystalline silicon layer 3 having the first thickness 3T1 smaller than the range 8R of the phosphor 8 in the impurity introduction can, simultaneously with the impurity introduction in the polycrystalline silicon layer 3 by the ion implantation, introduce the impurity in the N− silicon carbide epitaxial layer 2, to thereby form the impurity introducing area 4, resulting in the forming of the electric field relaxing area 5 in a self-matching manner.
Referring to an energy band structure from a point A to a point B in
A difference between an electron affinity χSiC of the silicon carbide and an electron affinity χPoly of the N− polycrystalline silicon forms an accumulation layer on the N− polycrystalline silicon layer 3A (the anode 7) side of the hetero junction HJ's interface under the thermal equilibrium state, to thereby form a barrierφh50 on the hetero junction HJ's interface.
With this, by grounding the cathode 6 and applying a proper voltage across the N− polycrystalline silicon layer 3A (the anode 7) of the element allows an electron to flow from the cathode 6, via the N+ silicon carbide substrate 1, the N− silicon carbide epitaxial layer 2 and the impurity introducing area 4, to the N− polycrystalline silicon layer 3A (the anode 7), thus featuring a forward current of the diode.
Hereinafter described is a state where the N− polycrystalline silicon layer 3A (the anode 7) of the element is grounded to thereby apply a high voltage to the cathode 6. In other words, hereinafter described is an operation where a reverse voltage is applied.
With the element, in the absence of the electric field relaxing area 5 including the impurity introducing area 4 and the hetero junction HJ, applying the reverse voltage applies a high electric field to the hetero junction HJ's interface, to thereby vary the energy band structure as shown in
In this case, with the thus applied high electric field, a part of the electron 51 accumulated on the N− polycrystalline silicon layer 3A (the anode 7) side of the hetero junction HJ's interface tunnels in the barrier φh50, or goes over the barrier φh50, to thereby move from the N− polycrystalline silicon layer 3A to the N− silicon carbide epitaxial layer 2. Contrary to the above, in the presence of the electric field relaxing area 5, the electric field relaxing area 5 relaxes the electric field which covers the hetero junction HJ's interface, thereby decreasing a reverse leak current from the hetero junction HJ.
In addition, unlike a conventional edge termination area and the like, the silicon carbide semiconductor device 20 according to the first embodiment of the present invention can be formed without a high temperature active annealing, thereby preventing the N− silicon carbide epitaxial layer 2's surface from being deteriorated. In addition, forming the electric field relaxing area 5 in the self-matching manner in the introducing of the impurity in the polycrystalline silicon layer 3 can make the process easier.
In addition, using the silicon carbide for the first semiconductor material can provide the semiconductor device 20 featuring a high reverse blocking voltage.
Moreover, using the polycrystalline silicon for the second semiconductor material (the polycrystalline silicon layer 3) can make the processes easier, including an etching or a conduction controlling in the production of the silicon carbide semiconductor device 20.
The silicon carbide semiconductor device 20 according to the second embodiment of the present invention is substantially the same in structure as the silicon carbide semiconductor device 20 according to the first embodiment, except the following difference: the electric field relaxing area 5 is formed only on an outer periphery 3C of the N− polycrystalline silicon layer 3A (the anode 7), with the outer periphery 3C being so formed as to contact the N− silicon carbide epitaxial layer 2.
Hereinafter described is a method of producing the silicon carbide semiconductor device 20 in
At first, the N silicon carbide semiconductor substrate 100 is prepared which has the N− silicon carbide epitaxial layer 2 formed on the N+ silicon carbide substrate 1. The N− silicon carbide epitaxial layer 2 has density and thickness, for example, 1×1016 cm−3 and 10 μm, respectively.
Then, as shown in
Then, by the photolithography and etching, the outer periphery 3C of the polycrystalline silicon layer 3 has the first thickness 3T1 smaller than the ion range in the ion implantation in the impurity introduction. For example, under the above ion implantation condition, the first thickness 3T1 (of the polycrystalline silicon layer 3) smaller than the ion range is, for example, 1,000 angstrom, in a nutshell, forming an area where the polycrystalline silicon layer 3 has two different thicknesses including the first thickness 3T1 (smaller than the ion range of the ion implantation in the impurity introduction) and the second thickness 3T2 (larger than the ion range of the ion implantation in the impurity introduction).
Then, as shown in
Thereby, the electric field relaxing area 5 is formed which includes: i) the hetero junction HJ between the N− silicon carbide epitaxial layer 2 and the polycrystalline silicon layer 3 and ii) the impurity introducing area 4.
Then, the thus obtained is subjected to a heat treatment in a nitrogen atmosphere at 950° C. for 20 minutes, to thereby activate (annealing) the phosphor 8 implanted in the polycrystalline silicon layer 3. Then, the polycrystalline silicon layer 3 is patterned by the photolithography and etching, to thereby form the N− polycrystalline silicon layer 3A. In this case, the patterning is so implemented that the outer periphery 3C of the N− polycrystalline silicon layer 3A is disposed on the impurity introducing area 4.
Then, Ti (titanium) and Ni (nickel) are sequentially deposited on the back face of the N+ silicon carbide substrate 1 by the spattering method. Then, the thus obtained is subjected to the RTA (Rapid Thermal Anneal) in the nitrogen atmosphere at 1,000° C. for 1 minute, to thereby form the cathode 6, thus completing the silicon carbide semiconductor device 20 shown in
The silicon carbide semiconductor device 20 thus produced according to the second embodiment has the electric field relaxing area 5 disposed on the outer periphery 3C the N− polycrystalline silicon layer 3A (the anode 7) where the electric field is most concentrated when the reverse voltage is applied. Therefore, in addition to the effect brought about according to the first embodiment, the silicon carbide semiconductor device 20 according to the second embodiment has decreased leak current from the outer periphery 3C of the N− polycrystalline silicon layer 3A (the anode 7), compared with the one without the electric field relaxing area 5, resulting in higher reverse blocking voltage.
Moreover, with the electric field relaxing area 5 disposed only on the outer periphery 3C of the N− polycrystalline silicon layer 3A (the anode 7), the silicon carbide semiconductor device 20 according to the second embodiment has a forward current characteristic like the one without the electric field relaxing area 5 and has high reverse blocking voltage, realizing a low ON resistance.
Herein, the silicon carbide semiconductor device 20 according to the second embodiment has the structure where the electric field relaxing area 5 is disposed on the outer periphery 3C of the N− polycrystalline silicon layer 3A (the anode 7). Otherwise, taking any of the following patterning A and patterning B of the polycrystalline silicon layer 3 can selectively form the impurity introducing area 4 on the N− silicon carbide epitaxial layer 2, in combination with the impurity introduction in the polycrystalline silicon layer 3:
Patterning A (
Patterning B (
With this, the electric field relaxing areas 5 are formed at the certain intervals 53 as shown in
In addition, according to the first embodiment and the second embodiment, the N polycrystalline silicon layer 3A serves as the anode 7. Otherwise, the anode 7 made of metal as shown in
According to the first embodiment and the second embodiment of the present invention, the diode is exemplified. Otherwise, the electric field relaxing area 5 under the present invention can be used as the simple edge termination as described above. Therefore, not limited to the diode, the electric field relaxing area 5 under the present invention is applicable to a switching element and the like.
In
On the first main face 100-1 side of the N silicon carbide semiconductor substrate 100, in other words, on the N− silicon carbide epitaxial layer 2 side, there are formed trenches 13 (grooves) at certain intervals 55. In a certain position on a first main face 2-1 side of the N− silicon carbide epitaxial layer 2, there is formed a source area 9 made of N− polycrystalline silicon which is a semiconductor material different from the N silicon carbide semiconductor substrate 100 in band gap, thus forming the hetero junction HJ between the N− silicon carbide epitaxial layer 2 and the source area 9.
Adjacent to the N− silicon carbide epitaxial layer 2 (on a side wall of the trench 13) and the source area 9, a gate electrode 10 is formed via a gate insulating film 14, A source electrode 11 is formed on the source area 9, and a drain electrode 12 is formed on a second main face 100-2 side of the N+ silicon carbide substrate 1. On the outer peripheries of the multiple unit cells and on the N− silicon carbide epitaxial layer 2 side in a certain area between the trenches 13, there is formed the electric field relaxing area 5 including the impurity introducing area 4 so formed as to contact the hetero junction HJ. The gate electrode 10 and the source electrode 11 are electrically insulated by a layer-to-layer insulating film 15.
Hereinafter described referring to
At first, as shown in
Then, as shown in
Then, as shown in
Implementing the ion implantation under the above conditions can implant the boron 30 in a part of the polycrystalline silicon layer 3 and on the N− silicon carbide epitaxial layer 2 side directly below the polycrystalline silicon layer 3, to thereby form the impurity introducing area 4.
Then, as shown in
In the above operation in
Then, as shown in
Then, as shown in
Then, the layer-to-layer insulating film 15 is deposited, as shown in
Hereinafter described is a specific operation of the thus produced silicon carbide semiconductor device 20, according to the third embodiment. The element is used in such a manner that the source electrode 11 is grounded and a positive drain voltage is applied to the drain electrode 12.
In this case, with the gate electrode 10 grounded, the element according to the third embodiment has a characteristic like the reverse characteristic of the silicon carbide semiconductor device 20 in
Then, applying a proper positive voltage to the gate electrode 10 accumulates the electron 51 i) in the source area 9 which is disposed adjacent to the gate insulating film 14 and is made of polycrystalline silicon, and ii) in the N− silicon carbide epitaxial layer 2, resulting in flow of current between the source electrode 11 and the drain electrode 12 with a certain drain voltage D, thus bringing about a conductive state.
Moreover, removing the positive voltage applied to the gate electrode 10 eliminates the accumulation layer of the electron 51 from the source area 9 and the N− silicon carbide epitaxial layer 2 which are disposed adjacent to the gate insulating film 14. With this, the barrier φh50 (refer to
On the outer peripheries of the multiple of the unit cells and on the N− silicon carbide epitaxial layer 2 side in the certain area between the trenches 13 (in which two places the electric field is likely to be concentrated in the applying of the drain voltage), the element has the electric field relaxing area 5 including the impurity introducing area 4 so formed as to contact the hetero junction HJ. The electric field relaxing area 5, can relax the electric field on the outer periphery in the applying of the drain voltage, thus bringing about a high drain reverse blocking voltage.
In addition, in the reverse conduction of the element, the electric field relaxing area 5 serves as a unipolar reflux diode, thus eliminating the need of providing a reflux diode in the switching element, thereby decreasing an area per unit cell. In other words, the ON resistance can be further decreased. In addition, the electric field relaxing area 5 serving as the reflux diode is the unipolar element, thus preventing implantation of minority carriers. Thereby, power loss in the switching operation can be decreased.
According to the third embodiment, the impurity introduced in the impurity introducing area 4 is the boron 30, while the impurity introduced in polycrystalline silicon layer 3 made of the second semiconductor material is the phosphor 8, as shown in
In
In a certain position on the first main face 2-1 side of the N− silicon carbide epitaxial layer 2, there is formed the source area 9 made of the N− polycrystalline silicon which is the semiconductor material different from the N silicon carbide semiconductor substrate 100 in band gap, thus forming the hetero junction HJ between the N− silicon carbide epitaxial layer 2 and the source area 9. In a certain position on a first main face 9-1 side of the source area 9, a source contact area 16 made of N+ polycrystalline silicon is so formed as to contact the source area 9.
Adjacent to the N− silicon carbide epitaxial layer 2 (on the side wall of the trench 13), the source area 9 and the source contact area 16, the gate electrode 10 is formed via the gate insulating film 14. The source electrode II is formed on the source contact area 16, and the drain electrode 12 is formed on the second main face 100-2 side of the N+ silicon carbide substrate 1.
On the outer peripheries of the multiple of the unit cells and on the N− silicon carbide epitaxial layer 2 side in a certain area between the trenches 13, there is formed the electric field relaxing area 5 including the impurity introducing area 4 so formed as to contact the hetero junction HJ. The gate electrode 10 and the source electrode 11 are electrically insulated by the layer-to-layer insulating film 15.
Hereinafter described referring to
At first, as shown in
Then, as shown in
Then, as shown in
In this case, the phosphor 8 is implanted also in the N− silicon carbide epitaxial layer 2 side directly below an area where the polycrystalline silicon layer 3 has the first thickness 3T1 smaller than the range 8R of the phosphor 8, to thereby form the impurity introducing area 4. Thereby, the electric field relaxing area 5 is formed which includes: i) the hetero junction HJ between the N− silicon carbide epitaxial layer 2 and the polycrystalline silicon layer 3 and ii) the impurity introducing area 4. Then, the thus obtained is subjected to a heat treatment in a nitrogen atmosphere at 950° C. for 20 minutes, to thereby activate (annealing) the phosphor 8 implanted in the polycrystalline silicon layer 3, thus forming the N− polycrystalline silicon layer 3A.
Then, as shown in
Then, as shown in
In addition, as shown in
Then, as shown in
The thus produced the silicon carbide semiconductor device 20 according to the fourth embodiment shows a like operation to that of the silicon carbide semiconductor device 20 according to the third embodiment.
Although the present invention has been described above by reference to four embodiments, the present invention is not limited to the four embodiments described above. Modifications and variations of any of the four embodiments described above will occur to those skilled in the art, in light of the above teachings.
The source area 9 according to the fourth embodiment has the accumulated MOSFET including the N− polycrystalline silicon. The source area 9 may, however, have a reversed MOSFET including the N− polycrystalline silicon, in this case, the boron 30 and the like can be used for the ion implantation to the source area 9.
As described above, the longitudinal MOSFET has been exemplified as the switching element, according to the third embodiment and the fourth embodiment. Another switching element having an active area including a source area, a drain area G and a drive area may replace the longitudinal MOSFET.
For example, a lateral switching element including: i) a unipolar device such as MOSFET, JFET and the like, ii) a bipolar device such as IGBT, and iii) an MOSFET having RESURF structure can bring about a like effect.
In addition, the first, second, third and fourth embodiments of the present invention each describe the N type first conduction and the P type second conduction. Alternatively, a P type first conduction and an N type second conduction can also bring about the like effect.
Moreover, the first, second, third and fourth embodiments of the present invention each describe the first semiconductor material as the silicon carbide and the second semiconductor material as the polycrystalline silicon. The present invention, is however, not limited to the above semiconductor materials.
For example, any other semiconductor materials such as a wide gap semiconductor including gallium nitride, diamond, oxidized zinc and the like, or germanium, gallium arsenide, indium nitride and the like can bring about the like effect.
In other words, the second semiconductor material may be any of a single crystal silicon, a polycrystalline silicon, and an amorphous silicon.
This application is based on a prior Japanese Patent Application No. P2005-021465 (filed on Jan. 28, 2005 in Japan). The entire contents of the Japanese Patent Application No. P2005-021465 are incorporated herein by reference, in order to take some protection against translation errors or omitted portions.
The scope of the present invention is defined with reference to the following claims.
