This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-050691, filed Mar. 13, 2014, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor device and a module.
It is difficult to ignore the electric resistance of semiconductor device connections as chips with a low overall electric resistance are developed. For example, when the semiconductor device is electrically connected to a source electrode using a metal plate (for example, a source connector) which covers up the entire chip surface, a lower resistance value is achieved as compared to when the semiconductor device is electrically connected to the source electrode using a wire bonding. However, still further reduction of the electric resistance of the semiconductor device is required.
An embodiment provides a semiconductor device and a module having a reduced a source connector electrical resistance.
According to an embodiment, a semiconductor device includes a first conductive plate having a semiconductor chip mounted thereon, and a second conductive plate that overlaps the semiconductor chip and at least two sides of the first conductive plate. In some embodiments, the semiconductor chip includes a source electrode, a drain electrode, and a gate electrode, and the first conductive plate includes a first terminal electrically connected to the drain electrode and a second terminal electrically connected to the gate electrode; a third terminal on the second conductive plate is provided on the at least two sides and electrically connected to the source electrode.
In general, according to one embodiment, there is provided a semiconductor device including: a semiconductor chip, a first conductive plate and a second conductive plate. The first conductive plate is mounted with the semiconductor chip, and a circumference thereof is configured by at least four sides/edges. The second conductive plate covers the semiconductor chip and at least two sides/edges of the first conductive plate.
Hereinafter, some of the embodiments will be described referring to accompanying drawings. In the drawings, same reference numerals refer to same elements, and a duplicated description thereof is appropriately omitted.
The accompanying drawings are intended to promote description and understanding of the embodiments, respectively, and it should be noted that shapes, sizes, and dimensional ratios in each drawing may be different from those of an actual device. These differences may be appropriately modified in design by those skilled in the art considering a following description and known technologies.
A semiconductor device 1 according to the present embodiment includes a drain frame BP1, a semiconductor chip C, a source connector TP1, and a gate terminal GT. The semiconductor chip C according to the embodiment includes a power Metal Insulator Semiconductor Field Effect Transistor (MISFET), having a source electrode ES, a drain electrode ED (refer to
The semiconductor chip C is mounted on the drain frame BP1, and is connected to the drain frame BP1 using solder or the like.
The drain electrode ED is provided on a back surface side of the semiconductor chip C in this embodiment and is electrically connected to the drain frame BP1.
The gate electrode EG is connected to a gate terminal GT through a wire WR.
A source electrode ES is provided on the upper surface side of the semiconductor chip C, and a source connector TP1 is provided so as to cover the semiconductor chip C while being in contact with the source electrode ES, and thereby the source electrode ES is electrically connected to the source connector TP1. In the first embodiment, the source electrode ES, the drain electrode ED and the gate electrode EG correspond to, for example, a first electrode to a third electrode, respectively.
Both the drain frame BP1 and the source connector TP1 are formed from a conductor, and are formed from, for example, copper (Cu) in the first embodiment. This also applies to the drain frames BP3, BP4, and BP11, and the source connectors TP2 to TP5 to be described below. The drain frame BP1 and the source connector TP1 correspond, respectively, to, for example, the first conductive plate and the second conductive plate in the present embodiment.
The semiconductor chip C has a rectangular planar shape in the first embodiment, and a circumference (perimeter) of the semiconductor chip C is configured to have four edges (sides) S1 to S4.
The source connector TP1 extends horizontally (e.g., parallel to a plane of the semiconductor chip C) after a bent transition (that is, source connector TP1 is bent downwardly at its right and left ends in
One feature of the semiconductor device 1 in the first embodiment is that the source connector TP1 has a rectangular shape whose circumference is configured to have four edges S11 to S14 which each are parallel to four edges S1 to S4 that configure a circumference of the semiconductor chip C, and source terminals ST1 and ST2 are provided at edges S11 and S13, which extend in a Y direction and oppose each other in a X direction.
The drain terminal DT1 is provided at one edge S52 of the drain frame BP1 along an edge S12 which is adjacent to the edges S11 and S13 and extends in the X direction.
As described above, according to the semiconductor device 1 according to the first embodiment, the source connector TP1 is disposed so as to cover the semiconductor chip and two edges S51 and S53 of the drain frame BP1, and furthermore, a plurality of source terminals ST1 and ST2 are provided along at least two edges S11 and S13 among the four edges S11 to S14, so that a source current flows in from both a ST1 side and a ST2 side of the source connector TP1. Accordingly, an electric resistance of the source connector may be reduced.
FIGS . 2 and 3 illustrate an example of a module in which the semiconductor device 1 illustrated in
In addition, the module M1 also includes a resin R which seals (encapsulates) the semiconductor device 1 as illustrated in
According to the module M1 according to the first embodiment, there is provided a module in which the semiconductor device 1 has a reduced electric resistance of the source connector with the mounting to the wiring board 201. This similarly applies when mounting the semiconductor devices according to the second to fifth embodiments, to be described below, on the wiring board 201 or the equivalent.
In the semiconductor device 100 of the reference example, among the four edges S110 to S140 configuring a circumference of the source connector TP100, a source terminal ST100 is provided only on a side of an edge S110.
In general, an electric resistance of a packaged device is mostly the result of an electric resistance of the drain frame and an electric resistance of the source connector. In the semiconductor device 100 of the reference example, a drain current flows in the semiconductor chip C from the drain frame BP100 and is drawn to the source terminal ST100 through the source connector TP100. The drain frame BP100 at this time has a low electric resistance since a distance from the drain terminal DT100 to the semiconductor chip C is short.
However, a path of the source current is from the source electrode ES of the semiconductor chip C to the source terminal ST100 of the source connector TP100. The distance therebetween is longer than a path of the drain current. Therefore, an electric resistance of the source connector TP100 becomes higher than an electric resistance of the drain frame BP100.
Therefore, as in the first embodiment described above, the source terminal may be provided on at least two edges among the four edges which form a circumference of the source connector TP1, and this thereby allows the source current to flow in both the ST1 side and the ST2 side, which lowers the electric resistance of the source connector. Accordingly, the drain terminal is disposed at a position along a remaining edge at which the source terminal is not provided. In a specific example of the first embodiment, the drain terminal DT1 is provided on the edge S52 along the edge S12 of the source connector TP1.
However, the drain terminal DT1 does not need to be disposed only along the edge S52, and may be instead (or also) disposed on an edge S54 side opposed to the edge S52.
By comparison with
With this configuration, according to the semiconductor device 11 according to the modification example, reduction in both of an electric resistance of the source connector TP1 and an electric resistance of the drain frame BP11 is achieved.
By comparison with
As described above, the semiconductor device 2 according to the second embodiment includes the source terminals ST1 to ST3 which are provided on three adjacent edges S11, S14, and S13, respectively, so that the source current flows in three paths. Accordingly, it is possible to further reduce an electric resistance of the source connector TP2.
By comparison with
The source connector TP3 includes a protruding portion 30 which extends outwardly from the edge S12 (confronting the edge S14) to cover an edge S62 of the drain frame BP3, and extends outwardly in a horizontal manner after being bent to a drain frame BP3 side, and a source terminal ST4 is further provided at the protruding portion 30.
The drain frame BP3 has a rectangular shape in which four edges S61 to S64 configure a circumference, and the drain terminals DT3 are provided on the back surface side of the drain frame.
In this manner, the semiconductor device 3 according to the third embodiment includes the source terminals ST1 to ST4 each provided along all of the four adjacent edges S11 to S14, so that the source current flows in four paths. Accordingly, it is possible to further reduce an electric resistance of the source connector TP3.
Moreover, the semiconductor device 3 according to the third embodiment may radiate heat at a high efficiency since the source connector TP3 substantially covers the semiconductor chip C and the drain frame BP3.
The source connector TP4 has an L-shaped planar shape, and the source terminals ST1 and ST3 are provided along two edges S11 and S14 adjacent to each other, respectively.
As described above, according to the semiconductor device 4 according to the fourth embodiment, the source terminals ST1 and ST3 are provided respectively along the two adjacent edges S11 and S14 among the four edges S11 to S14 which configure a circumference of the source connector TP4, so that the source current flows in both the ST1 side and the ST3 side in the source connector TP4. Accordingly, it is possible to reduce an electric resistance of the source connector TP4.
In the fourth embodiment, the drain terminal DT4 is provided on the edge S53 of the drain frame BP4, however, the exemplary embodiment is not limited thereto, and the drain terminal DT4 may be provided on, for example, the edge S52.
A semiconductor device 5 according to the fifth embodiment includes a source connector TP5 which has an L-shape similar to a shape obtained by vertically inverting the source connector TP4 in
According to the semiconductor device 5 according to the fifth embodiment, it is possible to reduce an electric resistance of the source connector TP5 with this configuration.
In the fifth embodiment, the drain terminal DT4 of the drain frame BP4 may be provided on, for example, the edge S54 and/or provided on the edge S53.
According embodiments described above, a source connector includes a source terminal connected to a source electrode provided along at least two edges among a first edge to a fourth edge which configure a circumference of the source connector, and thereby it is possible to reduce the electric resistance of the source connector.
In addition, according at least one embodiment described above, a module mounted with a semiconductor device having reduced electric resistance of the source connector is provided.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
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2014-050691 | Mar 2014 | JP | national |