SEMICONDUCTOR DEVICE COMPOSED OF HIGH VOLTAGE TRANSISTORS

Abstract

A plurality of first transistors formed on a substrate share a gate electrode. Isolation regions isolate the plurality of first transistors from one another. In the region where the plurality of first transistors, an impurity region is formed in such a manner that it includes the source and drain regions of the plurality of first transistors and that the depth of the impurity region is greater than the depth of the source and drain regions. The impurity region sets the threshold voltage of the first transistors.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1A is a plan view showing a plurality of bit line connect transistors according to a first embodiment of the invention, FIG. 1B is a sectional view taken along line 1B-1B of FIG. 1A, FIG. 1C is a sectional view taken along line 1C-1C of FIG. 1A, and FIG. 1D is a sectional view taken along line 1D-1D of FIG. 1A;

FIG. 2 is a circuit diagram of a NAND type EEPROM applied to the first embodiment;

FIG. 3A is a circuit diagram of a NAND cell and FIG. 3B is a plan view of a NAND cell;

FIG. 4A is a sectional view taken along line 4A-4A of FIG. 3B and FIG. 4B is a sectional view taken along line 4B-4B of FIG. 3B;

FIG. 5A is a schematic diagram to help explain a potential when a NAND type EEPROM is erased from and each of FIGS. 5B to 5E shows the relationship between voltages in the bit line connect transistor 12;

FIGS. 6A to 6D show modification 1 of the first embodiment, FIG. 6A is a plan view, FIG. 6B is a sectional view taken along line 6B-6B of FIG. 6A, FIG. 6C is a sectional view taken along line 6C-6C of FIG. 6A, and FIG. 6D is a sectional view taken along line 6D-6D of FIG. 6A;

FIGS. 7A to 7D show modification 2 of the first embodiment, FIG. 7A is a plan view, FIG. 7B is a sectional view taken along line 7B-7B of FIG. 7A, FIG. 7C is a sectional view taken along line 7C-7C of FIG. 7A, and FIG. 7D is a sectional view taken along line 7D-7D of FIG. 7A;

FIG. 8 is a circuit diagram to which a second embodiment of the invention is applied;

FIGS. 9A and 9B are plan views of the second embodiment;

FIG. 10A is a sectional view taken along line 10A-10A of FIG. 9A, FIG. 10B is a sectional view taken along line 10B-10B of FIG. 9A, and FIG. 10C is a sectional view taken along line 10C-10C of FIG. 9A;

FIGS. 11A and 11B are plan views of modification 1 of the second embodiment;

FIG. 12A is a sectional view taken along line 12A-12A of FIG. 11A, FIG. 12B is a sectional view taken along line 12B-12B of FIG. 11A, and FIG. 12C is a sectional view taken along line 12C-12C of FIG. 11A;

FIGS. 13A and 13B are plan views of modification 2 of the second embodiment;

FIG. 14A is a sectional view taken along line 14A-14A of FIG. 13A, FIG. 14B is a sectional view taken along line 14B-14B of FIG. 13A, FIG. 14C is a sectional view taken along line 14C-14C of FIG. 13A, and FIG. 14D is a sectional view taken along line 14D-14D of FIG. 13A;

FIGS. 15A and 15B are plan views of modification 3 the second embodiment; and

FIG. 16A is a sectional view taken along line 16A-16A of FIG. 15A, FIG. 16B is a sectional view taken along line 16B-16B of FIG. 15A, FIG. 16C is a sectional view taken along line 16C-16C of FIG. 15A, and FIG. 16D is a sectional view taken along line 16D-16D of FIG. 15A.

Claims

1. A semiconductor device comprising: a first-conductivity-type semiconductor substrate;a plurality of first transistors formed on the semiconductor substrate, each of which includes a first gate electrode, a second-conductivity-type first diffused layer constituting one of a source region and a drain region, and a second-conductivity-type second diffused layer constituting the other of the source and drain regions, the first gate electrode being shared by said plurality of first transistors;isolation regions which are formed in the semiconductor substrate and isolate said plurality of first transistors from one another; anda first-conductivity-type impurity region which is formed in the region of the semiconductor substrate where said plurality of first transistors are formed in such a manner that the depth of the first-conductivity-type impurity region is greater than the depth of the first and second diffused layers of said plurality of first transistors to set the threshold voltage of the first transistors.

2. The semiconductor device according to claim 1, wherein a voltage higher than the voltage applied to the second diffused layer and the first gate electrode is applied to the first diffused layer.

3. The semiconductor device according to claim 1, further comprising a first field stopper which is formed in the isolation region located below the first gate electrode.

4. The semiconductor device according to claim 1, further comprising a second field stopper which is formed along the first gate electrode in the isolation region located in the vicinity of the first diffused layer of said plurality of first transistors.

5. The semiconductor device according to claim 3, further comprising a plurality of second transistors which are adjacent to one another in the channel length direction of said plurality of first transistors and which share a second gate electrode and further share one of the source and drain regions with the second diffused layer and has a third diffused layer acting as the other of the source and drain regions, the depth of the first-conductivity-type impurity region being greater than the depth of the second and third diffused layers of the second transistor to control the threshold voltage of the second transistors.

6. The semiconductor device according to claim 5, further comprising a third field stopper which is formed in the channel length direction in the isolation region adjacent to the second diffused layer.

7. The semiconductor device according to claim 1, further comprising a fourth field stopper which is formed along the first gate electrode in the isolation region in the vicinity of the third diffused layer.

8. The semiconductor device according to claim 1, wherein each of said plurality of first transistors is a transistor which connects a bit line to a sense amplifier.

9. The semiconductor device according to claim 1, wherein each of said plurality of first transistors is a transistor which connects a bit line to a power supply node.

10. A semiconductor device comprising: a first-conductivity-type semiconductor substrate;a first transistor which is formed on the semiconductor substrate and which includes a first gate electrode, and a second-conductivity-type first diffused layer and a second-conductivity-type second diffused layer that are formed in the semiconductor substrate on both sides of the first gate electrode, a voltage higher than the voltage supplied to the first gate electrode and the second diffused layer being supplied to the first diffused layer;an isolation region which is formed in the semiconductor substrate and isolates the first transistor from another element; anda first-conductivity-type impurity region which is formed in the region of the semiconductor substrate where the first transistor is formed in such a manner that the depth of the first-conductivity-type impurity region is greater than the depth of the first and second diffused layers of the first transistor to set the threshold voltage of the first transistor.

11. The semiconductor device according to claim 10, wherein the first diffused layer is connected to a bit line.

12. The semiconductor device according to claim 10, wherein the first diffused layer is connected to a power supply node.

13. The semiconductor device according to claim 10, further comprising a first field stopper which is formed in the channel width direction of the first transistor in the isolation region located below the first gate electrode.

14. The semiconductor device according to claim 10, further comprising a second field stopper which is formed in the channel width direction of the first transistor in the isolation region located in the vicinity of the first diffused electrode.

15. The semiconductor device according to claim 13, further comprising a second transistor which is adjacent in the channel length direction of the first transistor and which includes a second gate electrode, the second diffused layer shared with the first transistor, and a third diffused layer, wherein the depth of the first-conductivity-type impurity region is made greater than the depths of the second and third diffused layers of the second transistor to set the threshold voltage of the second transistor.

16. The semiconductor device according to claim 15, further comprising a third field stopper which is formed in the channel length direction in the isolation region adjacent to the second diffused layer.

17. The semiconductor device according to claim 10, further comprising a fourth field stopper which is formed in the channel width direction of the first and second transistors in the isolation region in the vicinity of the third diffused layer.

18. The semiconductor device according to claim 10, wherein the first transistor is a transistor which connects a bit line to a sense amplifier.

19. The semiconductor device according to claim 10, wherein the first transistor is a transistor which connects a bit line to a power supply node.

20. The semiconductor device according to claim 15, wherein the first transistor is a transistor which connects a bit line to a sense amplifier and the second transistor connects the first transistor to a power supply node.