Claims
- 1. A semiconductor device comprising:
- a semiconductor substrate having electronic devices formed therein, the substrate having a surface;
- a first patterned metal layer interconnecting the electronic devices;
- a first adhesion promoter overlying a portion of the substrate, wherein the first adhesion promoter comprises a material selected from the group consisting of a metal halide, a metal alkoxide, and vinyltrichlorisilane; and
- a first dielectric layer on the first adhesion promoter, the dielectric layer separating portions of the first patterned metal layer from the substrate, wherein the first dielectric layer comprises a fluorinated polymer.
- 2. The semiconductor device of claim 1 wherein the first dielectric layer comprises a material selected from the group consisting of polytetrafluoroethylene, perfluoroalkoxy resin, and fluorinated ethylene propylene polymer.
- 3. The semiconductor device of claim 1 further comprising a second adhesion promoter over the first dielectric layer, the second adhesion promoter comprising a material selected from the group consisting of a metal halide, a metal alkoxide, and vinyltrichlorisilane.
- 4. The semiconductor device of claim 1 further comprising:
- a second adhesion promoter formed over the first patterned metal layer:
- a second dielectric layer formed over the second adhesion promoter, wherein the second dielectric layer is patterned to expose portions of the first patterned metal layer; and
- a second patterned metal layer formed over the second dielectric layer and electrically coupling to the exposed portions of the first patterned metal layer.
- 5. A semiconductor device comprising:
- a semiconductor substrate;
- an adhesion promoter overlying a portion of the substrate, wherein the adhesion promoter comprises a material selected from the group consisting of a metal halide, a metal alkoxide, and vinyltrichlorisilane; and
- a fluorinated polymer layer on the adhesion promoter.
- 6. The semiconductor device of claim 5 wherein the fluorinated polymer layer has a first portion having particle sizes less than 0.2 microns and a second portion having amorphous particles.
- 7. The semiconductor device of claim 5 wherein the fluorinated polymer layer has particle sizes less than 0.2 microns.
- 8. The semiconductor device of claim 7 further including a conductor overlying the fluorinated polymer layer.
Parent Case Info
This application is a continuation of prior application Ser. No. 07/779,663, filed on Oct. 21, 1991, now abandoned.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
4996584 |
Young et al. |
Feb 1991 |
|
5055342 |
Markovich et al. |
Oct 1991 |
|
Non-Patent Literature Citations (1)
Entry |
"Optimization of a Fine Line Air Bridge Process", Huang et al U.S. Conf. on GaAs Manufacturing Technology, Apr. 1990. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
779663 |
Oct 1991 |
|