Claims
- 1. A method of manufacturing a semiconductor device, comprising the steps of:forming a collector layer of a first conductivity type having a main surface; forming a base layer of a second conductivity type in a prescribed region on the main surface of said collector layer; forming an emitter layer in a prescribed region on the main surface of said base layer; forming a first insulating layer having an opening on said emitter layer at least in a prescribed region on said base layer; forming a semiconductor layer on said first insulating layer; forming a second insulating layer on an upper surface and a side surface of said semiconductor layer; and forming an emitter electrode so as to be electrically connected to said emitter layer within the opening of said first insulating layer, and to extend on and along a surface of said second insulating layer.
- 2. A method of manufacturing a semiconductor device, comprising the steps of:forming a collector layer of a first conductivity type having a main surface; forming a base layer of a second conductivity type in a prescribed region on the main surface of said collector layer; forming an emitter layer in a prescribed region on the main surface of said base layer; forming by thermal oxidation a first insulating layer having an opening on said emitter layer, at least in a prescribed region on said base layer; forming a second insulating layer on said first insulating layer, said second insulating layer having a thickness of at least ten times a thickness of said first insulating layer; wherein said second layer is not formed by thermal oxidation and forming an emitter electrode so as to be electrically connected to said emitter layer within an opening of said first insulating layer, and to extend on and along an upper surface of said second insulating layer.
- 3. A method of manufacturing a semiconductor device, comprising the steps of:forming a collector layer of a first conductivity type having a main surface; forming a base layer of a second conductivity type in a prescribed region on the main surface of said collector layer; forming an emitter layer in a prescribed region on the main surface of said base layer; forming a first insulating layer having an opening on said emitter layer, at least in a prescribed region on said base layer; forming a semiconductor layer on said first insulating layer: forming a second insulating layer on said semiconductor layer; and forming a polycrystalline silicon emitter electrode so as to be electrically connected to said emitter layer within an opening of said first insulating layer, and to extend on and along an upper surface of said second insulating layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
5309362 |
Dec 1993 |
JP |
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Parent Case Info
This application is a Divisional of application Ser. No. 08/581,887 filed Jan. 2, 1996 now U.S. Pat. No. 5,731,617, which is a Continuation of application Ser. No. 08/273,174 filed Jul. 26, 1994.
US Referenced Citations (12)
Foreign Referenced Citations (1)
Number |
Date |
Country |
3-51310 |
Aug 1991 |
JP |
Continuations (1)
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Number |
Date |
Country |
Parent |
08/273174 |
Jul 1994 |
US |
Child |
08/581887 |
|
US |