BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and 1B illustrate cross-sectional views to describe a typical method for fabricating a semiconductor device;
FIG. 2 illustrates a cross-sectional view of a semiconductor device consistent with an embodiment of this invention; and
FIGS. 3A to 3F illustrate cross-sectional views to describe a method for fabricating a semiconductor device consistent with an embodiment of this invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS
A semiconductor device having a contact plug and a method for fabricating the same in accordance with exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, identical or like reference numerals throughout the exemplary embodiments of the present invention represent identical or like elements in different drawings.
FIG. 2 illustrates a semiconductor device consistent with an embodiment of this invention. A patterned first insulation layer 22 including a plurality of contact holes 23 is formed over a substrate 21. Protection layers 24 are formed on both sidewalls of the contact holes 23. The protection layers 24 include a nitride-based layer, e.g., a silicon nitride layer. The contact holes 23 are filled with the landing plugs 25A and 25B, contacting the protection layers 24. The landing plugs 25A and 25B include polysilicon.
A second insulation pattern 26A is formed over the resultant substrate structure. A bit line contact 27 is formed in the second insulation pattern 26A, contacting the individual landing plug 25A. A bit line 28 is formed over the bit line contact 27.
A patterned third insulation layer 29 is formed over the resultant substrate structure. Storage node contact holes 30 are formed in the patterned third insulation layer 29, exposing top surfaces of the other landing plugs 25B. The storage node contact holes 30 are filled with storage node contact plugs 31. The storage node contact plugs 31 include polysilicon.
The patterned first insulation layer 22, the second insulation pattern 26A, and the patterned third insulation layer 29 include a silicon oxide layer. The protection layers 24 formed on the sidewalls of the contact holes 23 isolate the adjacent landing plugs 25A and 25B, functioning as a part of an isolation structure. The isolation structure formed between the adjacent landing plugs 25A and 25B is formed in a triple-layer structure, including a protection layer 24, the patterned first insulation layer 22, and another protection layer 24. Since the protection layers 24 include a silicon nitride layer and the patterned first insulation layer 22 includes a silicon oxide layer, the isolation structure in the triple layer structure includes a silicon nitride layer, a silicon oxide layer, and another silicon nitride layer.
In particular, the protection layers 24 prevent a bridge which may be generated between the landing plug 25A and the storage node contact plug 31 formed adjacent to each other. The landing plug 25A and the storage node contact plug 31 formed adjacent to each other are not supposed to be in contact with each other even when a portion of the first insulation layer 22 is dissolved during the wet etching process performed after forming the storage node contact holes 30. Thus, the protection layers 24 includes a material with a high wet etch selectivity, i.e., a silicon nitride layer, for the wet cleaning process of the patterned first insulation layer 22, the second insulation pattern 26A, and the patterned third insulation layer 29. Reference denotation ‘C’ denotes a portion of the storage node contact plug 31 filling a dissolved portion of the patterned first insulation layer 22.
FIGS. 3A to 3F illustrate cross-sectional views to describe a method for fabricating a semiconductor device consistent with an embodiment of this invention.
Referring to FIG. 3A, predetermined processes are performed onto predetermined regions of a substrate 21. The predetermined processes refer to forming a transistor including an isolation structure, sources, drains, and gate electrodes. A plurality of gate lines (not shown) are formed over the substrate 21. A first insulation layer is formed over the substrate structure. A photolithography process is performed thereon to etch the first insulation layer to form a plurality of contact holes 23 in a patterned first insulation layer 22. The contact holes 23 are formed to connect subsequent landing plugs to portions of the substrate 21. Thus, the patterned first insulation layer 22 functions as a landing plug isolation layer. The patterned first insulation layer 22 includes an oxide-based layer such as a borophosphosilicate glass (BPSG) layer. The patterned first insulation layer 22 may include a silicon oxide layer.
Referring to FIG. 3B, protection layers 24 are formed on both sidewalls of the contact holes 23. The protection layers 24 have an etch rate different to that of the first insulation layer 22 and other subsequent insulation layers to be formed later. In more detail, an insulation layer is formed over the substrate structure. A dry etching process, i.e., an etch-back process, is performed onto the insulation layer in a manner that portions of the insulation layer remain on the sidewalls of the contact holes 23. The protection layers 24 are formed to prevent bridges from occurring between a subsequent storage node contact plug and an adjacent landing plug when a portion of the patterned first insulation layer 22 is dissolved-during a subsequent wet cleaning process. The protection layers 24 include a material insoluble to the wet chemical used during the wet cleaning process. The protection layers 24 may include a nitride-based layer. That is, the protection layers 24 may include a silicon nitride layer having a thickness ranging from approximately 100 Å to approximately 300 Å.
Referring to FIG. 3C, a conductive layer is formed over the resultant substrate structure, filling the contact holes 23. One of an etch-back process and a planarization process is performed thereon to form landing plugs 25A and 25B in the contact holes 23. The conductive layer may include polysilicon. The landing plug 25A refers to a landing plug which is to contact a bit line, and the landing plugs 25B refer to landing plugs which is to contact a storage node. In particular, an isolation structure formed between the adjacent landing plugs 25A and 25B is formed in a triple-layer structure, including a protection layer 24, the patterned first insulation layer 22, and another protection layer 24. Since the protection layers 24 include a silicon nitride layer and the patterned first insulation layer 22 includes a silicon oxide layer, the isolation structure in the triple layer structure includes a silicon nitride layer, a silicon oxide layer, and another silicon nitride layer.
Referring to FIG. 3D, a second insulation layer is formed over the resultant substrate structure. The second insulation layer includes an oxide-based layer such as a BPSG layer. The second insulation layer may include a silicon oxide layer. The second insulation layer is selectively etched to expose a bit line contact region. A conductive layer fills the bit line contact region to form a bit line contact 27 in a patterned second insulation layer 26. The bit line contact 27 is in contact with the landing plug 25A. A bit line 28 is formed over the bit line contact 27.
Referring to FIG. 3E, a third insulation layer is formed over the resultant substrate structure. The third insulation layer includes an oxide-based layer such as a BPSG layer. The third insulation layer may include a silicon oxide layer. A photolithography process is performed thereon to etch portions of the third insulation layer and the patterned second insulation layer 26, thereby forming storage node contact holes 30 and exposing top surfaces of the landing plugs 25B. Reference notation 29 denotes a patterned third insulation layer, and reference notation 26A denotes a second insulation pattern.
In more detail, a hard mask is formed over the third insulation layer. The third insulation layer and patterned second insulation layer 26 are selectively dry etched using the hard mask. A portion of the patterned first insulation layer 22 may be etched during the formation of the storage node contact holes 30 due to an alignment defect.
A wet cleaning process is performed onto the resultant substrate structure to remove by-products of etching. The wet etching process uses a wet chemical. The wet chemical may include a hydrogen fluoride (HF) solution or a buffered oxide etchant (BOE) solution. A portion of the patterned first insulation layer 22 may be dissolved, i.e., etched, during the wet cleaning process as denoted with reference letter ‘D’.
The wet chemical used in the wet cleaning process may etch the portion of the patterned first insulation layer 22, but does not etch the protection layers 24. In more detail, the protection layers 24 include a nitride-based layer which is indissoluble to the HF solution or the BOE solution, and thus, the protection layers 24 are not etched during the wet cleaning process. Consequently, sidewalls of the landing plugs 25A and 25B are protected from being exposed to the wet chemical by the protection layers 24.
Referring to FIG. 3F, the storage node contact holes 30 are filled with a conductive layer. An etch-back process or a planarization process is performed thereon to form storage node contact plugs 31. The conductive layer may include polysilicon. When forming the storage node contact plugs 31, a portion of the storage node contact plugs 31 may fill the dissolved portion of the patterned first insulation layer 22 as denoted with reference denotation ‘C’. However, the protection layers 24 formed on the sidewalls of landing plugs 25A and 25B prevent the storage node contact plugs 31 from bridging with the adjacent landing plug 25A.
Consistent with this embodiment, forming the protection layers, including a nitride-based layer which does not dissolve even when the patterned first insulation layer is dissolved by the wet chemical, on the sidewalls of the contact holes formed in the patterned first insulation layer isolating the adjacent landing plugs prevents generation of bridges between the storage node contact plugs and the adjacent landing plugs even when the patterned first insulation layer is dissolved by the wet chemical due to the misalignment defect. Consequently, device characteristics and yields may be improved.
The present application contains subject matter related to the Korean patent application Nos. KR 2006-0032329 and KR 2006-0121416, filed in the Korean Patent Office on Apr. 10, 2006 and Dec. 4, 2006, respectively, the entire contents of which are herein incorporated by reference.
While the present invention has been described with respect to certain specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Patent Application
20070238280
