This invention relates to semiconductor devices such as Insulated Gate Bipolar Transistors (IGBTs) and more specifically relates to a novel process for the manufacture of non-punch IGBTs formed in float zone (FZ) material in which a lightly doped weak collector permits an increased device switching speed.
IGBTs employing a weak collector are well known. Such devices, using a non-punch through technology, and using ultra-thin float zone wafers rather than more expensive wafers with an epitaxially formed silicon layer for device junctions and buffer zones for example, are described in a paper 0-7803-3106-0/96; 1996 I.E.E.E., entitled NPT-IGBT-Optimizing for Manufacturability, in the names of Darryl Burns et al.
As described in that paper, high voltage non-punch through IGBTs (NPT-IGBTs) offer reasonable on state voltages, high short-circuit ruggedness, and minimal turn-off losses without heavy metal or E-beam lifetime killing. In addition, they have reduced cost as compared to the more conventional epitaxial IGBT because they are fabricated on low-cost bulk (float zone) silicon substrates and do not use thick, expensive epitaxial layers. The final thickness of the float zone wafers for non-punch thru IGBTs ranges from about 80 microns for 600 volt devices to 250 microns for 1700 volt devices. Even thinner wafers are needed for even lower breakdown voltages. Such wafers are fragile and subject to breakage during processing. Typically, the wafer will be about 80 microns thick for a 600 volt breakdown and 185 microns thick for a 1200 volt breakdown.
The known NPT-IGBT uses a simple, shallow low concentration backside P type implant (a “weak” or “transparent” collector) to form an emitter with low efficiency, thereby providing fast turn-off time. A collector contact including a first aluminum layer is then sintered into the bottom of the silicon wafer. In contrast, the conventional epitaxial IGBT uses an N+ epitaxial buffer layer and lifetime killing to obtain fast turn-off time.
The weak collector in an IGBT has been found to improve the relation between forward voltage drop (Vce) and switching speed, as compared to that obtained by E beam radiation or heavy metal implants. Thus, in
In accordance with the present invention, it has been found that the formation of a large number of spaced activated weak collector (or anode) segments over a single die area will produce a device which has characteristics along the dotted line portion of
This characteristic can be obtained, for example, by disposing a screen mask into and perpendicular to the higher dose implant ion beam which forms the weak collector region. Such screens can be formed by a nickel foil having the desired screen pattern. Alternatively, a full area, continuous implant, can be made, which is activated only at spaced locations over the surface by a suitably controlled laser beam heat source.
Referring first to
The invertible channel areas of channel regions 23 and 24 are covered by a gate oxide lattice 30, which, in turn, is covered by a conductive polysilicon gate lattice 31. A low temperature oxide (LTO) 32 then covers the polysilicon gate lattice 31 to insulate it from a continuous aluminum emitter electrode 35. A collector (anode) electrode 36 is then connected to the bottom of the P+ wafer.
The junction pattern shown in
The starting wafer of
In
It should be noted that the FZ wafer will have a greater initial thickness, for example, 400 to 500 microns during the process steps used to form the DMOS top surface of the IGBT, as shown in
After the DMOS topside structure is completed, the bottom surface is ground back to location 52 in
The next step in the manufacture shown in
A conventional thermal backside anneal is carried out in the prior art, after forming the electrode 61. This anneal takes place at 300° C. to 400° C. for 30 to 60 minutes and is used to enhance the interaction of aluminum and the P type implanted silicon layer to create the weak collector of the IGBT.
The use of this conventional backside process has severe constraints. First, the thickness of NPT IGBT wafer is determined by the desired blocking voltage and can range from 80 microns for a 600 volt device to about 250 microns for a 1700 volt blocking voltage. In general, the lower the blocking voltage, the thinner the wafer must be. Wafer breakage can be excessive at these thicknesses so that the number of process steps and type of process equipment used in the “back end” fabrication process must be limited and well controlled.
A second constraint on the fabrication of NPT IGBTs is that the weak collector 60 is formed after the front side metallization and patterning (the DMOS top) are done. Therefore, all subsequent processes are restricted to temperatures well below 570° C. the eutectic temperature of aluminum/silicon.
In accordance with the invention and as shown in
It has been found that when the anodes 100 to 104 are activated, that the resulting device will have a faster switching speed (the dotted line region in
The spaced activated regions 100-104 of
Alternatively, the boron or other impurity can be implanted through openings in a nickel foil or other screen 110 as shown in
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.
This application is a divisional application of U.S. Ser. No. 09/565,973, filed May 5, 2000 and entitled A SEMICONDUCTOR DEVICE HAVING INCREASED SWITCHING SPEED and is related to application (IGBT WITH AMORPHOUS SILICON TRANSPARENT COLLECTOR—Richard Francis), U.S. Ser. No. 09/566,219, filed May 5, 2000; (DIODE WITH WEAK ANODE—Richard Francis, Chiu Ng and Fabrizio Rue Redda), U.S. Pat. No. 6,753,580, issued Jun. 22, 2004; (ANNEAL-FREE PROCESS FOR FORMING WEAK COLLECTOR—Richard Francis and Chiu Ng), U.S. Pat. No. 6,242,288, issued Jun. 5, 2001; and (PLURAL TAPERED HYDROGEN IMPLANTS FOR BUFFER ZONE OF PUNCH-THROUGH NON EPI IGBT—Richard Francis and Chiu Ng), U.S. Ser. No. 6,482,681, issued Nov. 19, 2002.
Number | Name | Date | Kind |
---|---|---|---|
3776770 | Lando | Dec 1973 | A |
RE33209 | Plummer | May 1990 | E |
5105244 | Bauer | Apr 1992 | A |
5141889 | Terry et al. | Aug 1992 | A |
5171696 | Hagino | Dec 1992 | A |
5178370 | Clark et al. | Jan 1993 | A |
5183769 | Rutter et al. | Feb 1993 | A |
5270230 | Sakurai | Dec 1993 | A |
5273917 | Sakurai | Dec 1993 | A |
5286655 | Tsunoda | Feb 1994 | A |
5331184 | Kuwahara | Jul 1994 | A |
5369291 | Swanson | Nov 1994 | A |
5369304 | Lesk et al. | Nov 1994 | A |
5444271 | Kuwahara | Aug 1995 | A |
5485022 | Matsuda | Jan 1996 | A |
5567649 | Lesk et al. | Oct 1996 | A |
5589408 | Robb et al. | Dec 1996 | A |
5608238 | Matsuda | Mar 1997 | A |
5661314 | Merrill et al. | Aug 1997 | A |
5698867 | Bauer et al. | Dec 1997 | A |
5723349 | Fallica | Mar 1998 | A |
5723882 | Okabe et al. | Mar 1998 | A |
5795793 | Kinzer | Aug 1998 | A |
6031254 | Quoirin | Feb 2000 | A |
6043112 | Francis et al. | Mar 2000 | A |
6198115 | Francis et al. | Mar 2001 | B1 |
6239466 | Elasser et al. | May 2001 | B1 |
6242288 | Francis et al. | Jun 2001 | B1 |
6426248 | Francis et al. | Jul 2002 | B2 |
6753580 | Francis et al. | Jun 2004 | B1 |
20020019084 | Francis et al. | Feb 2002 | A1 |
20050280076 | Barthelmess et al. | Dec 2005 | A1 |
Number | Date | Country |
---|---|---|
3-155677 | Jul 1991 | JP |
Number | Date | Country | |
---|---|---|---|
20050227461 A1 | Oct 2005 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 09565973 | May 2000 | US |
Child | 11144727 | US |