Patent Grant
8497548
1. Field of the Invention
The present invention relates to a semiconductor device and a production method therefor, and more particularly to a structure and a production method for an SGT (Surrounding Gate Transistor) which is a vertical MOS transistor comprising a pillar-shaped semiconductor layer having a sidewall serving as a channel region, and a gate electrode formed to surround the channel region.
2. Background Art
With a view to achieving higher integration and higher performance of a semiconductor device, an SGT (Surrounding Gate Transistor) has been proposed which is a vertical transistor comprising a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (see, for example, Patent Document 1: JP 2-188966A). In the SGT, a drain, a gate and a source are arranged in a vertical direction, so that an occupancy area can be significantly reduced as compared with a conventional planar transistor.
a) and 46(b) show an SGT disclosed in the Patent Document 1, wherein
a) to 47(c) show a CMOS inverter using an SGT, wherein
As a prerequisite to enhancing a channel controllability by a gate in an SGT to sufficiently suppress short-channel effects, it is necessary to form a pillar-shaped silicon layer to have a sufficiently-small size relative to a gate length. A size of a pillar-shaped silicon layer can be reduced in a relatively easy manner, for example, by causing dimensional shrinking during dry etching for forming the pillar-shaped silicon layer, or by performing sacrificial oxidation after formation of the pillar-shaped silicon layer. Thus, in many cases, a pillar-shaped silicon layer is formed to have a size less than a minimum fabrication size F, in order to sufficiently suppress the short-channel effects in an SGT.
However, the SGT structure illustrated in
Secondly, in view of a reduction in the number of steps in an SGT production process, it is desirable to simultaneously form two contacts on respective ones of the upper diffusion layer 1615 and a lower diffusion layer 1614. In this case, the contact 1616 to be formed on top of the pillar-shaped silicon layer has to undergo overetching to an extent corresponding to a height dimension of the pillar-shaped silicon layer or more, as compared with the contact to be formed on the lower diffusion layer 1614. In the SGT structure illustrated in
In view of the above circumstances, it is an object of the present invention to, in a vertical transistor, reduce the narrow width effect on a silicide layer on top of a pillar-shaped silicon layer while reducing an interface resistance between the silicide and an upper diffusion layer, to improve transistor characteristics. It is another object of the present invention to achieve a structure free of the occurrence of a short-circuiting between a contact and a gate.
In order to achieve the above objects, according to a first aspect of the present invention, there is provided a MOS transistor which comprises: a pillar-shaped semiconductor layer; one of drain and source regions which is formed underneath the pillar-shaped semiconductor layer to serve as a first drain/source region; a gate electrode formed around a sidewall of the pillar-shaped semiconductor layer through a first dielectric film; an epitaxial semiconductor layer formed on top of an upper surface of the pillar-shaped semiconductor layer; and a remaining one of the drain and source regions which is formed so as to be at least partially in the epitaxial semiconductor layer to serve as a second drain/source region, wherein an area of an upper surface of the second drain/source region is greater than an area of the upper surface of the pillar-shaped semiconductor layer.
Preferably, the MOS transistor of the present invention further comprises a silicide layer formed on the upper surface of the second drain/source region.
More preferably, an interface area between the silicide layer and the second drain/source region is greater than the area of the upper surface of the pillar-shaped semiconductor layer.
Preferably, in the MOS transistor of the present invention, the epitaxial semiconductor layer consists of a silicon (Si) layer or a silicon carbide (SiC) layer formed by epitaxial growth, in cases where it is an n-type epitaxial semiconductor layer, or consists of a silicon (Si) layer or a silicon germanium (SiGe) layer formed by epitaxial growth, in cases where it is a p-type epitaxial semiconductor layer.
Preferably, in the MOS transistor of the present invention, when the number of the pillar-shaped semiconductor layers is at least two, the epitaxial semiconductor layers formed on tops of respective upper surfaces of the at least two pillar-shaped semiconductor layers are connected to each other to form a single common drain/source region.
Preferably, in the MOS transistor of the present invention, the epitaxial semiconductor layer is formed on top of the gate electrode through a second dielectric film.
Preferably, the above MOS transistor further comprises a contact formed on the silicide layer, wherein an area of the contact is less than an area of an upper surface of the silicide layer.
Preferably, the above MOS transistor further comprises at least one contact formed on the epitaxial semiconductor layers on tops of the upper surfaces of the at least two pillar-shaped semiconductor layers, wherein the number of the contacts is less than the number of the pillar-shaped semiconductor layers.
Preferably, the above MOS transistor further comprises at least one contact formed on the connected epitaxial semiconductor layers, wherein the at least one contact includes a contact formed on the connected epitaxial semiconductor layers at a position corresponding to a position between adjacent two of the at least two pillar-shaped semiconductor layers.
Preferably, the above MOS transistor further comprises a plurality of contacts at least one of which is formed on the connected epitaxial semiconductor layers, wherein an area of the at least one contact in cross-section parallel to a principal surface of the substrate is greater than that of each of the remaining contacts.
According to a second aspect of the present invention, there is provided a method of producing a semiconductor device having a MOS transistor. The method comprises the steps of: providing a substrate having a plurality of pillar-shaped semiconductor layers formed thereover; forming one of drain and source regions underneath the pillar-shaped semiconductor layers to serve as a first drain/source region; forming a first dielectric film on a surface of the obtained product; forming a conductive film on the first dielectric film; etching back the first dielectric film and the conductive film to form each of the first dielectric film and the conductive film to have a height dimension equal to a gate length along a sidewall of each of the pillar-shaped semiconductor layers; removing a part of the conductive film and the first dielectric film by selective etching to form a gate electrode around the pillar-shaped semiconductor layers, and a gate line extending from the gate electrode; forming an epitaxial layer on top of an upper surface of at least one of the pillar-shaped semiconductor layers by epitaxial growth, in such a manner that an area of an upper surface of the epitaxial layer becomes greater than that an area of the upper surface of the at least one pillar-shaped semiconductor layer; and forming a remaining one of the drain and source regions in the epitaxial layer and each of the pillar-shaped semiconductor layers to serve as a second drain/source region having a same conductive type as that of the first drain/source region formed on the substrate.
Preferably, the method of the present invention further comprises the step of forming a silicide layer in a surface of the epitaxial layer.
Preferably, in the method of the present invention, the epitaxial semiconductor layer consists of a silicon (Si) layer or a silicon carbide (SiC) layer formed by epitaxial growth, in cases where it is an n-type epitaxial semiconductor layer, or consists of a silicon (Si) layer or a silicon germanium (SiGe) layer formed by epitaxial growth, in cases where it is a p-type epitaxial semiconductor layer.
Preferably, in the method of the present invention, when at least two of the pillar-shaped semiconductor layers are arranged adjacent to each other with a given distance or less therebetween to constitute a MOS transistor, conditions for film formation by epitaxial growth are adjusted in such a manner that only the epitaxial layers formed on tops of respective upper surfaces of the at least two of the pillar-shaped semiconductor layers constituting the MOS transistor are self-alignedly connected together to allow a single common drain/source region to be formed therein.
Preferably, the method of the present invention further comprises, as a pretreatment for the step of forming an epitaxial layer, the step of forming a second dielectric film for isolating between the gate electrode and the epitaxial semiconductor layer.
More preferably, the step of forming a second dielectric film includes the sub-steps of: forming a silicon nitride film or a laminated film comprised of a silicon nitride film and a silicon oxide film, on a surface of the product obtained from the step of removing a part of the conductive film and the first dielectric film; and etching back the silicon nitride film or the laminated film to cover a sidewall of each of the pillar-shaped semiconductor layers, a sidewall of the gate electrode and a sidewall of the gate line by the etched silicon nitride film or laminated film, while allowing the etched silicon nitride film or laminated film to remain on top of the gate electrode, and allowing the first drain/source region and an upper surface of each of the pillar-shaped semiconductor layers to be exposed.
Preferably, in the method of the present invention, the step of providing a substrate having a plurality of pillar-shaped semiconductor layers formed thereover, and the step of forming one of drain and source regions underneath the pillar-shaped semiconductor layers to serve as a first drain/source region, comprise the sub-steps of: forming a plurality of pillar-shaped semiconductor layers on a substrate; forming an element isolation region on the substrate; and forming one of drain and source regions on the substrate to serve as a first drain/source region.
Preferably, in the method of the present invention, the step of providing a substrate having a plurality of pillar-shaped semiconductor layers formed thereover, and the step of forming one of drain and source regions underneath the pillar-shaped semiconductor layers to serve as a first drain/source region, comprise the sub-steps of: forming a planar semiconductor layer, on a dielectric film on a substrate, and then forming a plurality of pillar-shaped semiconductor layers on the planar semiconductor layer substrate; isolating the planar semiconductor layer on an element-by-element basis; and forming one of drain and source regions in the isolated planar semiconductor layer to serve as a first drain/source region.
In the present invention, the term “over a substrate” means a position on the substrate or a position located upwardly of the substrate through a certain layer formed on the substrate.
In a vertical transistor, the present invention makes it possible to reduce the narrow width effect on a silicide layer on top of a pillar-shaped silicon layer while reducing an interface resistance between the silicide and an upper diffusion layer, to improve transistor characteristics. The present invention also makes it possible to achieve a structure free of the occurrence of a short-circuiting between a contact and a gate.
a) and 1(b) are, respectively, a top plan view and a sectional view showing a transistor according to a first embodiment of the present invention.
a) and 2(b) are, respectively, a top plan view and a sectional view showing one example of modification of the transistor according to the first embodiment.
a) and 3(b) are, respectively, a top plan view and a sectional view showing another example of modification of the transistor according to the first embodiment.
a) and 4(b) are, respectively, a top plan view and a sectional view showing yet another example of modification of the transistor according to the first embodiment.
a) and 5(b) are, respectively, a top plan view and a sectional view showing still another example of modification of the transistor according to the first embodiment.
a) and 6(b) are process diagrams showing one example of a production method for the transistor illustrated in
a) and 7(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 8(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 9(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 10(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 11(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 12(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 13(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 14(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 15(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 16(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 17(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 18(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 19(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 20(b) are process diagrams showing the example of the production method for the transistor illustrated in
a) and 21(b) are, respectively, a top plan view and a sectional view showing a transistor according to a second embodiment of the present invention.
a) and 22(b) are, respectively, a top plan view and a sectional view showing one example of modification of the transistor according to the second embodiment.
a) and 23(b) are, respectively, a top plan view and a sectional view showing a CMOS inverter according to a third embodiment of the present invention.
a) and 24(b) are, respectively, a top plan view and a sectional view showing one example of modification of the CMOS inverter according to the third embodiment.
a) and 25(b) are, respectively, a top plan view and a sectional view showing a transistor formed on an SOI substrate (SOI transistor), according to a fourth embodiment of the present invention.
a) and 26(b) are, respectively, a top plan view and a sectional view showing one example of modification of the SOI transistor according to the fourth embodiment.
a) and 27(b) are process diagrams showing one example of a production method for the SOI transistor illustrated in
a) and 28(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 29(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 30(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 31(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 32(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 33(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 34(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 35(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 36(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 37(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 38(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 39(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 40(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 41(b) are process diagrams showing the example of the production method for the SOI transistor illustrated in
a) and 42(b) are, respectively, a top plan view and a sectional view showing an SOI transistor according to a fifth embodiment of the present invention.
a) and 43(b) are, respectively, a top plan view and a sectional view showing a CMOS inverter formed on an SOI substrate (SOI CMOS inverter), according to a sixth embodiment of the present invention.
a) and 44(b) are, respectively, a top plan view and a sectional view showing a transistor according to a seventh embodiment of the present invention.
a) and 45(b) are, respectively, a top plan view and a sectional view showing a transistor according to an eighth embodiment of the present invention.
a) and 46(b) are, respectively, a bird's-eye view and a sectional view showing a conventional SGT.
a), 47(b) and 47(c) are, respectively, an equivalent circuit diagram, a top plan view and a sectional view showing a conventional SGT-based inverter.
a) is a top plan view showing a transistor according to a first embodiment of the present invention, and
A silicon substrate 101 is isolated on an element-by-element basis by an element isolation region 102, and two pillar-shaped silicon layers (pillar-shaped semiconductor layers) 105a, 105b are formed on the silicon substrate. A gate dielectric film (first dielectric film) 107 and a gate electrode (108a, 108b) are formed around each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers). In the first embodiment, a High-k film is used as the gate dielectric film (first dielectric film), and a metal film is used as the gate electrode. Alternatively, a silicon oxynitride film formed by oxidation may be used as the gate dielectric film (first dielectric film), and a polysilicon film may be used as the gate electrode. A lower N+ diffusion layer (first drain/source diffusion region, i.e., one of drain and source diffusion regions) 103 is formed underneath the pillar-shaped silicon layers (pillar-shaped semiconductor layers), and a lower silicide layer 111a is formed on a surface of the lower N+ diffusion layer (first drain/source diffusion region) 103, to reduce a parasitic resistance. An upper N+ diffusion layer (second drain/source diffusion region, i.e., a remaining one of the drain and source diffusion regions) (109a, 109b) is formed on top of each of the pillar-shaped silicon layers (pillar-shaped semiconductor layers), in such a manner that an area of an upper surface thereof becomes greater than that of an upper surface of the pillar-shaped silicon layer. In the first embodiment, the upper N+ diffusion layer (second drain/source diffusion region) (109a, 109b) having an upper surface with an area greater than that of the upper surface of the pillar-shaped silicon layer is comprised of an upper portion formed in an epitaxially-grown semiconductor epitaxial layer, and a lower portion formed in an upper portion of the pillar-shaped silicon layer. Alternatively, the upper N+ diffusion layer (second drain/source diffusion region) (109a, 109b) may be formed only in a part or an entirety of the semiconductor epitaxial layer. The semiconductor epitaxial layer is electrically isolated from the gate electrode (108a, 108b) by a second dielectric film 112, such as a silicon nitride film or a laminated film comprised of a silicon nitride film and a silicon oxide film, interposed therebetween. An upper silicide layer (111b, 111c) is formed on the upper diffusion layer (second drain/source diffusion region) (109a, 109b). The upper silicide layer is formed on the epitaxial silicon layer (semiconductor epitaxial layer) having a diameter greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). Thus, the narrow width effect on the upper silicide layer can be reduced. In addition, an interface area between the upper silicide layer and the upper N+ diffusion layer can be set largely, so that an interface resistance between the upper silicide layer and the upper N+ diffusion layer can be reduced. Further, the upper silicide layer (111b, 111c) may be formed on an upper surface of the upper N+ diffusion layer (second drain/source diffusion region) to have a diameter greater than that of a contact (115, 116) to be formed on an upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). This makes it possible to prevent a short-circuiting between the contact and the gate electrode even if the contact undergoes overetching during etching for contacts. The contact (115, 116) formed on the upper side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) is connected to one of drain and source terminals through an interconnection layer 120. A contact 118 formed on a lower side of the pillar-shaped silicon layer (pillar-shaped semiconductor layer) is connected to a remaining one of the drain and source terminals through an interconnection layer 122, and a contact 117 formed on a gate line 108 extending from the gate electrode is connected to a gate terminal through an interconnection layer 121.
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The first embodiment shows one example where an epitaxial silicon layer (semiconductor epitaxial layer) is formed. Specifically, an epitaxial silicon carbide (SiC) layer may be formed for an NMOS transistor, and an epitaxial silicon germanium (SiGe) layer may be formed for a PMOS transistor. In this case, a stress can be applied to a channel region to enhance carrier mobility.
A second embodiment shows one example where the present invention is applied to a transistor formed by connecting in series two transistors.
Two upper silicide layers 611b, 611c are formed, respectively, on the integral set of upper N+ diffusion layers (second drain/source diffusion regions) 609a, 609b and the integral set of upper N+ diffusion layers (second drain/source diffusion regions) 609c, 609d. Each of the upper silicide layers is formed on the connected epitaxial silicon layers (semiconductor epitaxial layers) each having a diameter greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). Thus, the narrow width effect on the upper silicide layer can be reduced. In addition, an interface area between the upper silicide layer and the integral set of upper N+ diffusion layers (609a, 609b; 609c, 609d) can be set largely, so that an interface resistance between the upper silicide layer and the integral set of upper N+ diffusion layers can be reduced. Further, the upper silicide layer (611b, 611c) may be formed in an upper surface of the integral set of the upper N+ diffusion layers (second drain/source diffusion regions) to have a diameter greater than a total diameter of two contacts (615a, 615b; 616a, 616b) to be formed on an upper side of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This makes it possible to prevent a short-circuiting between the contact and the gate electrode even if the contact undergoes overetching during etching for contacts. The two contacts 615a, 615b formed on the upper side of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) constituting the first transistor are connected to one of drain and source terminals through an interconnection layer 620a, and the two contacts 616a, 616b formed on the upper side of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) constituting the second transistor are connected to a remaining one of the drain and source terminals through an interconnection layer 620b. Further, the first transistor and the second transistor are connected in series through the lower N+ diffusion layer (first drain/source diffusion region) 603. A contact 617 formed on a gate line 608 extending from the gate electrode is connected to a gate terminal through an interconnection layer 621.
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A third embodiment shows one example where the present invention is applied to a CMOS inverter.
With reference to
Two upper silicide layers 811c, 811d are formed, respectively, on the integral set of upper N+ diffusion layers 809a and the integral set of upper P+ diffusion layers (second drain/source diffusion regions) 809b. Each of the upper silicide layers is formed on the connected epitaxial silicon layers (semiconductor epitaxial layers) each having a diameter greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). Thus, the narrow width effect on the upper silicide layer can be reduced. In addition, an interface area between the upper silicide layer and the integral set of upper diffusion layers (809a, 809b) can be set largely, so that an interface resistance between the upper silicide layer and the integral set of upper diffusion layers can be reduced. Further, the upper silicide layer (811c, 811d) may be formed in an upper surface of the integral set of the upper diffusion layers (second drain/source diffusion regions) to have a diameter greater than a total diameter of a plurality of contacts (815, 816) to be formed on an upper side of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This makes it possible to prevent a short-circuiting between the contact and the gate electrode even if the contact undergoes overetching during etching for contacts. As shown in
Further, for example, in an NMOS transistor illustrated in
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a) is a top plan view showing a transistor using an SOI substrate according to a fourth embodiment of the present invention, and
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Further, in the fourth embodiment using an SOI substrate, as to a contact for a plurality of pillar-shaped semiconductor layers, an upper side of the pillar-shaped semiconductor layers may be connected to an interconnection layer via a less number of contacts than the number of the pillar-shaped semiconductor layers, as described in connection with
Further, a contact may be formed on an integral set of upper N+ diffusion layers (second drain/source diffusion regions) at a position corresponding to a position between adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers), as described in connection with
Further, a contact having an area greater than that of other contact in cross-section parallel to a principal surface of a substrate may be formed on an upper side of a plurality of pillar-shaped silicon layers (pillar-shaped semiconductor layers), in a number less than the number of the pillar-shaped semiconductor layers, as described in connection with
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The fourth embodiment shows one example where an epitaxial silicon layer (semiconductor epitaxial layer) is formed. Specifically, an epitaxial silicon carbide (SiC) layer may be formed for an NMOS transistor, and an epitaxial silicon germanium (SiGe) layer may be formed for a PMOS transistor. In this case, a stress can be applied to a channel region to enhance carrier mobility.
A fifth embodiment shows one example where the present invention is applied to a set of transistors formed by connecting in series two transistors.
Two upper silicide layers 1211b, 1211c are formed, respectively, on the integral set of upper N+ diffusion layers (second drain/source diffusion regions) 1209a, 1209b and the integral set of upper N+ diffusion layers (second drain/source diffusion regions) 1209c, 1209d. Each of the upper silicide layers is formed on the connected epitaxial silicon layers (semiconductor epitaxial layers) each having a diameter greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). Thus, the narrow width effect on the upper silicide layer can be reduced. In addition, an interface area between the upper silicide layer and the integral set of upper N+ diffusion layers (1209a to 1209d) can be set largely, so that an interface resistance between the upper silicide layer and the integral set of upper N+ diffusion layers can be reduced. Further, the upper silicide layer (1211b, 1211c) may be formed in an upper surface of the integral set of the upper N+ diffusion layers (second drain/source diffusion regions) to have a diameter greater than a total diameter of two contacts (1215a, 1215b; 1216a, 1216b) to be formed on an upper side of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This makes it possible to prevent a short-circuiting between the contact and the gate electrode even if the contact undergoes overetching during etching for contacts. The two contacts 1215a, 1215b formed on the upper side of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) constituting the first transistor are connected to one of drain and source terminals through an interconnection layer 1220a, and the two contacts 1216a, 1216b formed on the upper side of the pillar-shaped silicon layers (pillar-shaped semiconductor layers) constituting the second transistor are connected to a remaining one of the drain and source terminals through an interconnection layer 1220b. Further, the first transistor and the second transistor are connected in series through the lower N+ diffusion layer (first drain/source diffusion region) 1203. A contact 1217 formed on a gate line 1208 extending from the gate electrode is connected to a gate terminal through an interconnection layer 1221.
In the fifth embodiment using an SOI substrate, as to a contact for a plurality of pillar-shaped semiconductor layers, an upper side of the pillar-shaped semiconductor layers may be connected to an interconnection layer via a less number of contacts than the number of the pillar-shaped semiconductor layers, as described in connection with
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Further, in the same manner as that in
A sixth embodiment shows one example where the present invention is applied to a CMOS inverter using an SOI substrate.
With reference to
Two upper silicide layers 1311c, 1311d are formed, respectively, on the integral set of upper N+ diffusion layers 1309a and the integral set of upper P+ diffusion layers (second drain/source diffusion regions) 1309b. Each of the upper silicide layers is formed on the connected epitaxial silicon layers (semiconductor epitaxial layers) each having a diameter greater than that of the pillar-shaped silicon layer (pillar-shaped semiconductor layer). Thus, the narrow width effect on the upper silicide layer can be reduced. In addition, an interface area between the upper silicide layer and the integral set of upper diffusion layers (1309a, 1309b) can be set largely, so that an interface resistance between the upper silicide layer and the integral set of upper diffusion layers can be reduced. Further, the upper silicide layer (1311c, 1311d) may be formed in an upper surface of the integral set of the upper diffusion layers (second drain/source diffusion regions) to have a diameter greater than a total diameter of a plurality of contacts (1315, 1316) to be formed on an upper side of the adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers). This makes it possible to prevent a short-circuiting between the contact and the gate electrode even if the contact undergoes overetching during etching for contacts.
In the sixth embodiment using an SOI substrate, as to a contact for a plurality of pillar-shaped semiconductor layers, an upper side of the pillar-shaped semiconductor layers may be connected to an interconnection layer via a less number of contacts than the number of the pillar-shaped semiconductor layers, as described in connection with
Further, a contact may be formed on an integral set of upper N+ diffusion layers (second drain/source diffusion regions) at a position corresponding to a position between adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers), as described in connection with
Further, in the same manner as that in
a) is a top plan view showing a transistor using a polysilicon layer as a gate electrode, according to a seventh embodiment of the present invention, and
In the seventh embodiment using a polysilicon film as a gate electrode, as to a contact for a plurality of pillar-shaped semiconductor layers, an upper side of the pillar-shaped semiconductor layers may be connected to an interconnection layer via a less number of contacts than the number of the pillar-shaped semiconductor layers, as described in connection with
Further, a contact may be formed on an integral set of upper N+ diffusion layers (second drain/source diffusion regions) at a position corresponding to a position between adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers), as described in connection with
Further, a contact having an area greater than that of other contact in cross-section parallel to a principal surface of a substrate may be formed on an upper side of a plurality of pillar-shaped silicon layers (pillar-shaped semiconductor layers), in a number less than the number of the pillar-shaped semiconductor layers, as described in connection with
a) is a top plan view showing a transistor having a gate electrode formed of a fully-silicided polysilicon layer, according to an eighth embodiment of the present invention, and
In the eighth embodiment using a fully-silicided polysilicon film as a gate electrode, as to a contact for a plurality of pillar-shaped semiconductor layers, an upper side of the pillar-shaped semiconductor layers may be connected to an interconnection layer via a less number of contacts than the number of the pillar-shaped semiconductor layers, as described in connection with
Further, a contact may be formed on an integral set of upper N+ diffusion layers (second drain/source diffusion regions) at a position corresponding to a position between adjacent pillar-shaped silicon layers (pillar-shaped semiconductor layers), as described in connection with
Further, a contact having an area greater than that of other contact in cross-section parallel to a principal surface of a substrate may be formed on an upper side of a plurality of pillar-shaped silicon layers (pillar-shaped semiconductor layers), in a number less than the number of the pillar-shaped semiconductor layers, as described in connection with
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-109126 | Apr 2009 | JP | national |
Pursuant to 35 U.S.C. §119(e), this application claims the benefit of the filing date of Provisional U.S. Patent Application Ser. No. 61/217,896 filed on Jun. 4, 2009. This application also claims priority under 35 U.S.C. §119(a) to JP2009-109126 filed on Apr. 28, 2009. The entire contents of these applications are hereby incorporated by reference.
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