Patent Application
20230411340
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are now widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, cellular telephones and solid-state drives (SSDs).
While many varied packaging configurations are known, flash memory storage cards may be assembled as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of dies are mounted and interconnected on a small footprint substrate. The substrate may include a rigid, dielectric base having a conductive layer etched on one or both sides. Electrical connections are formed between the dies and the conductive layer(s), and the conductive layer(s) provide an electric lead structure for connection of the dies to a host device. Once electrical connections between the dies and substrate are made, the assembly is then typically encased in a molding compound which provides a protective package.
In order to most increase memory capacity yet stay within the package footprint, it is known to stack semiconductor dies on top of each other on a surface of the substrate, with an offset and/or overlapping each other while separated by a spacer or wire embedded film. However, there still is a need to increase storage capacity without increasing the overall size of a memory device.
The present technology will now be described with reference to the figures which in embodiments relate to a semiconductor device including memory dies mounted on a top surface of the substrate and within a cavity formed in the substrate. It is understood that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the invention to those skilled in the art. Indeed, the invention is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be clear to those of ordinary skill in the art that the present invention may be practiced without such specific details.
The terms “top” and “bottom,” “upper” and “lower” and “vertical” and “horizontal,” and forms thereof, as may be used herein are by way of example and illustrative purposes only, and are not meant to limit the description of the technology inasmuch as the referenced item can be exchanged in position and orientation. Also, as used herein, the terms “substantially” and/or “about” mean that the specified dimension or parameter may be varied within an acceptable manufacturing tolerance for a given application. In one embodiment, the acceptable manufacturing tolerance is ±0.15 mm, or alternatively, ±2.5% of a given dimension.
For purposes of this disclosure, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when a first element is referred to as being connected, affixed, mounted or coupled to a second element, the first and second elements may be directly connected, affixed, mounted or coupled to each other or indirectly connected, affixed, mounted or coupled to each other. When a first element is referred to as being directly connected, affixed, mounted or coupled to a second element, then there are no intervening elements between the first and second elements (other than possibly an adhesive or melted metal used to connect, affix, mount or couple the first and second elements).
An embodiment of the present technology will now be explained with reference to the flowcharts of
In step 200, the substrate 100 is formed. Substrate 100 is a signal-carrier medium provided for transferring electrical signals between semiconductor dies mounted on and in the substrate and a host device, as explained below. In one embodiment of the present technology, the substrate 100 may be a printed circuit board (PCB), including those having edge connectors for connecting to a host device such as a motherboard. In further embodiments, the substrate 100 may be a PCB having solder balls for soldering the substrate 100 to a host device such as a motherboard or other PCB. It is understood that the substrate 100 may be formed of other signal-carrier mediums such as flex tapes, interposers or combinations thereof in further embodiments.
Further detail of the formation of substrate 100 will now be described with reference to the flowchart of
In one embodiment, the substrate 100 may initially be formed by laminating conductive layers onto a dielectric layer in step 230, and then forming a conductance pattern in the conductive layers on one or both sides of the dielectric layer in step 232.
In step 234, if substrate 100 includes more dielectric and conductive layers, steps 230 and 232 are repeated. As shown in the perspective view of
The assembly order of the different layers of substrate 100 described above is by way of example only, and may vary in further embodiments. For example,
Once all layers have been added to the substrate 100, a cavity 116 may be formed in step 236 in a bottom surface of the substrate 100.
The cavity 116 may be formed by any of a wide variety of methods, including with a controlled depth routing process or through a controlled depth laser process. Alternatively or additionally, the conductance pattern in layer 108 may be exposed in cavity 116 using photolithographic and/or etching processes, including for example a plasma etch cleaning of the contact pads 114 in layer 108 after formation of the cavity 116.
In step 238, the substrate 100 may be drilled to define through-hole vias 118 in the substrate 100 which allow signal transmission between the different conductive layers 106, 108, 110 of the substrate 100. The vias 118 (only some of which are numbered in the figures) shown are by way of example, and the substrate may include many more vias 118 than is shown in the figures, and they may be in different locations than is shown in the figures. The vias 118 may alternatively be formed earlier in the process, for example before the conductive and dielectric layers are affixed to each other and/or before the cavity 116 is formed.
In embodiments, the finished substrate 100 may have a length of 30.0 mm, a width of 22.0 mm and a depth of 0.8 mm. In such embodiments, the cavity may have a length (corresponding to the length dimension of the substrate) of 17.6 mm, a width (corresponding to the width dimension of the substrate) of 12.4 mm and a depth of 0.47 mm. It is understood that the dimensions of both the substrate 100 and the cavity 116 may vary in further embodiments, proportionally or disproportionally to each other. For example, the depth of the cavity 116 is disclosed as being slightly more than half of the overall thickness of the substrate 100. In further embodiments, the depth of the cavity 116 may in general be 30% to 90% of the overall thickness of the substrate 100, and more particularly 50% to 75% of the overall thickness of the substrate 100. The depth of the cavity 116 may be outside of these ranges in further embodiments.
A solder mask may be applied to the substrate in step 240, leaving the contact pads 114 exposed through openings in the solder mask. After the solder mask is applied, the contact pads 114 and any other solder areas on the conductance patterns may be plated with Ni/Au, immersion gold or the like in step 244 in a known electroplating or thin film deposition process. The substrate 100 may then be inspected and operationally tested in step 248. These inspections may for example include an automatic optical inspection (AOI), an automated visual inspection (AVI) and/or a final visual inspection (FVI) to check for defects, contamination, scratches and discoloration. One or more of these steps may be omitted or performed in a different order in further embodiments.
The order of the steps set forth in the flowchart of
Referring again to
In the illustrated embodiment, there are two stacks of memory dies 126, each stack including eight dies 126. There may be a single stack of dies in further embodiments. The memory dies 126 may be stacked atop each other stepped offset configuration. The number of dies 126 shown in each stack is by way of example only, and embodiments may include different numbers of semiconductor dies in cavity 116, including for example 1, 2, 4, 8, 16, 32 or 64 dies. There may be other numbers of dies in further embodiments, with the understanding that the dies fit within the cavity 116 (not protrude beyond surface 122). The dies may be affixed to the substrate and/or each other in cavity 116 using a die attach film. As one example, the die attach film may be cured to a B-stage to preliminarily affix the dies 126 in the stack, and subsequently cured to a final C-stage to permanently affix the dies 126 to the substrate 100.
In step 206, the pads 114 within cavity 116 may be cleaned in a plasma etch process. In step 208, the memory dies 126 in cavity 116 may be electrically interconnected to each other and to the contact pads 114 with bond wires 128 as shown in
In step 212, a sealing compound 132 may fill the cavity 116 around the memory dies 126 and bond wires 128 as shown in the cross-sectional side view of
With the bottom surface 122 supported on a chuck or other work surface, passive and/or electronic components 134 may next be affixed to the top surface 120 of substrate 100 in a step 214 and as shown in the perspective view of
In step 216, one or more semiconductor dies 138 may be mounted on the top surface 120 of the substrate 100 as shown in the perspective view of
Where multiple semiconductor dies 138 are included, the semiconductor dies 138 may be stacked atop each other in an offset stepped configuration to form a die stack as shown in
The dies may be affixed to the substrate and/or each other using a die attach film. As noted above with respect to dies 126, the die attach film may be cured to a B-stage to preliminarily affix the dies 138 in the stack, and subsequently cured to a final C-stage to permanently affix the dies 138 to the substrate 100. This final curing process for dies 138 may be the same final curing process as for dies 126 or it may be different.
In step 220, the bond pads 114 on the top surface 120 may be cleaned in a plasma etch. Next in step 224, the memory dies 138 on top surface 120 may be electrically interconnected to each other and to the contact pads 114 on the top surface 120 with bond wires 140 as shown in
In one example where substrate 100 is used as an edge connector PCB to mount directly to a host device such as a motherboard, the semiconductor device 150 shown in
In a further embodiment shown in
In the embodiment described above and shown for example in
In a further embodiment, the molding compound 146 may cover the components on the top side of the substrate, and the contact pads 114 on the bottom surface 122 are left exposed. Such contact pads 114 may be configured as contact fingers so that the semiconductor device 150 is used as a land grid array (LGA) package or memory card. In such an embodiment, the semiconductor device 150 may be removably inserted into a slot of a host device so that the contact pads/fingers 114 on the bottom surface 122 mate with pins in the host device slot to enable the exchange of data between the host device and dies 126 and/or dies 138.
In the embodiments described above, the controller die 144 is mounted to the top surface 120. However, in an alternative embodiment, the controller die 144 may be mounted within the cavity 116. Examples of such embodiments are shown in
The semiconductor device 150 including memory dies 126 in cavity 116 provides increased storage capacity (e.g., twice as much) as conventional semiconductor packages of the same footprint and size. In one example, the semiconductor device may have a storage capacity of 4 Terabytes. Semiconductor dies are currently fabricated as thin as 31 microns, and will get thinner with further technological innovations. Thus, large numbers of such dies may be stacked within the cavity 116, as well as on the top surface of the substrate, to further improve the storage capacity of device 150. Moreover, in further embodiments, the depth of the cavity 116 may be increased without increasing the overall thickness of the substrate to allow even more memory dies 126 to be stacked within the cavity 116.
In the embodiments described above, the semiconductor dies 126 in cavity 116, and the semiconductor dies 138 on the surface 120 are memory dies. However, it is understood that the semiconductor dies within the cavity 116 and/or the semiconductor dies on surface 120 may be other types of semiconductor dies in further embodiments.
In summary, in one example, the present technology relates to a semiconductor device, comprising: a signal carrier medium including first and second opposed surfaces; a first group of contact pads on the first surface of the signal carrier medium; a cavity formed in the second surface of the signal carrier medium; a second group of contact pads within the cavity; a first group of one or more semiconductor dies mounted on the first surface of the signal carrier medium and electrically coupled to the first group of contact pads on the first surface of the signal carrier medium; and a second group of one or more semiconductor dies mounted in the cavity and electrically coupled to the second group of contact pads within the cavity.
In another example, the present technology relates to a semiconductor device, comprising: a signal carrier medium including first and second opposed surfaces; a first conductive layer on the first surface comprising a first set of traces and contact pads; a second conductive layer between the first and second surfaces comprising a second set of traces and contact pads; a third conductive layer on the second surface comprising a third set of traces and contact pads; a cavity formed in the second surface of the signal carrier medium to a depth exposing the second conductive layer; a first plurality of memory dies mounted on the first surface of the signal carrier medium and physically coupled to the contact pads of the first set of traces and contact pads; and a second plurality of memory dies mounted in the cavity and physically coupled to the contact pads of the second set of traces and contact pads.
In a further example, the present technology relates to a semiconductor device, comprising: a signal carrier means including first and second opposed surfaces; a first conductive layer on the first surface comprising a first set of traces and contact pads; a second conductive layer between the first and second surfaces comprising a second set of traces and contact pads; a third conductive layer on the second surface comprising a third set of traces and contact pads; means for exposing the contact pads of the second set of traces and contact pads to enable wire bonding to the contact pads of the second set of traces and contact pads; a first plurality of memory dies mounted on the first surface of the signal carrier medium and wire bonded to the contact pads of the first set of traces and contact pads; and a second plurality of memory dies mounted in the cavity and wire bonded to the contact pads of the second set of traces and contact pads.
The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.
