Patent Application
20070218663
The invention is directed in general to a semiconductor device, and more specifically, to a semiconductor device incorporating fluorine into the gate dielectric.
Low frequency, or 1/f noise has been a concern in the implementation of high performance analog transistor technology. It is generally accepted that 1/f noise is caused by carriers, such as electrons or holes, being transiently trapped in the gate dielectric or trapped in the interface between the gate dielectric and the channel of a transistor. The random translocation of carriers into traps or defect centers, such as silicon dangling bonds, into the gate dielectric and back into the channel, causes the current through the transistor to fluctuate, which manifests as 1/f noise.
The push toward smaller and faster semiconductor devices has increased the need to reduce 1/f noise. As an example, it is well known that the output noise spectrum (Sids) of 1/f noise from a transistor device increases as an inverse second order function of decreasing effective channel length (i.e., Sids1/Leff2). The increase in 1/f as device area is decreased has especially deleterious consequences for analog-to-digital converter and amplifier applications.
The effect of 1/f noise can be partially mitigated by using transistors having large device areas in the initial stages, so that 1/f noise does not get amplified to the same extent as the signal in subsequent stages of an amplification circuit. This approach, however, does not prevent 1/f noise from being introduced at later amplification stages in the circuit where smaller transistors are used. Moreover, the dimensions to which such devices can be scaled down to are limited by the necessity for one or more large early stage transistors.
Negative Bias Thermal Instability (NBTI) is another concern raised as semiconductor device sizes shrink. NBTI is caused by thermal and voltage stress. The activation temperature can be as low as 100° C., and the minimum necessary gate field strength is below 6 MV/cm. These are conditions routinely experienced by MOSFET transistors in current generation integrated circuits. The changes in transistor performance can significantly degrade circuit performance by causing changes in circuit timing, resulting in increased error rates or even device failure.
A cause of NBTI is the formation of trapped charge at the interface between the gate oxide and the channel. Trapped charge results from the removal of hydrogen at the interface between the channel and the gate dielectric. Hydrogen may be incorporated in the interface as a result of hydrogen containing processes during fabrication. Hydrogen is also intentionally introduced at the end of the fabrication process with a forming gas anneal to reduce un-bonded active bonds (i.e., dangling bonds) at the gate oxide-channel interface. These dangling bonds are a consequence of the crystal lattice mismatch between crystalline silicon in the channel and amorphous silicon dioxide in the gate dielectric. Such bonds will result in trapped charge at the interface unless they are passivated.
Several techniques to reduce NBTI are known, including fluorine implantation of the channel and modification of nitrogen content of nitrided gate oxide. Current fluorine implantation processes, while effective at stabilizing the interface, introduces other detrimental effects, such as enhanced boron diffusion in the gate oxide and higher junction leakage.
Addressing the concurrent problems of 1/f noise and NBTI presents challenges, especially when semiconductor device feature sizes have shrunk to deep sub-micron ranges, e.g., less than 90 nm. Current processes developed to address both 1/f noise and NBTI in larger device sizes are inadequate address these issues.
Accordingly, what is needed is a method of fabricating a semiconductor device that addresses these deficiencies.
The invention, in one aspect, provides a method of fabricating a semiconductor device. An embodiment comprises forming a gate dielectric layer over a semiconductor substrate, depositing a gate layer over the gate dielectric layer, incorporating fluorine into the gate dielectric layer and doping the gate layer after incorporating fluorine into the gate dielectric.
In another embodiment, an integrated circuit is fabricated by forming gate electrodes over a semiconductor substrate that includes depositing a gate layer over a gate dielectric layer and incorporating fluorine into the gate dielectric layer before doping the gate layer. The fabrication further includes forming source/drains within the semiconductor substrate and adjacent the gate electrodes, depositing dielectric layers over the gate electrodes, and forming interconnects within and over the dielectric electrodes to interconnect the gate electrodes and form an integrated circuit.
In another embodiment, a semiconductive device is provided that comprises a gate dielectric layer on a substrate, a gate layer located over the gate dielectric layer, where the gate layer being doped with a dopant, and fluorine incorporated into the gate dielectric layer prior to the gate layer being doped with the dopant.
The invention is described with reference to example embodiments and to accompanying drawings wherein:
In the illustrated embodiment, the semiconductor device 100 includes transistors 135, 140. Transistor 135 is an NMOS transistor and transistor 140 is a PMOS transistor. However, various transistor configurations are also within the scope of the invention. The transistors 135, 140 may each comprise source/drains 155 and spacers 160 and silicide contacts 165.
The transistors 135, 140 further include gate dielectric layers 145 over which transistor gate electrodes 150 are located. In the embodiment shown in
The semiconductor device 200 further includes a gate dielectric layer 235. The thickness of the dielectric layer 235 may vary from one embodiment to another, but in one aspect, its thickness will be about 3.5 nm or less. Conventional processes may be used to form the dielectric layer 245, and it may be comprised of conventional materials. Additionally, it may have a high or low dielectric constant (K), e.g, a dielectric constant that is either higher or lower than silicon dioxide. In one aspect, the layer 245 may be silicon dioxide that has been grown in a thermal oxidizing atmosphere and that results in a high quality silicon dioxide. Alternatively, the layer may be comprised of deposited refractory oxides, such as hafnium oxide, or it may also include other deposited dielectric materials, such as silicon oxynitride.
A gate layer 240 is located over the gate dielectric layer 235. The gate layer 240 may also be comprised of conventional materials, such as polysilicon, and conventional processes, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), may be used to deposit the gate layer 240. Gate layer 240 may also be a stacked structure that includes other known materials, such as refractory metals and silicides. While the thickness of the gate layer 240 may vary, one embodiment is directed to thicknesses typically associated with submicron technologies, e.g., 80 nm or less. At this point, the gate layer 240 is not doped to a degree sufficient to allow it to function as an operative gate electrode. However, small amounts or trace amounts of gate dopants may be present. Therefore, for purposes of the invention the gate layer 240 is substantially undoped at this point of manufacture.
After the deposition of the gate layer 240, the semiconductor device 200 is subjected to a fluoridation process 245, such as a fluorine implant or fluorine gas diffusion process. As shown in the embodiment of
Because the gate layer 240 is not substantially doped at the time the fluorine is incorporated into the gate dielectric layer 235, the dopant cannot be diffused into the dielectric layer 235 or the channel region within the active region 215, as in conventional processes. Moreover, the higher temperatures more robustly activate the fluorine without over diffusing the dopant. It has also been found that these higher temperatures improve the interface quality of the gate dielectric layer 235.
The temperature at which the process 245 may be conducted varies depending on the process technology used. However, the process 245 should be conducted at a temperature sufficient to adequately diffuse the fluorine into the gate dielectric layer 235 or to the interface of the gate dielectric layer 235 and the active region 215.
Further, the temperature should be sufficient to activate the fluorine and cause it to replace at least some, if not a substantial portion, of the oxygen within the gate dielectric layer 235; and, thereby, improve the interface quality between the gate layer 240 and the gate dielectric layer 235. Examples of temperatures that may be used to accomplish this include temperatures above about 850° C., with one example being a temperature at or above about 870° C. The implanted dosage of the fluorine will also vary from one embodiment to another.
After the process step 245, the semiconductor device 200 is masked and patterned to expose portions of the gate dielectric layer 235 and gate layer 240 that overlie the well 220, which may be configured as an NMOS device, as seen in
In
As seen in
After the formation of the LDD source/drains 255 and 259, in those embodiments where they are present, conventional processes may then be used to form spacers 262, as seen in FIG. 2G. The spacers 260 may comprise a single layer or multiple layers, as shown, and may be constructed with conventional materials, such as oxides, nitrides, or combinations thereof. Conventional deep source/drain implant process may then be conducted to form source/drains 263 and 264 located adjacent the respect gate electrodes 252 and 254. The dopants and concentrations used to form source/drains 263 and 264 will again depend on the type of device. At this stage of manufacture, silicide contacts 265, which may be fabricated using conventional processes and materials, have also been formed to complete the formation of transistors 266 and 268. The transistors 266, 268 may be configured as all NMOS or PMOS devices, or they may be arranged in a complementary NMOS and PMOS configuration, as shown.
Also shown are gate dielectric layers 335 and gate layers 340 that have been patterned to form gate electrodes 352 and 354. At this point in the process, the gate electrodes 352 and 354 have not been doped to form an operative gate electrode. The materials and processes used to construct these features may be the same as those discussed above regarding other embodiments. Additionally, neither of the gate dielectric layers 335 have been uniformly fluorinated, as with previous embodiments. Thus, the fluoridation process, which is discussed below, can more appropriately be tailored to the type of intended device. In the illustrated embodiment, the gate electrode 352 may be doped to operate as an NMOS device, while the gate electrode 354 may be doped to operate as a PMOS device. Conventional doping and masking processes may be used to dope the respective devices.
This embodiment provides a process for selectively incorporating fluorine into a specific gate dielectric layer. This does not exclude incorporation of fluorine into the gate dielectric layer 335 of gate electrode 354. To do so, the patterned mask 356 can be removed and another mask formed over gate electrode 352 to protect it from a fluoridation process conducted on the exposed gate electrode 354. Alternatively, both gate electrodes 352, 354 may be left exposed to the fluorine implantation process 358.
Following the fluorine implantation process 358, conventional processes may be used to appropriately dope the gate electrodes 352 and 354 and complete the semiconductor device 300 as shown in
Those skilled in the art to which the invention relates will appreciate that other and further additions, deletions, substitutions, and modifications may be made to the described example embodiments, without departing from the invention.
