Patent Application
20080303098
The invention is directed, in general, to a semiconductor device and method of manufacture thereof and, more particularly, to a semiconductor device and manufacturing method to reduce damage to a low-k dielectric material from the effects of chemical mechanical polishing.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. As components have scaled and transistors have gotten closer together, so, too, have the interconnect structures to connect the smaller components in the semiconductor device. The insulating dielectric in interconnect structures have thinned to the point where charge build-up and crosstalk adversely affect the performance of the device. To address these problems, manufacturers have begun replacing silicon dioxide dielectric material with low-k dielectric material of the same thickness to reduce parasitic capacitance, thus enabling faster switching speeds and lower heat dissipation.
However, one drawback of the use of low-k dielectric materials is that they are porous. When exposed to water, a low-k dielectric material can degrade (such as increasing its dielectric constant). Most of the degradation is non-recoverable, even after baking the material. Increasing the dielectric constant of the low-k dielectric material increases parasitic capacitance in the interconnect structure, defeating the purpose of using the low-k dielectric material in the first place. Also, exposing porous, low-k dielectric material to water/moisture increases the occurrence of subsequent cracking of the low-k dielectric material, leading to reliability issues with the finished semiconductor device. Additionally, low-k dielectric material is prone to mechanical damage such as scratches during subsequent processing such a chemical mechanical processing (CMP). Low-k dielectric material is harder to clean and dry due to its porousness and hydrophobicity.
CMP is often used in semiconductor processing to planarize the topography of an interconnect layer prior to depositing a subsequent interconnect layer. Typically a water-based slurry is used during the CMP process and the semiconductor wafer is rinsed with high pressure water after the polishing step. The semiconductor wafer is then cleaned with water based chemicals after the CMP process. In such conventional processes, a low-k dielectric material is often exposed to water in both the polishing step and the post-CMP cleaning, which as explained above, is detrimental to the low-k dielectric material.
Accordingly, what is needed in the art is a method of semiconductor manufacturing to protect low-k dielectric material from exposure to water during a CMP and post-CMP cleaning process, thereby: maintaining the dielectric constant of the low-k dielectric material; reducing the occurrence of subsequent cracking of the low-k dielectric material; protecting the low-k dielectric material from scratches and other mechanically induced damages during the CMP process; and, alleviating the difficulty of cleaning and drying the porous low-k dielectric material.
To address the above-discussed deficiencies of the prior art, in one embodiment, there is provided a method of manufacturing a semiconductor device. In this particular embodiment, the method comprises depositing a barrier layer over a low-k dielectric layer located over a semiconductor substrate over which a metal layer is deposited. A chemical mechanical polish process is used to remove a portion of the metal layer and the barrier layer and a dry etch is used to remove a remaining portion of the barrier layer.
In another embodiment, there is provided another method of manufacturing a semiconductor device. In this embodiment, the method comprises placing a low-k dielectric layer over a semiconductor substrate and depositing a hard mask layer over the low-k dielectric layer. A trench is formed in the low-k dielectric layer, and a metal barrier layer is deposited over the low-k dielectric layer and within the trench. A metal layer is deposited over the barrier layer and within the trench. A chemical mechanical polishing process is used to remove a portion of the metal layer and at least a portion of the barrier layer or the hard mask layer. A dry etch is used to remove another portion of the metal layer and remove a remaining portion of the barrier layer or the hard mask layer adjacent to the trench.
In yet another embodiment there is provided a semiconductor device. In this embodiment, the semiconductor device comprises a low-k dielectric layer located over a semiconductor substrate and a hard mask layer located over the low-k dielectric layer. A trench is located in the low-k dielectric layer with a metal barrier layer and a metal layer located therein. A portion of the metal layer and at least a portion of the metal barrier layer or the hard mask layer are removed using a wet chemical mechanical polishing process. Another portion of the metal layer and a remaining portion of the metal barrier layer or the hard mask layer adjacent to the trench are removed using a dry etch.
For a better understanding, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
In one embodiment, the dielectric layer 125 may be a low-k dielectric material, such as organo silicate glass (OSG), and can be deposited by conventional process, e.g., a spin-on approach or chemical vapor deposition (CVD). As noted above, one reason a low-k dielectric material is used is to reduce parasitic capacitances between differing layers of dielectric materials, which allow for faster switching speeds and lower heat dissipation. A low-k dielectric material is a material that has a dielectric constant lower than that of silicon dioxide (which has a dielectric constant k≈3.9). Most low-k dielectric materials have a dielectric constant of less than 3.0.
A hard mask layer 130 can then be deposited over the low-k dielectric material 125. The hard mask layer 130 may be deposited with a conventional method, such as CVD, and typically consists of silicon nitride or silicon oxide material. A layer of polymeric photoresist 135 is deposited over the hard mask layer 130. Conventional processes may be used to deposit and pattern the photoresist layer 135 for subsequent trench etching.
Subsequent to formation of the trench 240, a barrier metal layer 245 is blanket deposited over the semiconductor device 200 as illustrated in
In one embodiment, the hard mask layer 230 and metal barrier layer 245 in combination form a barrier layer 250 to protect the porous low-k dielectric material layer 225 from a subsequent CMP process step. In another embodiment, the metal barrier layer 245 forms the barrier layer 250 protecting the porous low-k dielectric layer 225. In both embodiments, the metal barrier layer 245 may also serve as a diffusion barrier for a subsequent metal deposition in addition to protecting the porous low-l dielectric layer 225.
As described above, CMP is conducted to planarize the topography of semiconductor device 200 for subsequent layers of interconnect structures, in effect, planarizing the top surface of the semiconductor device 200.
Since the porous low-k dielectric material 225 is protected with the barrier layer 250, there is no need to maintain a short duration time between the CMP process and a next process step. Nor is there a need to keep the semiconductor device 200 in a dry environment, such as a nitrogen box. Also, there is no need to bake the semiconductor device 200.
Subsequent to the CMP process step, an etch stop layer 260, typically a silicon nitride or silicon carbide layer, is blanket deposited on the semiconductor device 200. A conventional process may be used to form the etch stop layer 260. Since the semiconductor device still has the barrier layer 250 over the low-k dielectric material 225, this layer, in one embodiment, is removed prior to the deposition of the etch stop layer 260. The semiconductor device 200 is placed in a conventional deposition machine. In a first chamber of the deposition machine, a non-selective sputter etch removes the barrier layer 250. The sputter etch is non-selective in that it is applied to the entire semiconductor device 200 rather than to a specific area of the semiconductor device 200. The sputter etch typically uses 1000 Watts of power, 5 micro Torr of pressure, and an AC bias of 500 Watts.
Subsequent to the non-selective sputter etch, the semiconductor device 200 is moved to a second chamber of the deposition machine without breaking the vacuum seal of the deposition machine. The silicon nitride or silicon carbide etch stop layer 260 is then deposited on the semiconductor device 200 in the second chamber of the deposition machine. The etch stop layer 260 is deposited over the copper metal layer 255 in the trench 240 and the low-k dielectric material 225.
Those skilled in the art will appreciate that other and further additions, deletions, substitutions, and modifications may be made to the described embodiments without departing from the scope of the invention.
