SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE

Abstract

There is provided a semiconductor device manufacturing method which prevents cracking of an overcoat during polishing process, and a semiconductor wafer and a semiconductor device which have an overcoat free from cracking. A plurality of divided overcoats 10 are formed on each chip 3 in a chip region 2 and on each unavailable chip pattern in an unavailable region in the periphery of the chips 3 on the surface of a semiconductor wafer 1, and the semiconductor wafer 1 is mounted upside down on a table with an intervening film so that the back surface of the semiconductor wafer 1 is polished.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view showing a semiconductor wafer in a first embodiment of the present invention;

FIG. 2 is a detailed view showing a chip formed on a semiconductor wafer of FIG. 1;

FIG. 3 is a detailed view showing an unavailable chip pattern formed in the semiconductor wafer of FIG. 1;

FIG. 4 is a detailed view showing a chip according to a second embodiment of the present invention;

FIG. 5 is a detailed view showing a chip according to a third embodiment of the present invention; and

FIG. 6 is a detailed view showing a chip according to a fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiment 1

FIG. 1 is a schematic view showing the surface side of one semiconductor wafer 1 with a plurality of power semiconductor devices formed thereon in the first embodiment of the present invention. The semiconductor wafer 1 is defined by a plurality of orthogonal dicing line regions X, Y so as to form a chip region 2, a shaded area in the center, which is formed by arraying a plurality of chips 3. An unshaded area in the periphery of the chip region 2 is an unavailable region 4 in which the sufficient size of the chip 3 cannot be obtained. A plurality of the chips 3 and arrayed unavailable chip patterns 5 are formed.

FIG. 2 shows the detail of the chip 3 operating as one power semiconductor device. The chip 3 includes an emitter electrode 6 and a gate bonding pad 7 as metal interconnection layers made of aluminum and the like, and a gate line 8 extending from the gate bonding pad 7 so as to divide the emitter electrode 6. The chip 3 has a guard ring 9 formed in the periphery thereof.

The surface of the chip 3 is coated with, for example, polyimide resin as an overcoat 10, and the overcoat on the emitter electrode 6 and the gate bonding pad 7 has an opening section in order to allow electric connection to the outside of the chip 3 via wire-bonding and the like. The opening section in the emitter electrode 6 are divided into a plurality of sections by making the overcoat remain on the gate line 8 (the opening sections are hereinbelow referred to as emitter bonding regions 11).

FIG. 3 shows the detail of the unavailable chip pattern 5. The unavailable chip pattern 5 has a plurality of overcoats 12 formed on the surface thereof, the overcoats 12 being formed by dividing an overcoat into a grid so that the area of an overcoat 12 becomes smaller than the area of a chip 3.

Further, after the overcoats 10, 12 are formed, the semiconductor wafer 1 is mounted upside down on the table of a polishing device with an intervening film so that the back surface thereof is polished with a grinder.

Description is now given of the operation of the semiconductor wafer 1 having the above structure.

In the present embodiment, the overcoats 12 are formed on the unavailable region 4, so that in the polishing process, not only the chip region 2 but also the unavailable region 4 are supported by the table. As a result, the pressure from the grinder is evenly received by the entire surface of the semiconductor wafer 1. Also, since a plurality of the overcoats 12 in the unavailable region 4 surrounding the chip region 2, which are formed by dividing an overcoat into pieces smaller than the area of a chip 3, alleviate (suppress) sagging of the film to decrease the stress, the stress in the chip region 2 can also be alleviated and the overcoat 10 in the chip 3 can be made less likely to have cracking.

Since cracking of the overcoat 10 on the chip 3 can be suppressed simply by changing the overcoat of the unavailable chip pattern 5 which is formed in the unavailable region 4, the semiconductor device can be applied in a wide product range regardless of the pattern of the overcoat 10 on the chips 3 arrayed in the chip region 2.

Embodiment 2

FIG. 4 shows a chip 3 according to the second embodiment of the present invention. In the following description, the components identical to those in the first embodiment will be designated by identical reference numerals, and their description will be omitted.

The chip 3 in the present embodiment further includes a plurality of overcoats 13 which are formed by dividing the overcoat 10 into a plurality of pieces and which are placed in between the emitter bonding regions 11 in the chip in the first embodiment, i.e., on the gate lines 8.

In the present embodiment, the overcoats 13 are formed by dividing the overcoat, which sits on a section where stress is still locally concentrated in the first embodiment, i.e., which sits in between the emitter bonding regions 11, into a plurality of pieces. Since the overcoats 13 are made of small divided pieces, the stress is distributed to a number of the overcoats 13 so that the locally concentrated stress is decreased, and this can make the overcoats 10, 13 on the chip 3 further less likely to have cracking.

Embodiment 3

FIG. 5 shows a chip 3 according to the third embodiment of the present invention.

The chip 3 in the present embodiment includes an overcoat 14 for covering the vicinity of a gate line 8, the periphery of a gate bonding pad 7, and the vicinity of a guard ring 9. It is to be noted that depending on the layout of the gate bonding pad 7, the overcoat 14 may be formed so that a section covering the vicinity of the gate line 8 and the periphery of the gate bonding pad 7 and a section covering the vicinity of the gate line 8 are separated.

In the present embodiment, the overcoat 14 is formed only in the section which may be damaged when coming into pressure contact with the table of a polishing device and which may thereby cause damage upon the functions of the chip 3. Accordingly, the overcoat 14 is formed so that its entire area is small and each area is generally separated from each other. Therefore, even if the film has local sagging in the chip region 2 (chip 3), the overcoat 14 can absorb the deformation and prevent cracking.

Embodiment 4

FIG. 6 shows a chip 3 according to the fourth embodiment of the present invention.

The chip 3 in the present embodiment includes a overcoat 14 formed for covering the vicinity of a gate line 8, the periphery of a gate bonding pad 7 and a guard ring 9 as in the third embodiment, as well as a number of divided small overcoats 15 which are placed generally evenly on the entire surface of the chip 3 except an emitter bonding region 11 and the gate bonding pad 7.

In the present embodiment, the overcoats 15 are divided pieces smaller than those in the third embodiment, so that bending stress can be received in a further distributed state, which prevents cracking of the overcoats 14, 15.

Claims

1. A semiconductor device manufacturing method, comprising the steps for: forming a number of overcoats divided from each other on a surface of a chip region of a semiconductor wafer in which a plurality of chips is formed and on a surface of an unavailable region which is in a periphery of the chip region so that each of the divided overcoats is smaller than an area of the chip at least in the unavailable region;mounting the semiconductor wafer upside down on a table with an intervening film; andpolishing a back surface of the semiconductor wafer.

2. The semiconductor device manufacturing method according to claim 1, wherein the overcoat of the chip region is formed on the respective chips in the state of being divided into a plurality of pieces.

3. The semiconductor device manufacturing method according to claim 1, wherein the overcoat of the chip region is formed only on a gate line and a guard ring.

4. A semiconductor device manufacturing method, comprising the steps for: forming a plurality of divided overcoats on each chip in a chip region on a surface of a semiconductor wafer;mounting the semiconductor wafer upside down on a table with an intervening film; andpolishing a back surface of the semiconductor wafer.

5. A semiconductor device manufacturing method, comprising the steps for: forming an overcoat covering only a gate line and a guard ring on each chip in a chip region on a surface of a semiconductor wafer;mounting the semiconductor wafer upside down on a table with an intervening film; andpolishing a back surface of the semiconductor wafer.

6. A semiconductor wafer, comprising: a plurality of chips formed thereon; anda number of divided overcoats formed on surfaces of the chips and an unavailable region in a periphery of the chips so that each of the overcoats is smaller than an area of the chip at least in the unavailable region,wherein a back surface of the semiconductor wafer is polished.

7. A semiconductor wafer, comprising: a plurality of chips formed thereon; anda plurality of divided overcoats formed on surfaces of each chip,wherein a back surface of the semiconductor wafer is polished.

8. A semiconductor wafer, comprising: a plurality of chips formed thereon; andan overcoat covering only a gate line and a guard ring formed on surfaces of each chip,wherein a back surface of the semiconductor wafer is polished.

9. A semiconductor device, comprising a plurality of divided overcoats formed on a surface of a semiconductor, wherein a back surface of the semiconductor is polished.

10. A semiconductor device, comprising an overcoat formed only on a gate line and a guard ring formed on a surface of a semiconductor, wherein a back surface of the semiconductor is polished.