Patent Application
20250022946
Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or ILD structures, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are typically packaged separately, in multi-chip modules, for example, or in other types of packaging.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the gate-all around transistor (GAA). The GAA device gets its name from the gate structure which can extend around the channel region providing access to the channel on two or four sides. GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes.
However, it can be challenging to integrate the fabrication of GAA features around the nanowire. While current methods have been satisfactory in many respects, continued improvements are still needed.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.
The nanostructure transistor (e.g. nanosheet transistor, nanowire transistor, multi-bridge channel, nano-ribbon FET, gate all around (GAA) transistor structures) described below may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, smaller pitches than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.
Embodiments for forming a semiconductor device structure are provided. The method for forming the semiconductor device structure may include recessing the isolation material surrounding the fin structure after removing the dummy gate structure. The capacitance may be reduced. In addition, the distance between the source/drain epitaxial structures may be increased, and adjacent source/drain epitaxial structures may not merge. The gate length in the isolation material may be smaller than the gate length wrapped around the nanostructures, and the capacitance may be further reduced. In addition, the dummy gate structure may not collapse, due to the lower aspect ratio during etching.
A semiconductor stack including first semiconductor material layers 104 and second semiconductor material layers 106 are formed over a substrate 102, as shown in
Next, first semiconductor material layers 104 and second semiconductor material layers 106 are alternating stacked over the substrate 102 to form the semiconductor stack 107, as shown in
The first semiconductor material layers 104 and second semiconductor material layers 106 may be formed by low pressure chemical vapor deposition (LPCVD) process, epitaxial growth process, other applicable methods, or a combination thereof. The epitaxial growth process may include molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).
It should be noted that, although there are two layers of the first semiconductor material layers 104 and two layers of the second semiconductor material layers 106 shown in
Next, a mask structure is formed over the semiconductor stack 107. The mask structure may be made of silicon nitride, silicon carbon nitride (SiCN), or applicable material. The mask structure may be formed by a deposition process, such as low-pressure CVD (LPCVD) process, plasma enhanced CVD (PECVD) process, or another deposition process.
After the first semiconductor material layers 104 and the second semiconductor material layers 106 are formed as the semiconductor stack 107 over the substrate 102, the semiconductor stack 107 is patterned to form fin structures 110 using the mask structure as a mask layer, as shown in
The patterning process may include forming a mask structure over the first semiconductor material layers 104 and the second semiconductor material layers 106 and etching the semiconductor stack 107 and the underlying substrate 102 through the mask structure. The mask structure may be a multilayer structure including a pad layer and a hard mask layer formed over the pad layer. The pad layer may be made of silicon oxide, which may be formed by thermal oxidation or CVD. The hard mask layer may be made of silicon nitride, which may be formed by CVD, such as LPCVD or plasma-enhanced CVD (PECVD).
The patterning process of forming the fin structures 110 may include a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.
After the fin structures 110 are formed, a liner layer is formed over the fin structures 110 and in the trenches between the fin structures 110. The liner layer may be conformally formed over the substrate 102, the fin structure 110, and the mask structure covering the fin structure 110. The liner layer may be used to protect the fin structure 110 from being damaged in the following processes (such as an anneal process or an etching process). The liner layer may be made of silicon nitride. The liner layer may be formed by using a thermal oxidation, a CVD process, an atomic layer deposition (ALD) process, a LPCVD process, a plasma enhanced CVD (PECVD) process, a HDPCVD process, a flowable CVD (FCVD) process, another applicable process, or a combination thereof.
Next, an isolation structure material 116 is then filled into the trenches between the fin structures 110 and over the liner layer, as shown in
Next, a dummy gate structure 122 is formed over and across the fin structures 110, as shown in
The dummy gate dielectric layer 118 may include one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, or a combination thereof. The dummy gate dielectric layer 118 may be formed by an oxidation process (e.g., a dry oxidation process, or a wet oxidation process), a chemical vapor deposition process, other applicable processes, or a combination thereof. Alternatively, the dummy gate dielectric layer 118 may include a high-k dielectric layer (e.g., the dielectric constant is greater than 3.9) such as hafnium oxide (HfO2). Alternatively, the high-k dielectric layer may include other high-k dielectrics, such as LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3, BaTiO3, BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, (Ba, Sr)TiO3, Al2O3, other applicable high-k dielectric materials, or a combination thereof. The high-k dielectric layer may be formed by a chemical vapor deposition process (e.g., a plasma enhanced chemical vapor deposition (PECVD) process, or a metalorganic chemical vapor deposition (MOCVD) process), an atomic layer deposition (ALD) process (e.g., a plasma enhanced atomic layer deposition (PEALD) process), a physical vapor deposition (PVD) process (e.g., a vacuum evaporation process, or a sputtering process), other applicable processes, or a combination thereof.
The dummy gate electrode layer 120 may include polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), other applicable materials, or a combination thereof. The dummy gate electrode layer 120 may be formed by a chemical vapor deposition process (e.g., a low pressure chemical vapor deposition process, or a plasma enhanced chemical vapor deposition process), a physical vapor deposition process (e.g., a vacuum evaporation process, or a sputtering process), other applicable processes, or a combination thereof.
Hard mask layers 128 are formed over the dummy gate structure 122, as shown in
The formation of the dummy gate structure 122 may include conformally forming a dielectric material as the dummy gate dielectric layer 118. Afterwards, a conductive material may be formed over the dielectric material as the dummy gate electrode layers 120, and the bi-layered hard mask layers 128, including the oxide layer 124 and the nitride layer 126, may be formed over the conductive material. Next, the dielectric material and the conductive material may be patterned and etched through the bi-layered hard mask layers 128 to form the dummy gate structure 122, as shown in
Next, a spacer layer material 132 is formed over the substrate 102 and the dummy gate structure 122, as shown in
Later, an etching process is performed. A pair of spacer layers 132 is formed over opposite sidewalls of the dummy gate structure 122, and a source/drain opening is formed beside the dummy gate structure 122, as shown in
After the spacer layers 132 are formed, the first semiconductor material layers 104 and the second semiconductor material layers 106 of the fin structure 110 not covered by the dummy gate structure 122 and the spacer layers 132 are etched to form the trenches beside the dummy gate structure 122, as shown in
The fin structures 110 may be recessed by performing a number of etching processes. That is, the first semiconductor material layers 104 and the second semiconductor material layers 106 of the fin structures 110 may be etched in different etching processes. The etching process may be a dry etching process or a wet etching process. The fin structures 110 may be etched by a dry etching process.
In some embodiments, the spacer layers 132 formed over the isolation structure material 116 is removed, and the top surface of the isolation structure material 116 is exposed in a cross-sectional view outside the dummy gate structure 122 along the extending direction of the dummy gate structure 122.
In some embodiments, after the etching process, the isolation material 116 between the source/drain openings has a flat top surface. In addition, the bottom surface of the source/drain openings is higher than the bottom surface of the first semiconductor layer 104 of the semiconductor stack 107.
Next, the first semiconductor material layers 104 may be laterally etched from the source/drain opening to form recesses. The outer portions of the first semiconductor material layers 104 may be removed, and the inner portions of the first semiconductor material layers 104 under the dummy gate structure 122 and the spacer layers 132 may remain. After the lateral etching process, the sidewalls of the etched first semiconductor material layers 104 may be not aligned with the sidewalls of the second semiconductor material layers 106.
The lateral etching of the first semiconductor material layers 104 may be a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the first semiconductor material layers 104 are Ge or SiGe and the second semiconductor material layers 106 are Si, and the first semiconductor material layers 104 are selectively etched to form the recesses by using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions, or the like.
Next, an inner spacer 134 is formed in the recess, as shown in
In some embodiments, the dielectric constant of the isolation structure material 116 is lower than the dielectric constants of the spacer layer 132 and the inner spacer 134.
Next, a source/drain epitaxial structure 136 is formed in the source/drain opening, as shown in
A strained material may be grown in the source/drain opening using an epitaxial (epi) process to form the source/drain epitaxial structure 136. In addition, the lattice constant of the strained material may be different from the lattice constant of the substrate 102. The source/drain epitaxial structure 136 may include SiGeB, SiP, SiAs, SiGe, other applicable materials, or a combination thereof. The source/drain epitaxial structure 136 may be formed by an epitaxial growth step, such as metalorganic chemical vapor deposition (MOCVD), metalorganic vapor phase epitaxy (MOVPE), plasma-enhanced chemical vapor deposition (PECVD), remote plasma-enhanced chemical vapor deposition (RP-CVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), or any other suitable method.
The source/drain epitaxial structure 136 may be in-situ doped during the epitaxial growth process. For example, the source/drain epitaxial structures 136 may be the epitaxially grown SiGe doped with boron (B). For example, the source/drain epitaxial structure 136 may be the epitaxially grown Si doped with carbon to form silicon:carbon (Si:C) source/drain features, phosphorous to form silicon:phosphor (Si:P) source/drain features, or both carbon and phosphorous to form silicon carbon phosphor (SiCP) source/drain features. The source/drain epitaxial structure 136 may be doped in one or more implantation processes after the epitaxial growth process.
Next, a contact etch stop layer 138 is formed over the source/drain epitaxial structure 136, as shown in
The contact etch stop layer 138 may be made of a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride (SiON), other applicable materials, or a combination thereof. The contact etch stop layer 138 may be formed by a chemical vapor deposition process (e.g., a plasma enhanced chemical vapor deposition (PECVD) process, or a metalorganic chemical vapor deposition (MOCVD) process), an atomic layer deposition (ALD) process (e.g., a plasma enhanced atomic layer deposition (PEALD) process), a physical vapor deposition (PVD) process (e.g., a vacuum evaporation process, or a sputtering process), other applicable processes, or a combination thereof.
After the contact etch stop layer 138 is formed, an inter-layer dielectric (ILD) structure 140 is formed over the contact etch stop layer 138, as shown in
Afterwards, a planarizing process or an etch-back process may be performed on the ILD structure 140 until the top surface of the dummy gate structure 122 is exposed. After the planarizing process, the top surface of the dummy gate structure 122 may be substantially level with the top surfaces of the spacer layers 132 and the ILD structure 140. The planarizing process may include a grinding process, a chemical mechanical polishing (CMP) process, an etching process, other applicable processes, or a combination thereof.
Next, as shown in
The protective layer 142 is used to protect the underlying ILD layer 140, preventing ILD layer 140 consume in the following etching processes. The protective layer 142 is formed by removing the top portion of the ILD layer 140 to form a recess, and the protective layer 142 is formed in the recess, and then the excess protective layer 142 outside of the recess is removed to form the protective layer 142 over the ILD layer 140.
The protective layer 142 may be made of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO2), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or a combination thereof. The protective layer 142 may be formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or another applicable process.
The dummy gate structure 122 may be removed by a dry etching process or a wet etching process. The removal process may include one or more etching processes. For example, when the dummy gate electrode layer 120 is polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the dummy gate electrode layer 120. Afterwards, the dummy gate dielectric layer 118 may be removed using a plasma dry etching, a dry chemical etching, and/or a wet etching.
Next, the isolation structure material 116 and the liner layer exposed by the trench 144 are etched back using an etching process 146, and an isolation structure 116 is formed surrounding the base fin structure, as shown in
As a result, the first semiconductor material layers 104 and the second semiconductor material layers 106 may be exposed. The isolation structure 116 may be a shallow trench isolation (STI) structure 116. The isolation structure 116 may be configured to electrically isolate active regions such as fin structures 110 of the semiconductor structure 10a and prevent electrical interference and crosstalk.
In some embodiments, since the isolation structure material 116 is etched after forming the spacer layer 132, the isolation structure material 116 under the spacer layer 132 remains after the etching process 146. In some embodiments, the bottommost surface of the spacer layer 132 is higher than the bottommost surface of the topmost second semiconductor material layer 106.
Next, the first semiconductor material layers 104 are removed and gaps are formed between the first semiconductor material layers 104. More specifically, the second semiconductor material layers 106 exposed by the gaps form nanostructures 106, and the nanostructures 106 are configured to function as channel regions in the resulting semiconductor devices 10a in accordance with some embodiments.
The first semiconductor material layers 104 may be removed by performing one or more etching processes. The etching process may include a selective wet etching process, such as APM (e.g., ammonia hydroxide-hydrogen peroxide-water mixture) etching process. The wet etching process uses etchants such as ammonium hydroxide (NH4OH), TMAH, ethylenediamine pyrocatechol (EDP), and/or potassium hydroxide (KOH) solutions.
Next, a gate structures 150 are formed surrounding the nanostructures 106 and over the nanostructures 106, as shown in
The gate structures 150 may be a multi-layered structure. Each of the gate structures 150 may include an interfacial layer, a gate dielectric layer, a work function layer, and a gate electrode layer.
The interfacial layer may be formed around the nanostructures 106 and on the exposed portions of the base fin structures. The interfacial layer may be made of silicon oxide, and the interfacial layer may be formed by thermal oxidation.
The gate dielectric layer may be formed over the interfacial layer, so that the nanostructures 106 are surrounded (e.g. wrapped) by the gate dielectric layer. In addition, the gate dielectric layer also covers the sidewalls of the spacer layers 132 and the inner spacers 134 in accordance with some embodiments. The gate dielectric layer may be made of one or more layers of dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other applicable high-k dielectric materials, or a combination thereof. The gate dielectric layer may be formed using CVD, ALD, other applicable methods, or a combination thereof.
The work function layers may be conformally formed over the nanostructure 106. The work function layers may be multi-layer structures. The work function layers may be made of a metal material. The metal material of the work function layers may include an N-work-function metal. The N-work-function metal may include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or a combination thereof. The metal material of the work function layer may include a P-work-function metal. The P-work-function metal may include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru) or a combination thereof. The work function layers may be formed by using CVD, ALD, other applicable methods, or a combination thereof.
Next, a gate electrode layer may be formed over the work function layer. The gate electrode layer may be made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof. The gate electrode layer may be formed using CVD, ALD, electroplating, another applicable method, or a combination thereof. After the gate electrode layer is formed, a planarization process such as CMP or an etch-back process may be performed.
In some embodiments, the gate structure 150 surrounding the nanostructures 106 has a length L1, and the gate structure 150 has a length L2 between the fin structures 110. In some embodiments, the length L2 of the gate structure 150 between the fin structures 110 is substantially equal to the length L1 of the gate structure 150 surrounding the nanostructures 106.
Next, a gate isolation structure 152 is formed between the fin structures 110, as shown in
A mask layer may be formed over the gate structure 150. The mask layer may be a hard mask layer made of SiN, SOC, other suitable materials, or a combination thereof. The mask layer may be formed using spin coating, LPCVD, PECVD, PVD, ALD, or other suitable processes.
Afterwards, an opening may be formed in the mask layer, the gate structure 150, and the isolation structure 116 between the fin structures 110. Next, the gate isolation structure material may be deposited in the opening. Afterwards, a removal process, such as CMP or other suitable processes, may be performed to remove excess gate isolation structure material from over the gate structure 150, such that upper surfaces of the gate isolation structure material are substantially level with upper surfaces of the gate structure 150. Therefore, the gate isolation structure 152 is formed in the opening.
The gate isolation structure 152 may provide isolation between the fin structures 110. The gate isolation structure 152 may be made of SiN, SiCN, SiCON, other suitable materials, or a combination thereof. The position of the gate isolation structure 152 may be defined by a patterning process, and the gate isolation structure 152 may be formed by CVD, such as LPCVD or plasma-enhanced CVD (PECVD).
Next, an opening is formed in the ILD structure 140, and a metal semiconductor compound layer may be formed over the source/drain epitaxial structure 136. The metal semiconductor compound layer may reduce the contact resistance between the source/drain epitaxial structure 136 and the subsequently formed contact structure over the source/drain epitaxial structure 136. The metal semiconductor compound layer may be made of titanium silicide (TiSi2), nickel silicide (NiSi), cobalt silicide (CoSi), or other suitable low-resistance materials. The metal semiconductor compound layer may be formed over the source/drain epitaxial structure 136 by forming a metal layer over the source/drain epitaxial structure 136 first. The metal layer may react with the source/drain epitaxial structure 136 in an annealing process and a metal semiconductor compound layer may be produced. Afterwards, the unreacted metal layer may be removed in an etching process and the metal semiconductor compound layer may be left.
Next, a barrier layer may be conformally formed over the bottom surface and the sidewalls of the opening. Afterwards, the barrier layer may be etched back. The barrier layer remains over the bottom surface of the opening. The barrier layer may be formed before filling the conductive material in the opening to prevent the conductive material from diffusing out. The barrier layer may also serve as an adhesive or glue layer. The material of the barrier layer may be TiN, Ti, other applicable materials, or a combination thereof. The barrier layer may be formed by depositing the barrier layer materials by a physical vapor deposition process (PVD) (e.g., evaporation or sputtering), an atomic layer deposition process (ALD), an electroplating process, other applicable processes, or a combination thereof.
Afterwards, a contact structure 154 is formed into the opening over the source/drain epitaxial structure 136, as shown in
In some embodiments, the contact structure 154 formed over adjacent source/drain epitaxial structures 136 are separated from each other.
By etching back the isolation structure material 116 after removing the dummy gate structure 122, the remaining isolation structure material 116 formed under the spacer layers 132 may reduce the amount of parasitic capacitance. The height of the dummy gate structure 122 is also lowered. Therefore, the dummy gate structure 122 may not collapse, due to the lower aspect ratio during the etching process.
Many variations and/or modifications may be made to the embodiments of the disclosure.
The isolation structure material 116 is etched back, and the remaining isolation structure material 116 surrounds the base portion of the fin structures 110, as shown in
Next, a refill material 160 is deposited over the isolation structure material 116 between the fin structures 110, as shown in
In some embodiments, the dielectric constant of the isolation structure material 116 is lower than the dielectric constant of the refill material 160. The film quality may be better, and isolation may be enhanced. In some embodiments, the dielectric constant of the refill material 160 is lower than the dielectric constants of the spacer layer 132 and the inner spacer 134. In some embodiments, the dielectric constant of the refill material 160 is greater than 3.9. In some embodiments, the refill material 160 and the isolation structure material 116 are made of different materials.
The refill material 160 may be deposited by a deposition process, such as a chemical vapor deposition (CVD) process (e.g. a flowable CVD (FCVD) process), a spin-on-glass process, or another applicable process. In some embodiments, the top surface of the refill material 160 is substantially level with the top surface of the semiconductor stack 107.
Afterwards, the dummy gate structure 122 is formed over the fin structure 110, and the spacer layers 132 is formed over the opposite sides of the dummy gate structure 132. The source/drain epitaxial structure 136 is formed over opposite sides of the dummy gate structures 122. The etch stop layer 138 is formed over the source/drain epitaxial structure 136, and the ILD structure 140 is formed over the source/drain epitaxial structure 136, as shown in
In some embodiments, the isolation material 116 and the etch stop layer 138 are separated by the refill material 160.
After removing the dummy gate structure 122, the refill material 160 exposed by the trench 144 are etched back using an etching process 146, and the refill material 160 surrounding the fin structure 110 is removed, as shown in
In some embodiments, since the refill material 160 is etched after forming the spacer layer 132, the refill material 160 under the spacer layer 132 remains after the etching process 146.
Later, the gate structure 150 is formed in the trench 144, the gate isolation structure 152 is formed between the fin structures 110, and the contact structures 154 are formed over the source/drain epitaxial structures 136, as shown in
By etching back the refill material 160 after removing the dummy gate structure 122, the remaining refill material 160 and the isolation structure material 116 formed under the spacer layers 132 may reduce the parasitic capacitance. The height of the dummy gate structure 122 is also lowered. Therefore, the dummy gate structure 122 may not collapse, due to the lower aspect ratio during the etching process. The refill material 160 may provide better film quality.
Many variations and/or modifications may be made to the embodiments of the disclosure.
In some embodiments, the isolation structure material 116 between the spacer layers 132 has a curved top surface in a cross-sectional view between the fin structures 110, as shown in
Next, the gate structure 150 is formed in the trench 144, the gate isolation structure 152 is formed between the fin structures 110, and the contact structures 154 are formed over the source/drain epitaxial structures 136, as shown in
In some embodiments, the bottom portion of the gate structure 150 over the isolation material 116 is narrower than the gate structure 150 wrapped around the second semiconductor layers 106. In some embodiments, the gate structure 150 surrounding the nanostructures 106 has a length L1, and the gate structure 150 has a length L2 between the fin structures 110. In some embodiments, the length L2 of the gate structure 150 between the fin structures 110 is less than the length L1 of the gate structure 150 surrounding the nanostructures 106. With a shorter length L2 of the gate structure 150 between the fin structures 110, the outer fringe parasitic capacitance between the contact structure 154 and the source/drain epitaxial structures 136 may be reduced. In addition, the gate structure 150 and the source/drain epitaxial structures 136 may not be short-circuited.
In some embodiments, the length L2 of the gate structure 150 is less than the length L1 of the gate structure 150 by a distance in a range of about 1 nm to about 6 nm. If the difference is too great, the length L2 of the gate structure 150 may be too short, and the dummy gate structure 122 surrounding the nanostructures 106 may remain. The electrical characteristics of the semiconductor structure 10c may be worse.
By etching back the isolation structure material 116 after removing the dummy gate structure 122, the remaining isolation structure material 116 formed under the spacer layers 132 may reduce the parasitic capacitance. The height of the dummy gate structure 122 is also lowered. Therefore, the dummy gate structure 122 may not collapse, due to the lower aspect ratio during the etching process. The length L2 of the gate structure 150 between the fin structures 110 is less than the length L1 of the gate structure 150 surrounding the nanostructures 106. The parasitic capacitance may be reduced, and the gate structure 150 and the source/drain epitaxial structures 136 may not be short-circuited.
Many variations and/or modifications may be made to the embodiments of the disclosure.
When the first semiconductor material layers 104 being laterally etched from the source/drain opening to form a recess, the upper first semiconductor material layers 104 may be etched more than the lower first semiconductor material layers 104. Therefore, the upper inner spacer 134 formed in the recess may be wider than the lower inner spacer 134 formed in the recess.
Next, the dummy gate structure 122 may be removed, and the isolation structure material 116 may be etched back. In some embodiments, less of the bottom portion of the isolation structure material 116 than the top portion of the isolation structure material 116 is laterally removed, as shown in
Next, the gate structure 150 is formed in the trench 144, the gate isolation structure 152 is formed between the fin structures 110, and the contact structures 154 are formed over the source/drain epitaxial structures 136, as shown in
In some embodiments, the lower portion of the gate structure 150 surrounding the nanostructures 106 is longer than the upper portion of the gate structure 150 surrounding the nanostructures 106.
In some embodiments, the length L3 of the higher gate structure 150 surrounding the nanostructure 106 is less than the length L1 of the lower gate structure 150 surrounding the nanostructure 106. In some embodiments, the length L2 of the gate structure 150 between the fin structures 110 is less than the length L3 of the higher gate structure 150 surrounding the nanostructure 106.
In some embodiments, the length L2 of the gate structure 150 is less than the length L1 of the gate structure 150 by a distance in a range of about 1 nm to about 6 nm. If the difference is too great, the length L2 of the gate structure 150 may be too short, and the dummy gate structure 122 surrounding the nanostructures 106 may remain. The electrical characteristics of the semiconductor structure 10c may be worse.
In some embodiments, the length L3 of the gate structure 150 is less than the length L1 of the gate structure 150 by a distance in a range of about 1 nm to about 6 nm. If the difference is too great, the capacitance caused by the longer bottom gate structure 150 may be increased.
By etching back the isolation structure material 116 after removing the dummy gate structure 122, the remaining isolation structure material 116 formed under the spacer layers 132 may reduce the parasitic capacitance. The height of the dummy gate structure 122 is also lowered. Therefore, the dummy gate structure 122 may not collapse, due to the lower aspect ratio during the etching process. The length L2 of the gate structure 150 between the fin structures 110 is less than the length L1 of the gate structure 150 surrounding the nanostructures 106. The parasitic capacitance may be reduced, and the gate structure 150 and the source/drain epitaxial structures 136 may not be short-circuited. In addition, the length L3 of the higher gate structure 150 surrounding the nanostructure 106 is less than the length L1 of the lower gate structure 150 surrounding the nanostructure 106.
Many variations and/or modifications may be made to the embodiments of the disclosure.
In some embodiments, the spacer layers 132 formed over the isolation structure material 116 is removed, and the top surface of the isolation structure material 116 is exposed in a cross-sectional view outside the dummy gate structure 122 along the extending direction of the dummy gate structure 122 (i.e., the Y direction).
In some embodiments, when forming the source/drain opening, the isolation structure material 116 is less recessed since the dry etching rate of the isolation structure material 116 is low. In some embodiments, the isolation structure material 116 is not consumed during the dry etching process.
Next, the source/drain epitaxial structures 136 are formed in the source/drain opening, as shown in
In some embodiments, the shortest distance W3 is the distance between adjacent source/drain epitaxial structures 136, and the distance W1 is the distance between adjacent source/drain epitaxial structures 136 in the isolation structure material 116. In some embodiments, the ratio of distance W3 to distance W1 is in a range of about 0.5 to about 1. If the ratio of the distance W3 to the distance W1 is too low, adjacent source/drain epitaxial structure 136 may be merged.
In some embodiments, the source/drain epitaxial structures 136 are laterally extended by a distance L. In some embodiments, the lateral distance L is less than 3 nm. If the lateral distance L is too great, adjacent source/drain epitaxial structure 136 may be merged.
Next, the ILD structure 140 is formed over the source/drain epitaxial structure 136, and the dummy gate structure 122 is removed, as shown in
Afterwards, the isolation structure material 116 is etched back by the etching process 146, as shown in
In some embodiments, the middle portion at half height of the source/drain epitaxial structure 136 is surrounded by the isolation material 116, not by the contact etch stop layer 138.
By etching back the isolation structure material 116 after removing the dummy gate structure 122, the remaining isolation structure material 116 formed under the spacer layers 132 may reduce the parasitic capacitance. The height of the dummy gate structure 122 is also lowered. Therefore, the dummy gate structure 122 may not collapse, due to the lower aspect ratio during etching. Higher isolation structure material 116 may confine the growth of the source/drain epitaxial structures 136, and adjacent source/drain epitaxial structures 136 may not merge.
Many variations and/or modifications may be made to the embodiments of the disclosure.
Next, the source/drain epitaxial structures 136 are formed in the source/drain opening, and the refill material 160 is etched back, as shown in
Later, the gate structure 150 is formed in the trench 144, the gate isolation structure 152 is formed between the fin structures 110, and the contact structures 154 are formed over the source/drain epitaxial structures 136, as shown in
In some embodiments, the middle portion at half height of the source/drain epitaxial structure 136 is surrounded by the refill material 160, not by the contact etch stop layer 138.
By etching back the refill material 160 after removing the dummy gate structure 122, the remaining refill material 160 under the spacer layers 132 may reduce the parasitic capacitance. The height of the dummy gate structure 122 is also lowered. Therefore, the dummy gate structure 122 may not collapse, due to the lower aspect ratio during etching. A higher refill material 160 may confine the growth of the source/drain epitaxial structures 136, and adjacent source/drain epitaxial structures 136 may not merge.
Many variations and/or modifications may be made to the embodiments of the disclosure.
An opening may be formed in the ILD structure 140, and adjacent source/drain epitaxial structures 136 and the refill material 160 between the source/drain epitaxial structures 136 are exposed in the opening. The etching process of forming the opening may stop over the refill material 160.
Afterwards, a contact structure 154 is formed into the opening over the source/drain epitaxial structure 136, as shown in
By etching back the refill material 160 after removing the dummy gate structure 122, the remaining refill material 160 under the spacer layers 132 may reduce the parasitic capacitance. The height of the dummy gate structure 122 is also lowered. Therefore, dummy gate structure 122 may not collapse, due to the lower aspect ratio during etching. The contact structure 154 formed over adjacent source/drain epitaxial structures 136 may be merged with an extending portion 154e stop over the refill material 160. The parasitic capacitance may be reduced.
Many variations and/or modifications may be made to the embodiments of the disclosure.
After forming the dummy gate structure 122, the gate isolation structure 152c may be formed in the dummy gate structure 122 over the refill material 160. Later, the dummy gate structure 122 is removed, and the gate isolation structure 152c remains over the refill material 160, as shown in
The gate isolation structure 152c may be made of oxide, such as SiO2, SiOCN, SiON, or the like. The gate isolation structure 152c may also be made of a high k dielectric material, such as HfO2, ZrO2, HfAlOx, HfSiOx, Al2O3, or the like. The gate isolation structure 152c may be formed by performing ALD, CVD, PVD, another suitable process, or a combination thereof.
After the dummy gate structure 122 is removed, the refill material 160 is etched back, as shown in
Later, the gate structure 150 is formed in the trench 144, as shown in
Next, the contact structures 154 are formed over the source/drain epitaxial structures 136, as shown in
By etching back the refill material 160 after removing the dummy gate structure 122, the remaining refill material 160 under the spacer layers 132 may reduce the parasitic capacitance. The height of the dummy gate structure 122 is also lowered. Therefore, dummy gate structure 122 may not collapse, due to the lower aspect ratio during etching. The gate structures 150 may be isolated by forming a gate isolation structure 152c over the refill material 160.
As described previously, the isolation structure material 116 may be etched back after removing the dummy gate structure 122. Therefore, the isolation structure material 116 that remains under the spacer layers 132 may reduce the parasitic capacitance. The dummy gate structure 122 may not collapse, due to the lower height of the dummy gate structure 122. In some embodiments as shown in
Embodiments of a semiconductor device structure and a method for forming the same are provided. The isolation structure material is etched back after removing the dummy gate structure, but it remains under the spacer layers. The capacitance may be reduced. Higher isolation structure material may confine the growth of the source/drain epitaxial structures, and adjacent source/drain epitaxial structures may not merge.
In some embodiments, a method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming fin structures over a substrate. The method for forming a semiconductor device structure also includes depositing an isolation material surrounding the fin structures. The method for forming a semiconductor device structure also includes forming a dummy gate structure across the fin structure. The method for forming a semiconductor device structure also includes growing source/drain epitaxial structures over opposite sides of the dummy gate structure. The method for forming a semiconductor device structure also includes removing the dummy gate structure. The method for forming a semiconductor device structure also includes recessing the isolation material after removing the dummy gate structure. The method for forming a semiconductor device structure also includes forming a gate structure over the isolation material.
In some embodiments, a method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming fin structures with first semiconductor layers and second semiconductor layers alternately disposed over a substrate. The method for forming a semiconductor device structure also includes forming an isolation material surrounding base portions of the fin structures. The method for forming a semiconductor device structure also includes forming a refill material over the isolation material. The method for forming a semiconductor device structure also includes forming a dummy gate structure across the fin structure. The method for forming a semiconductor device structure also includes forming spacer layers over opposite sides of the dummy gate structure. The method for forming a semiconductor device structure also includes removing the dummy gate structure to form a gate trench between the spacer layers. The method for forming a semiconductor device structure also includes removing the refill material exposed by the gate trench. The method for forming a semiconductor device structure also includes removing the first semiconductor layers. The method for forming a semiconductor device structure also includes forming a gate structure wrapped around the second semiconductor layers.
In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes fin structures with nanostructures formed over a substrate. The semiconductor device structure also includes an isolation material surrounding the fin structures. The semiconductor device structure also includes a gate structure surrounding the nanostructures and longitudinally oriented along a first direction. The semiconductor device structure also includes spacer layers formed over opposite sides of the gate structure. The semiconductor device structure also includes source/drain epitaxial structures formed at opposite sides of the gate structures in a second direction. The second direction is different from the first direction. The semiconductor device structure also includes a gate isolation structure formed between the fin structures. The semiconductor device structure also includes contact structures formed over the source/drain epitaxial structures. The bottommost surface of the spacer layers is higher than the bottommost surface of the topmost nanostructures in a cross-sectional view over the spacer layers along the first direction.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
