Embodiments of the disclosure relate to the field of semiconductor device design and fabrication. More specifically, embodiments of the disclosure relate to methods of forming an array of openings in a substrate, to related methods of forming a semiconductor device structure, and to a related semiconductor device structure.
A continuing goal of integrated circuit fabrication is to decrease the dimensions thereof. Integrated circuit dimensions can be decreased by reducing the dimensions and spacing of the constituent features or structures thereof. For example, by decreasing the dimensions and spacing of features (e.g., storage capacitors, access transistors, access lines, etc.) of a memory device, the overall dimensions of the memory device may be decreased while maintaining or increasing the storage capacity of the memory device.
Reducing the dimensions and spacing of semiconductor device features places ever increasing demands on the methods used to form the features. For example, due to limitations imposed by optics and radiation wavelengths, many conventional photolithographic methods cannot facilitate the formation of features having critical dimensions (e.g., widths, diameters, etc.) of less than about sixty (60) nanometers (nm). Electron beam (E-beam) lithography and extreme ultraviolet (EUV) lithography have been used to form features having critical dimensions less than 60 nm, but generally require complex processes and significant costs.
One approach for achieving features having critical dimensions of less than about 60 nm has been the use of pitch density multiplication processes, such as pitch density doubling processes. In a conventional pitch density doubling process, a photolithographic process is used to form photoresist lines over a sacrificial material over a substrate. The sacrificial material is etched using the photoresist lines to form mandrels, the photoresist lines are removed, spacers are formed on sides of the mandrels, and the mandrels are removed. The remaining spacers are used as a mask to pattern the substrate. Where the initial photolithography process formed one feature and one trench across a particular width of the substrate, after pitch density doubling, the same width of the substrate can include two smaller features and two smaller trenches, the width of each of the smaller trenches defined by the width of the spacers. Thus, the use of pitch density doubling can halve the minimum critical dimensions of features formed by the photolithographic processes, resulting in features having minimum critical dimension of about 30 nm. However, to achieve features having critical dimensions less than about 30 nm, the pitch density doubling process needs to be repeated (i.e., the process becomes a pitch density quadrupling process), significantly increasing processing time as well as energy and material costs.
Another approach for achieving semiconductor device features having critical dimensions of less than about 60 nm has been the use of self-assembling (SA) block copolymers. For example, an SA block copolymer deposited within a trench having particular graphoepitaxial characteristics (e.g., dimensions, wetting properties, etc.) may be annealed to form select morphology (e.g., spherical, lamellar, cylindrical, etc.) domains of one polymer block of the SA block copolymer within a matrix domain of another polymer block of the SA block copolymer. The select morphology domains or the matrix domain can be selectively removed, and the remaining select morphology domains or matrix domain utilized as an etch mask for patterning features into an underlying substrate. As the dimensions of the select morphology domains and the matrix domain are at least partially determined by the chain length of the SA block copolymer, feature dimensions much smaller than 60 nm are achievable (e.g., dimensions similar to those achievable through E-beam and EUV lithography processes). Such methods have, for example, been used to form close-packed, hexagonal arrays of openings in an underlying substrate. However, certain semiconductor device structures may utilize different (i.e., non-hexagonal) array configurations. For example, Dynamic Random Access Memory (DRAM) device structures may utilize rectilinear arrays of openings (e.g., contact openings) rather than hexagonal arrays of openings.
A need, therefore, exists for new, simple, and cost-efficient methods of forming a rectilinear array of openings for a semiconductor device structure, such as, for example, a rectilinear contact array for a memory device structure, that enables the formation of the closely packed openings having critical dimensions (e.g., widths, diameters, etc.) less than or equal to about 30 nm.
Methods of forming a rectilinear array of openings (e.g., a rectilinear contact array) in a substrate are disclosed, as are related methods of forming a semiconductor device structure including the rectilinear array of openings, and a related semiconductor device structure including the rectilinear array of openings. In some embodiments, a template structure having the dimensions, spacing, and wetting characteristics for forming a rectilinear array of cylindrical domains of a first polymer within a matrix domain of a second polymer from a block copolymer material may be formed over a substrate by way of pitch density doubling processes. An appropriate block copolymer material may be deposited in wells defined by the template structure, the block polymer material may be processed (e.g., annealed) to form a self-assembled block copolymer material, and the cylindrical domains of the first polymer may be selectively removed to form a patterned polymer material. The patterned polymer material may be used as a mask to form a rectilinear array of openings in the substrate. The openings of the rectilinear array may each have substantially the same width, such as less than or equal to about 30 nm, and a pitch between adjacent openings may be substantially uniform, such as less than or equal to about 50 nm. The rectilinear array of openings may, for example, be utilized in a dynamic random access memory (DRAM) device. The methods of forming the rectilinear array of openings disclosed herein may decrease processing complexity, steps, and cost relative to conventional methods of forming a rectilinear array of openings. The methods of the disclosure may enable increased opening density, facilitating increased performance in semiconductor device structures (e.g., DRAM cells) and semiconductor devices (e.g., DRAM devices) that rely on high opening (e.g., contact) density.
As used herein, the term “rectilinear array” means and includes an array including rows of features that intersect columns of features at about a ninety degree (90°) angle. Accordingly, a “rectilinear array of openings” means and includes an array of openings including rows of openings that intersect columns of openings at about a ninety degree (90°) angle.
As used herein, the term “pitch” refers to the distance between identical points in two adjacent (i.e., neighboring) features. By way of non-limiting example, the pitch between two adjacent cylindrical domains may be viewed as the sum of the radii of the adjacent cylindrical domains and any space between the adjacent cylindrical domains. Stated another way, the pitch in the foregoing example may be characterized as the distance between the centers of the adjacent cylindrical domains.
As used herein, relational terms, such as “first,” “second,” “over,” “top,” “bottom,” “underlying,” etc., are used for clarity and convenience in understanding the disclosure and accompanying drawings and does not connote or depend on any specific preference, orientation, or order, except where the context clearly indicates otherwise.
As used herein, the term “substantially,” in reference to a given parameter, property, or condition, means to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a small degree of variance, such as within acceptable manufacturing tolerances.
The following description provides specific details, such as material types, material thicknesses, and processing conditions in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art will understand that the embodiments of the present disclosure may be practiced without employing these specific details. Indeed, the embodiments of the present disclosure may be practiced in conjunction with conventional fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a semiconductor device. The semiconductor device structures described below do not form a complete semiconductor device. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form the complete semiconductor device from the semiconductor device structures may be performed by conventional fabrication techniques. Also note, any drawings accompanying the present application are for illustrative purposes only, and are thus not drawn to scale. Additionally, elements common between figures may retain the same numerical designation.
Referring to
The substrate masking material 104 may be a material that is selectively etchable relative to a domain of a self-assembled block copolymer material to be formed over the substrate masking material 104, as described in further detail below. As used herein, a material is “selectively etchable” relative to another material if the material exhibits an etch rate that is at least about five times (5×) greater than the etch rate of another material, such as about ten times (10×) greater, about twenty times (20×) greater, or about forty times (40×) greater. The substrate 102 may be selectively etchable relative to the substrate masking material 104. In some embodiments, the substrate masking material 104 is formed of and includes amorphous carbon. A thickness of the substrate masking material 104 may be selected at least partially based on the etch chemistries and process conditions used to form the rectilinear array of openings of the disclosure, as described in further detail below. By way of non-limiting example, the substrate masking material 104 may have a thickness within a range of from about 100 nanometers (nm) to about 1000 nm, such as from about 200 nm to about 800 nm, or from about 300 nm to about 700 nm. In some embodiments, the substrate masking material 104 has a thickness of about 600 nm.
The template material 106 may be a material that, upon being patterned, facilitates forming a self-assembled block copolymer material including a rectilinear array of cylindrical domains of a first polymer within a matrix domain of a second polymer, as described in further detail below. The template material 106 may, for example, be a material that is preferential wetting to a polymer block (e.g., a minority block, or a majority block) of the block copolymer material (as well as any homopolymers included in the block copolymer material that are of the same polymer type as the polymer block). As a non-limiting example, template material 106 may be formed of and include at least one of a silicon oxide, a silicon nitride, a silicon oxycarbide, and a dielectric anti-reflective coating (DARC) (e.g., a silicon oxynitride, such as a silicon-rich silicon oxynitride). In some embodiments, the template material 106 is selected to be preferential wetting toward a polymethylmethacrylate (PMMA) block of poly(styrene-b-methylmethacrylate) (PS-b-PMMA). In additional embodiments, the template material 106 is selected to be preferential wetting toward a polydimethylsiloxane (PDMS) block of poly(styrene-block-dimethylsiloxane) (PS-b-PDMS). The template material 106 may have a thickness T1 conducive to the patterning of the template material 106 to form a template structure, as described in further detail below. By way of non-limiting example, the thickness T1 of the template material 106 may be within a range of from about 50 nanometers (nm) to about 500 nm, such as from about 50 nm to about 100 nm. In some embodiments, the thickness T1 of the template material 106 is about 75 nm.
The template masking materials 108 may include materials that aid in the patterning of the template material 106. For example, as depicted in
Each of the substrate 102, the substrate masking material 104, the template material 106, and the template masking materials 108 (if present) may be formed using conventional processes including, but not limited to, physical vapor deposition (“PVD”), chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), or spin-coating. PVD includes, but is not limited to, sputtering, evaporation, or ionized PVD. Such processes are known in the art and, therefore, are not described in detail herein.
The patterned photoresist material 114 may include parallel photoresist lines 116 separated by first trenches 118. As used herein, the term “parallel” means substantially parallel. Each of the parallel photoresist lines 116 may be formed of and include a conventional photoresist, such as a photoresist compatible with 13.7 nm, 157 nm, 193 nm, 248 nm, or 365 nm wavelength systems, a photoresist compatible with 193 nm wavelength immersion systems, or a photoresist compatible with electron beam lithographic systems. By way of non-limiting example, each of the parallel photoresist lines 116 may be formed of and include an argon fluoride (ArF) sensitive photoresist (i.e., a photoresist suitable for use with an ArF light source), or a krypton fluoride (KrF) sensitive photoresist (i.e., a photoresist suitable for use with a KrF light source).
Each of the parallel photoresist lines 116 may have substantially the same width W1, thickness T2, and length (not shown). In addition, the parallel photoresist lines 116 may be regularly spaced by a distance D1 (i.e., the width of each of the first trenches 118). Accordingly, a pitch P1 between centerlines C1 of adjacent parallel photoresist lines may be substantially uniform throughout the patterned photoresist material 114. The dimensions and spacing of the parallel photoresist lines 116 may be selected to provide desired dimensions and spacing to parallel spacers to be formed on the parallel photoresist lines 116. For example, the width W1, and the centerline C1 location of each of the parallel photoresist lines 116 may be selected to facilitate the formation of parallel spacers exhibiting smaller dimensions and decreased pitch relative to the parallel photoresist lines 116, as described in further detail below. In some embodiments, the width W1 of each of the parallel photoresist lines 116 is about 50 nm, the distance D1 between adjacent parallel photoresist lines is about 70 nm, and the pitch P1 between adjacent parallel photoresist lines is about 120 nm.
The patterned photoresist material 114 may be formed using conventional processing techniques, which are not described in detail herein. By way of non-limiting example, a photoresist material (not shown) may be formed over the template masking materials 108 and exposed to an appropriate wavelength of radiation through a reticle (not shown) and then developed. The parallel photoresist lines 116 may correlate to portions of the photoresist material remaining after the development, and the first trenches 118 may correlate to portions of the photoresist material removed during the development.
Referring to next to
Each of the parallel spacers 122 may have substantially the same width W2, thickness T3, and length (not shown). The thickness T3 of each of the parallel spacers 122 may be substantially the same as the thickness T2 of each of the parallel photoresist lines 116 (
By way of non-limiting example, if a target pitch between adjacent openings of the rectilinear array of openings to be formed is about 30 nm, the width W2 of each of the parallel spacers 122 may be within a range of from about 6 nm to about 12 nm, the distance D2 between adjacent parallel spacers of the patterned spacer material 120 may be within a range of from about 54 nm and about 48 nm, and the pitch P2 between centerlines C2 of adjacent parallel spacers of the patterned spacer material 120 may be about 60 nm. In some embodiments, the width W2 of each of the parallel spacers 122 is about 10 nm, the distance D2 between adjacent parallel spacers of the patterned spacer material 120 is about 50 nm, and the pitch P2 between adjacent parallel spacers of the patterned spacer material 120 is about 60 nm.
A pitch density doubling process may be utilized to form the patterned spacer material 120 using the patterned photoresist material 114. For example, referring collectively to
In additional embodiments, the patterned spacer material 120 may be formed using structures other than the parallel photoresist lines 116 of the patterned photoresist material 114. Such structures may, for example, be utilized if forming the spacer material over exposed surfaces of the parallel photoresist lines 116 would damage or degrade (e.g., thermally degrade) the parallel photoresist lines 116. By way of non-limiting example, a pattern defined by the patterned photoresist material 114 may be transferred (e.g., by way of at least one etching process) to the template masking materials 108 to form a patterned template masking material (not shown). The patterned spacer material 120 may then be formed using the patterned template masking material through a process substantially similar to that described above in relation to forming the patterned spacer material 120 using the patterned photoresist material 114.
Referring to
To form the intermediate template structure 128, the parallel spacers 122 of the patterned spacer material 120 may be used as a mask for at least one etching process (e.g., an anisotropic etching process) to substantially remove unmasked portions (i.e., portions not underlying the parallel spacers 122) of each of the template masking materials 108 and the template material 106. The unmasked portions of the template masking materials 108 may be completely removed, and the unmasked portions of the template material 106 may be partially removed. The etching process may, for example, extend the first pattern 126 from about 45 percent to about 55 percent of the way through the template material 106. As a non-limiting example, if the thickness T1 of the template material 106 is about 75 nm, the first pattern 126 may be extended from about 35 nm to about 40 nm into the template material 106.
Following the formation of the intermediate template structure 128, remaining portions of the parallel spacers 122 and the template masking materials 108 may be removed, as depicted in
Referring to
The additional protective material 136 may have a thickness sufficient to cover and surround each of the parallel features 130 (
The another patterned photoresist material 140 may include additional parallel photoresist lines 142 separated by third trenches 144. The additional parallel photoresist lines 142 may be formed of and include a conventional photoresist (e.g., an ArF sensitive photoresist, a KrF sensitive photoresist, etc.) that is the same as or different than that of the parallel photoresist lines 116 of the patterned photoresist material 114, previously described with respect to
Referring to next to
The dimensions and spacing of the additional parallel spacers 148 may be selected to provide desired dimensions and spacing for features of a template structure to be formed using the another patterned spacer material 146, as described in further detail below. The additional parallel spacers 148 may have substantially similar dimensions and spacing as the parallel spacers 122 of the patterned spacer material 120, except oriented in a direction substantially perpendicular to that of the parallel features 130 (
By way of non-limiting example, if a target pitch between adjacent openings of the rectilinear array of openings to be formed is about 30 nm, the width W4 of each of the additional parallel spacers 148 may be within a range of from about 6 nm to about 12 nm, the distance D4 between adjacent additional parallel spacers of the another patterned spacer material 146 may be within a range of from about 54 nm and about 48 nm, and the pitch P4 between centerlines C4 of adjacent additional parallel spacers of the another patterned spacer material 146 may be about 60 nm. In some embodiments, the width W4 of each of the additional parallel spacers 148 is about 10 nm, the distance D4 between adjacent additional parallel spacers of the another patterned spacer material 146 is about 50 nm, and the pitch P4 between adjacent parallel spacers of the another patterned spacer material 146 is about 60 nm. The another patterned spacer material 146 may be formed using processes substantially similar to those previously described with respect to forming the patterned spacer material 120.
Referring to
The parallel features 130′ may be substantially similar (e.g., in terms of dimensions and spacing) to the parallel features 130 of the intermediate template structure 128 previously described with reference to
The additional parallel features 156 may have substantially the same width W4, length (not shown), and pitch P4 as each of the additional parallel spacers 148 (
Since the parallel features 130′ and the additional parallel features 156 have substantially the same dimensions and spacing as the parallel spacers 122 and the additional parallel spacers 148, the width W2 of each of the parallel features 130′ and the width W4 of each of the additional parallel features 156 may both be within a range of from about 20 percent to about 40 percent of a target pitch between adjacent openings of a rectilinear array of openings to be formed using the template structure 154, such as from about 20 percent to about 30 percent of the target pitch. In addition the distance D2 between each of the parallel spacers 122 and the distance D4 between of the additional parallel spacers 148 may be within a range of from about 180 percent to about 160 percent of the target pitch between adjacent openings of the rectilinear array of openings to be formed using the template structure 154, such as from about 180 percent to about 170 percent of the target pitch. Further, the pitch P2 between centerlines C2 of adjacent parallel features of the parallel features 130′ and the pitch P4 between centerlines C4 of adjacent additional parallel features of the additional parallel features 156 may both be about two times (2×) the target pitch between adjacent openings of the rectilinear array of openings. Still further, the height H3 of each of the parallel features 130′ and the additional parallel features 156 may be within a range of from about one-half (½) the target pitch between adjacent openings of the rectilinear array of openings and about three times (3×) the target pitch between adjacent openings of the rectilinear array of openings, such as from about one times (1×) the target pitch and about two times (2×) the target pitch.
By way of non-limiting example, if a target pitch between adjacent openings of the rectilinear array of openings to be formed is about 30 nm, the width W2 of each of the parallel features 130′ and the width W4 of each of the additional parallel features 156 may be within a range of from about 6 nm to about 12 nm, the distance D2 between adjacent parallel features of the parallel features 130′ and the distance D4 between adjacent additional parallel features of the additional parallel features 156 may both be within a range of from about 54 nm and about 48 nm, the pitch P2 between centerlines C2 of adjacent parallel features of the parallel features 130′ and the pitch P4 between centerlines C4 of adjacent additional parallel features of the additional parallel features 156 may both be about 60 nm, and the height H3 of each of the parallel features 130′ and the additional parallel features 156 may be within a range of from about is about 15 nm to about 90 nm. In some embodiments, the width W2 of each of the parallel features 130′ and the width W4 of each of the additional parallel features 156 are both about 10 nm, the distance D2 between adjacent parallel features of the parallel features 130′ and the distance D4 between adjacent additional parallel features of the additional parallel features 156 are both about 50 nm, the pitch P2 between centerlines C2 of adjacent parallel features of the parallel features 130′ and the pitch P4 between centerlines C4 of adjacent additional parallel features of the additional parallel features 156 are both about 60 nm, and the height H3 of each of the parallel features 130′ and the additional parallel features 156 is about 35 nm.
As depicted in
Referring collectively to
Referring to
The neutral wetting material 166 may be formed using conventional processes (e.g., a PVD process, a CVD process, an ALD process, or a spin-coating process), which are not described in detail herein. By way of non-limiting example, if the neutral wetting material 166 is a neutral wetting carbon material, the neutral wetting carbon material may be deposited in the wells 160 by a CVD process. As another non-limiting example, if the neutral wetting material 166 is a neutral wetting random copolymer material, the neutral wetting random copolymer material may be spin-coated into the wells 160 and cross-linked (e.g., by way of at least one of thermal-processing and photo-processing). After forming the neutral wetting material 166 on the floor 164 of the wells 160, portions of the neutral wetting material 166 present on surfaces of the template structure 154 (e.g., surfaces of the parallel features 130′, the additional parallel features 156, and the elevated pillars 158 not proximate the substrate masking material 104) may be removed.
In additional embodiments, the neutral wetting material 166 may be formed on the substrate masking material 104 prior to forming the template structure 154. For example, the neutral wetting material 166 may be formed between the substrate masking material 104 and the template material 106 (
Referring next to
The block copolymer material 168 may have an SA block copolymer chain length and volumetric ratio of constituent polymers (i.e., polymer blocks of the SA block copolymer, and, if present, any homopolymers) facilitating the formation of a rectangular (e.g., square) array of cylindrical domains of a first polymer within a matrix domain of a second polymer in each of the wells 160, as described in further detail below. For example, if the block copolymer material 168 is an SA diblock copolymer, a first polymer block to be self-assembled into the cylindrical domains may constitute from about 20 percent to about 40 percent of the total volume of the SA diblock copolymer, and a second polymer block to be self-assembled into the matrix domain may constitute a remaining percentage of the total volume of the SA diblock copolymer (e.g., from about 80 percent to about 60 percent of the total volume of the SA diblock copolymer). If the block copolymer material 168 is a blend of an SA block copolymer and at least one homopolymer, the at least one homopolymer may constitute from about 0.1 percent to about 40 percent of the total volume of the blend. In some embodiments, the block copolymer material 168 is a PS-b-PMMA copolymer including about 30 percent by volume PS and about 70 percent by volume PMMA. In additional embodiments, the block copolymer material 168 is a PS-b-PDMS diblock copolymer including about 30 percent by volume PS and about 70 percent by volume PDMS.
The block copolymer material 168 may substantially fill a remaining portion of each of the wells 160 (i.e., a portion of each of the wells 160 remaining after the formation of the neutral wetting material 166 therein). The sidewalls 162 of the wells 160 may be preferential wetting to one of the polymer blocks of the block copolymer material 168. In addition, the block copolymer material 168 may be substantially contained within the wells 160 (i.e., less than or equal to a monolayer of the block copolymer material 168 may be located outside of the wells 160, such as on the surfaces of the parallel features 130′, the additional parallel features 156, and the elevated pillars 158 outside of the wells 160). In some embodiments, the block copolymer material 168 has a thickness within a range of about 25 nm to about 30 nm and is substantially contained in the wells 160.
The block copolymer material 168 may be formed in each of the wells 160 using conventional processes (e.g., spin-coating, knife-coating, etc.), which are not described in detail herein. By way of non-limiting example, the block copolymer material 168 may be deposited into each of the wells 160 by spin-coating from a dilute solution of the block copolymer material 168 in an organic solvent (e.g., dichloroethane, toluene, etc.). The deposition process may be controlled so that capillary forces pull excess of the block copolymer material 168 (e.g., block copolymer material 168 deposited outside of the wells 160) greater than a monolayer into the wells 160.
Referring to
As shown in
By way of non-limiting example, the width W5 of each of the cylindrical domains 176 of the first polymer may be equal to about one-fourth (¼) of the pitch (e.g., the pitch P2, and the pitch P4) between centerlines (e.g., the centerlines C2, and the centerlines C4) of adjacent features (e.g., adjacent parallel features of the parallel features 130′, and adjacent additional parallel features of the additional parallel features 156) of the template structure 154. In addition, the height H5 of each of the cylindrical domains 176 of the first polymer may be equal to the height of the block copolymer material 168 (
As illustrated in
The self-assembled block copolymer material 170 may be formed using a annealing process. For example, the block copolymer material 168 may be thermally annealed at a temperature above the glass transition temperature of the polymer blocks and homopolymers (if any) of the block copolymer material 168 to effectuate separation and self-assembly according to the wetting characteristics of the wells 160 (e.g., the preferential wetting characteristics of the sidewalls 162, and the neutral wetting characteristics of the neutral wetting material 166 on the floor 164). As another example, the block copolymer material 168 may be solvent annealed by swelling the polymer blocks and homopolymers (if any) of the block copolymer material 168 with a solvent and then evaporating the solvent. In some embodiments, such as where the block copolymer material 168 is a PS-b-PMMA copolymer, the block copolymer material 168 is annealed at a temperature within a range of from about 180° C. to about 250° C. in a vacuum oven or under an inert atmosphere for a period of time within a range of from about 2 minutes to about 24 hours to form the self-assembled block copolymer material 170.
Referring next to
The selective removal of the cylindrical domains 176 of the first polymer to form the patterned polymer material 178 may be performed using conventional processes, which are not described in detail herein. By way of non-limiting example, the cylindrical domains 176 of the first polymer may be removed using at least one of an oxygen plasma process and a chemical dissolution process (e.g., a process including irradiating the cylindrical domains 176 of the first polymer, ultrasonicating the self-assembled block copolymer material 170 in acetic acid, ultrasonicating the self-assembled block copolymer material 170 in deionized water, and rinsing the self-assembled block copolymer material 170 to remove the cylindrical domains 176 of the first polymer).
Referring next to
To form the patterned substrate 184, the matrix domain 174 of the patterned polymer material 178 may be used as a mask for at least one etching process (e.g., an anisotropic etching process, such as an reactive ion etching process) to substantially remove unmasked portions (e.g., portions not underlying the matrix domain 174) of each of the substrate masking material 104 and the substrate 102. The unmasked portions of the substrate masking material 104 may be completely removed, and the unmasked portions of the substrate 102 may be at least partially removed (i.e., may be partially removed, or may be completely removed). The etching process may, for example, extend the rectilinear pattern 182 of openings 180 partially through the substrate 102 to form the rectilinear array 186 of openings 188 of the patterned substrate 184.
Accordingly, a method of forming a rectilinear array of openings in a substrate may comprise forming a template structure comprising a plurality of parallel features and a plurality of additional parallel features perpendicularly intersecting the plurality of additional parallel features of the plurality over a substrate to define wells, each of the plurality of parallel features having substantially the same dimensions and relative spacing as each of the plurality of additional parallel features. A block copolymer material may be formed in each of the wells. The block copolymer material may be processed to form a patterned polymer material defining a pattern of openings. The pattern of openings may be transferred to the substrate to form an array of openings in the substrate.
In addition, a method of forming a semiconductor device structure may comprise forming a template structure comprising intersecting features defining substantially rectangular wells over a substrate, each of the intersecting features having substantially the same dimensions and being preferential wetting to a polymer block of a self-assembling block copolymer. A neutral wetting material may be formed over a floor of each of the substantially rectangular wells. A block copolymer material comprising the self-assembling block copolymer may be formed over the neutral wetting material. The block copolymer material may be self-assembled to form an array of cylindrical domains of a first polymer within a matrix domain of a second polymer, the array of cylindrical domains of the first polymer exhibiting uniform pitch between substantially all adjacent cylindrical domains of the first polymer. The cylindrical domains of the first polymer may be selectively removed to define a pattern of cylindrical openings in the matrix domain of the second polymer. The pattern of cylindrical openings may be transferred to the substrate.
Following the formation of the patterned substrate 184, remaining portions of the template structure 154 (e.g., the parallel features 130′, the additional parallel features 156, and the elevated pillars 158), patterned polymer material 178 (e.g., the matrix domain 174), and the substrate masking material 104 may be removed, as depicted in
Accordingly, a semiconductor device structure of the disclosure may comprise a substrate defining a rectilinear array of openings, each opening of the rectilinear array of openings having substantially the same width of less than or equal to about 25 nm, and adjacent openings of the rectilinear array of openings having substantially the same pitch of less than or equal to about 50 nm.
The methods of the disclosure provide an effective and reliable way to control the dimensions and spacing of the rectilinear array of openings 186 of the patterned substrate 184. The methods facilitate simple and cost-effective formation of very small openings 188 (e.g., critical dimensions of less than or equal to about 30 nm) that are closely packed (e.g., a pitch of less than or equal to about 50 nm) and are substantially aligned in multiple directions (e.g., in the X and Y directions). The methods of the disclosure advantageously facilitate improved device performance, lower cost, increased miniaturization of components, and greater packaging density as compared to conventional methods of forming a contact array for a semiconductor device structure (e.g., a DRAM device structure).
While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure as defined by the following appended claims and their legal equivalents.
This application is a divisional of U.S. patent application Ser. No. 13/646,131, filed Oct. 5, 2012, pending, the disclosure of which is hereby incorporated herein in its entirety by this reference.
Number | Date | Country | |
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Parent | 13646131 | Oct 2012 | US |
Child | 14789297 | US |