Patent Application
20230273245
The present invention relates to a SiC semiconductor device that has a current sensing portion.
A semiconductor device that includes a current sensing portion to detect a current value of a principal current of a device is heretofore known, and semiconductor devices of, for example, Patent Documents 1 and 2 have been proposed.
Generally, a current sensing portion is formed smaller in area than a source portion through which a principal current flows. An area ratio between the current sensing portion and the source portion defines a sensing ratio when the principal current is detected. Additionally, the current value of the principal current is calculated by multiplying the value of an electric current that has actually flowed through the current sensing portion by the sensing ratio.
If conditions other than the area condition are completely identical with each other, the current value of the principal current might be able to be accurately detected only by considering the sensing ratio. However, in practice, differences exist with respect to a condition under which the current sensing portion and the source portion are placed, and the differences affect detection accuracy.
For example, a pad of the source portion is comparatively large, and the occupation area of a bonding wire with respect to the pad is small, and, on the other hand, a pad of the current sensing portion is comparatively small, and therefore the occupation area of the bonding wire with respect to the pad becomes large. This causes a difference in the amount of heat escaping through the bonding wire, and therefore there is a possibility that an error produced in on-resistance between the source portion and the current sensing portion will become large. This error in on-resistance affects the detection accuracy of the current value of the principal current.
An object of the present invention is to provide a SiC semiconductor device that is capable of improving the detection accuracy of the current value of a principal current detected by a current sensing portion by restraining heat from escaping from the current sensing portion to a wiring member joined to a sensing-side surface electrode.
A semiconductor device according to a preferred embodiment of the present invention includes a semiconductor layer made of SiC, a source portion that is formed at the semiconductor layer and that includes a first unit cell on a principal current side, a current sensing portion that is formed at the semiconductor layer and that includes a second unit cell on a current detection side, a source-side surface electrode disposed above the source portion, and a sensing-side surface electrode disposed so that at least one part of the sensing-side surface electrode includes a region positioned above the current sensing portion, and, in the semiconductor device, the second unit cell is disposed at a position below the sensing-side surface electrode and so as to avoid being positioned directly under a joint part of a wiring member.
According to this arrangement, the second unit cell on the current detection side is disposed so as to avoid being positioned directly under the joint part of the wiring member. This makes it possible to maintain a fixed distance between the second unit cell and the wiring member, and hence makes it possible to restrain heat generated at the second unit cell from escaping while being preferentially transmitted to the wiring member. Therefore, it is possible to lessen an error generated in on-resistance between the first unit cell of the source portion and the second unit cell of the current sensing portion. Additionally, the second unit cell is not placed directly under the joint part of the wiring member, and therefore it is possible to prevent a shock caused when the wiring member is joined to the sensing-side surface electrode from running directly to the second unit cell, and it is also possible to restrain the second unit cell from being broken. As a result thereof, it is possible to improve the detection accuracy of the current value of a principal current detected by the current sensing portion.
The use of the semiconductor layer made of SiC makes it possible to achieve an arrangement in which the second unit cell is disposed so as to avoid being positioned directly under the joint part of the wiring member as mentioned above. In other words, in a Si semiconductor device, the amount of flowing current per unit area is small, and therefore a cell area for a somewhat large sensing portion is required to set an appropriate sensing ratio (about 1000 to 2000) having high detection accuracy with respect to a source portion having a large area through which high current flows, and therefore it is difficult to form it so as to avoid being positioned directly thereunder. On the other hand, in the SiC semiconductor device, the amount of flowing current per unit area is large, and therefore it is possible to secure an appropriate sensing ratio even if the sensing portion is small in cell area with respect to the source portion, and therefore it is possible to form it so as to avoid being positioned directly thereunder.
The semiconductor device may include an interlayer insulating film disposed between the current sensing portion and the sensing-side surface electrode and a gate insulating film formed at a lower position than the interlayer insulating film, and, in the semiconductor device, the interlayer insulating film may be formed thicker than the gate insulating film.
According to this arrangement, it is possible to lessen a shock running to the second unit cell when the wiring member is joined to the sensing-side surface electrode. As a result, it is possible to secure the reliability of the detection accuracy of the current value of a principal current.
In the semiconductor device, the current sensing portion may be formed in a region surrounded by the source portion.
According to this arrangement, it is possible to bring the amount of heat generation of the current sensing portion close to that of the source portion, and therefore it is possible to lessen an error in on-resistance generated because of a difference in the amount of heat generation.
The semiconductor device may include a passivation film that selectively covers a portion positioned directly over the second unit cell of the sensing-side surface electrode and that has an opening by which a part of the sensing-side surface electrode is exposed as a sensing-side pad.
According to this arrangement, the portion positioned directly over the second unit cell and the sensing-side pad are clearly distinguished from each other when viewed from outside the semiconductor device, and therefore it is possible to prevent the wiring member from being erroneously joined to the portion positioned directly over the second unit cell. Therefore, it is possible to reliably maintain a fixed distance between the second unit cell and the wiring member.
In the semiconductor device, the first unit cell and the second unit cell may have mutually same cell structures, respectively.
According to this arrangement, it is possible to estimate a sensing ratio when the current value of the principal current is calculated from a cell ratio between the first unit cell and the second unit cell, and therefore it is possible to easily perform current detection.
In the semiconductor device, the current sensing portion may be formed at only one place in an in-plane direction of the semiconductor layer.
According to this arrangement, it is possible to achieve the space-saving of a surface part of the semiconductor layer.
In the semiconductor device, the interlayer insulating film may have a thickness of 1 μm or more.
According to this arrangement, it is possible to give sufficient shock resistance (for example, wire bonding resistance) to the interlayer insulating film.
The semiconductor device may include a gate-side surface electrode that is disposed on the semiconductor layer and that has a gate-side joint region to which a wiring member is joined, and, in the semiconductor device, the interlayer insulating film may also be disposed at a place directly under the gate-side joint region.
According to this arrangement, it is possible to form in the same process step an interlayer insulating film with which the source portion is covered and an interlayer insulating film with which the gate portion is covered, and therefore it is possible to shorten a manufacturing process.
In the semiconductor device, the interlayer insulating film may include a SiO2 film, and the SiO2 film may contain P (phosphorus) or B (boron).
The SiO2 film is easily produced, and, if the SiO2 film contains P (phosphorus) or B (boron), it is also possible to perform a reflow process after the film is produced. It is possible to easily flatten the interlayer insulating film (SiO2 film) by the reflow process, and therefore it is possible to easily join the wiring member, which possibly affects the heat dissipation capability of the current sensing portion, according to a design plan.
In the semiconductor device, the sensing-side surface electrode may include an electrode having a layered structure in which Ti, TiN, and AlCu are stacked together in this order from the bottom.
According to this arrangement, the use of AlCu for the topmost surface of the sensing-side surface electrode makes it possible to give sufficient shock resistance (for example, wire bonding resistance) to the electrode.
The semiconductor device may include a gate-side surface electrode disposed on the semiconductor layer and a passivation film that has an opening by which a part of the sensing-side surface electrode is exposed as a sensing-side pad and an opening by which a part of the gate-side surface electrode is exposed as a gate-side pad, and in the semiconductor device, the sensing-side pad and the gate-side pad may be each formed so as to have a shape long in a same direction.
According to this arrangement, it is possible to extend and join the wiring members from the same direction to the sensing-side pad and to the gate-side pad, respectively, and therefore it is possible to easily lay the wiring members when a package is assembled.
Preferred embodiments of the present invention will be hereinafter described in detail with reference to the accompanying drawings.
The semiconductor device 1 includes a semiconductor substrate 2 that is an example of a semiconductor layer of the present invention and that is formed in a quadrangular shape in a plan view. The semiconductor substrate 2 has four sides 3A, 3B, 3C, and 3D in a plan view.
A plurality of surface electrode films 4 are formed on the semiconductor substrate 2 so as to be separated from each other. The surface electrode films 4 include a source-side surface electrode 5, a sensing-side surface electrode 6, and a gate-side surface electrode 7. The source-side surface electrode 5 is formed in most regions on the semiconductor substrate 2 (the hatched region of
A passivation film 10 that wholly covers the plurality of surface electrode films 4 with the single film 10 is formed on the semiconductor substrate 2. The passivation film 10 has a plurality of pad openings 11, 12, and 13. The source-side surface electrode 5, the sensing-side surface electrode 6, and the gate-side surface electrode 7 are exposed from the pad openings 11, 12, and 13 as source-side pads 14A and 14B, as a sensing-side pad 15, and as a gate-side pad 16, respectively.
The plurality of source-side pads 14A and 14B are disposed so as to be separated from each other. In
The sensing-side pad 15 is disposed only at one corner portion of the quadrangular semiconductor substrate 2. This makes it possible to achieve space-saving on the semiconductor substrate 2. The sensing-side pad 15 is formed in a shape that is long along the two sides 3B and 3D of the semiconductor substrate 2, and is surrounded by one of the two source-side pads 14B and 14B. In the sensing-side pad 15, a part of its periphery may be surrounded by the source-side pad 14B as shown in
The gate-side pad 16 is disposed in the region 18 between the source-side pads 14B and 14B that face each other. The gate-side pad 16 is formed in a shape that is long along the sides 3B and 3D of the semiconductor substrate 2 in the same way as the sensing-side pad 15.
The gate-side surface electrode 7 additionally includes a gate finger 19 that extends from the gate-side pad 16. The gate finger 19 is covered with the passivation film 10. The gate finger 19 includes a central portion 20 that extends in a direction from the side 3C of the semiconductor substrate 2 toward the side 3A opposite to the side 3C so as to pass through the center of the source-side surface electrode 5 and a peripheral portion 21 that extends along a peripheral edge of the semiconductor substrate 2 (i.e., along the sides 3B, 3C, and 3D in
A source-side wire 22, a sensing-side wire 23, and a gate-side wire 24 are connected to the source-side pads 14A and 14B, to the sensing-side pad 15, and to the gate-side pad 16, respectively. For example, aluminum wires are used as the wires 22 to 24. The aluminum wire is normally joined by not ball bonding but slender wedge bonding. Therefore, if the sensing-side pad 15 and the gate-side pad 16 are each formed in a shape long in the same direction as in
With respect to the diameter of each of the wires 22 to 24, the diameter of the source-side wire 22 may be, for example, 300 μm to 500 μm, and the diameter of the sensing-side wire 23 and that of the gate-side wire 24 may be, for example, 100 μm to 200 μm.
A bonding wire is not necessarily required to be used as a wiring member by which the source-side pads 14A and 14B, the sensing-side pad 15, and the gate-side pad 16 are connected to the outside, and another wiring member, such as a bonding plate or a bonding ribbon, may be used as the wiring member.
In appearance, the sensing-side surface electrode 6 is exposed as the sensing-side pad 15 formed in a substantially rectangular shape in a plan view in a state in which a part (in
The region 25 covered with the passivation film 10 is formed in a rectangular shape in a plan view, and one short side and one long side of the region 25 form an extension portion of the short side and an extension portion of the long side of the sensing-side pad 15, respectively. The region 25 covered therewith is not necessarily required to be formed in a rectangular shape in a plan view, and may be formed in another shape (for example, square, circular, or triangular). Of course, likewise, its position is not necessarily required to be placed at a corner portion of the sensing-side surface electrode 6, and it may be placed, for example, between both ends of a side of the sensing-side surface electrode 6.
A current sensing portion 26 that serves as an aggregation of many sensing-side unit cells 40 (described later) is formed at a place directly under the covered region 25. On the other hand, the current sensing portion 26 is not formed at a place directly under the sensing-side pad 15. In other words, in the present preferred embodiment, the entirety of the current sensing portion 26 is formed so as to avoid being positioned directly under the sensing-side pad 15.
On the other hand, a source portion 27 that serves as an aggregation of many principal-current-side unit cells 34 (described later) is formed around the sensing-side surface electrode 6. The source portion 27 is formed at a place directly under the source-side surface electrode 5, and is formed so as to surround the sensing-side surface electrode 6 in a plan view. The source portion 27 may be formed at a place directly under the entirety of the source-side surface electrode 5 shown in
As shown in
A p− type well 30 (whose concentration is, for example, 1×1014 cm−3 to 1×1019 cm−3) is formed at a surface part of the n− type epitaxial layer 29. The p− type well 30 includes a principal-current-side p− type body well 31, a sensing-side p− type body well 32, and a gate-side p− type well 33. As shown in
The principal-current-side p− type body well 31 includes a cell forming portion 35 that forms a principal-current-side unit cell 34 that is an example of a first unit cell of the present invention and a field forming portion 36 that has a comparatively wide region. In other words, each cell forming portion 35 defines the principal-current-side unit cell 34 that is a minimum unit through which a principal current flows.
As shown in
The field forming portion 36 is formed so as to surround the many cell forming portions 35, and connects adjoining cell forming portions 35 together while straddling between the adjoining cell forming portions 35 at an outer peripheral part of the source portion 27.
The principal-current-side p− type body well 31 additionally includes a connection portion 37 formed at an intersection of lattice regions partitioned by the matrix-shaped cell forming portions 35. This connection portion 37 connects the adjoining cell forming portions 35 together inside the source portion 27.
As thus described, the cell forming portions 35 are electrically connected together at the outer peripheral part and the inner part of the source portion 27 by means of the field forming portion 36 and the connection portion 37. Consequently, the many cell forming portions 35 are held at mutually equal electric potentials.
An n+ type source region 38 is formed in an inner region of the cell forming portion 35, and a p+ type body contact region 39 (whose concentration is, for example, 1×1017 cm−3 to 1×1021 cm−3) is formed in an inner region of the n+ type source region 38 (whose concentration is, for example, 1×1017 cm−3 to 1×1021 cm−3).
The sensing-side p− type body well 32 includes a cell forming portion 41 that forms the sensing-side unit cell that is an example of a second unit cell of the present invention and a field forming portion 42 that has a comparatively wide region. In other words, each cell forming portion 41 defines the sensing-side unit cell 40 that is a minimum unit through which a principal current flows.
As shown in
The field forming portion 42 is formed so as to surround the many cell forming portions 41, and connects adjoining cell forming portions 41 together while straddling between the adjoining cell forming portions 41 at an outer peripheral part of the current sensing portion 26.
The sensing-side p− type body well 32 additionally includes a connection portion 43 formed at an intersection of lattice regions partitioned by the matrix-shaped cell forming portions 41. This connection portion 43 connects the adjoining cell forming portions 41 together inside the current sensing portion 26.
As thus described, the cell forming portions 41 are electrically connected together at the outer peripheral part and the inner part of the current sensing portion 26 by means of the field forming portion 42 and the connection portion 43. Consequently, the many cell forming portions 41 are held at mutually equal electric potentials.
An n+ type source region 44 (whose concentration is, for example, 1×1017 cm−3 to 1×1021 cm−3) is formed in an inner region of the cell forming portion 41, and a p+ type body contact region 45 (whose concentration is, for example, 1×1017 cm−3 to 1×1021 cm−3) is formed in an inner region of the n+ type source region 44.
The field forming portion 42 is formed so as to extend from an outer peripheral part of the cell forming portion 41 to the place positioned directly under the sensing-side pad 15. In the present preferred embodiment, the field forming portion 42 spreads over the entirety of the place directly under the sensing-side pad 15. In other words, in
Additionally, a p+ type region 46 (whose concentration is, for example, 1×1017 cm−3 to 1×1021 cm−3) is formed at a surface part of the field forming portion 42 at the place positioned directly under the sensing-side pad 15. The p+ type region 46 is connected directly to the sensing-side surface electrode 6. The formation of the p+ type region 46 makes it possible to stably keep the electric potential of the place positioned directly under the sensing-side pad 15 at a constant electric potential.
As shown in
A gate insulating film 48 is formed on the semiconductor substrate 2, and a gate electrode 49 is formed on the gate insulating film 48. The gate insulating film 48 is made of, for example, silicon oxide (SiO2), and the gate electrode 49 is made of, for example, polysilicon.
The gate electrode 49 includes a functional portion 52 that is formed along lattice regions partitioned by the matrix-shaped unit cells 34 and 40 and that straddles between adjoining unit cells 34 and 40 in the current sensing portion 26 and the source portion 27. Consequently, the gate electrode 49 faces channel regions 50 and 51 of the unit cells 34 and 40, respectively, with the gate insulating film 48 therebetween. The channel regions 50 and 51 are outer regions of the n+ type source regions 38 and 44 in the cell forming portions 35 and 41 of the p− type body wells 31 and 32, respectively.
As shown in
On the other hand, as shown in
Although the gate insulating film 48 is disposed below the gate electrode 49 in order to secure insulation between the gate electrode 49 and the semiconductor substrate 2, the gate insulating film 48 is also formed at a place directly under the sensing-side pad 15 and at a place directly under the gate-side pad 16 in the present preferred embodiment. As shown in
An interlayer insulating film 54 is formed on the semiconductor substrate 2 so as to cover the gate electrode 49. The interlayer insulating film 54 is made of, for example, silicon oxide (SiO2), and, preferably, contains P (phosphorus) or B (boron). In other words, the interlayer insulating film 54 may be BPSG (Boron Phosphorus Silicon Glass) or may be PSG (Phosphorus Silicon Glass). A SiO2 film is easily produced, and, if this SiO2 film contains P (phosphorus) or B (boron), it is also possible to perform a reflow process after the film is produced. The reflow process makes it possible to easily flatten the interlayer insulating film 54 (SiO2 film), and hence makes it possible to easily join the sensing-side wire 23, which possibly affects the heat dissipation capability of the current sensing portion 26, according to a design plan.
The interlayer insulating film 54 integrally includes a first part 55 with which the gate electrode 49 is covered in the current sensing portion 26 and in the source portion 27, a second part 56 disposed at a place directly under the sensing-side pad 15, and a third part 57 disposed at a place directly under the gate-side pad 16. It is possible to give sufficient shock resistance (for example, wire bonding resistance) to the interlayer insulating film 54 by thickening the interlayer insulating film 54 positioned directly under the sensing-side pad 15 and the interlayer insulating film 54 positioned directly under the gate-side pad 16.
The surface electrode film 4 (the source-side surface electrode 5, the sensing-side surface electrode 6, and the gate-side surface electrode 7) is formed on the interlayer insulating film 54. The source-side surface electrode 5 passes through the interlayer insulating film 54 and through the gate insulating film 48, and is connected to the n+ type source region 38 and to the p+ type body contact region 39. The sensing-side surface electrode 6 passes through the interlayer insulating film 54 and through the gate insulating film 48, and is connected to the n+ type source region 44 and to the p+ type body contact region 45. The gate-side surface electrode 7 (the gate finger 19) passes through the interlayer insulating film 54, and is connected to the gate electrode 49.
The surface electrode film 4 may be an electrode film having a layered structure in which, for example, Ti, TiN, and AlCu are stacked together in this order from the bottom (i.e., from the semiconductor-substrate-2 side). The use of AlCu for the topmost surface of the surface electrode film 4 makes it possible to give more sufficient shock resistance (for example, wire bonding resistance) to the electrode film 4 than the use of Al.
The passivation film 10 is formed on the surface electrode film 4. The passivation film 10 may be made of, for example, silicon nitride (SiN). The pad openings 11 to 13 are formed in the passivation film 10 as described above.
A drain electrode 58 is formed on a rear surface of the semiconductor substrate 2. The drain electrode 58 may be an electrode film having a layered structure in which Ti, Ni, Au, and Ag are stacked together in this order from the semiconductor-substrate-2 side. The drain electrode 58 serves as an electrode shared between the current sensing portion 26 and the source portion 27.
Next, as an example, a method for detecting an electric current in the semiconductor device 1 will be described with reference to
As shown in
A voltage larger than a threshold value is applied to the gate G in a state in which a voltage is applied between the source S and the drain D, and, as a result, an electric current flows between the source S and the drain D, and the semiconductor device 1 reaches an ON state. Consequently, a detection current ISENSE flows through the current sensing portion 26. On the other hand, a principal current IMAIN flows through the source portion 27.
Whether the principal current IMAIN is a short-circuit current is determined by monitoring whether the voltage VSENSE of the detection resistor 59 has exceeded a predetermined threshold value. The resistance RSENSE of the detection resistor 59 is fixed, and therefore the voltage VSENSE becomes higher in proportion to an increase in the detection current ISENSE. Therefore, the fact that the voltage VSENSE has exceeded the threshold value denotes that an excessive detection current ISENSE is flowing, and hence indicates that the current value IMAIN of the principal current calculated based on a sensing ratio between the current sensing portion 26 and the source portion 27 is also in an excessive state.
In the aforementioned detection method, if the principal current IMAIN that has actually flowed and the principal current IMAIN that is calculated by multiplying the detection current ISENSE by the sensing ratio are equal to each other, it is possible to accurately perform the short-circuit detection, and it is possible to shut off the gate voltage at an appropriate timing.
However, as shown in
Therefore, according to the semiconductor device 1, the current sensing portion 26 is disposed so as to avoid being positioned directly under the sensing-side pad 15 as shown in
The use of the semiconductor substrate 2 made of SiC makes it possible to achieve an arrangement in which the current sensing portion 26 is disposed so as to avoid being positioned directly under the sensing-side pad 15 as mentioned above. In other words, in a Si semiconductor device, the amount of flowing current per unit area is small, and therefore a cell area for a somewhat large sensing portion is required to set an appropriate sensing ratio (about 1000 to 2000) having high detection accuracy with respect to a source portion having a large area through which a high current flows, and therefore it is difficult to form it so as to avoid being positioned directly thereunder. On the other hand, in the SiC semiconductor device, the amount of flowing current per unit area is large, and therefore it is possible to secure an appropriate sensing ratio even if the sensing portion is small in cell area with respect to the source portion, and therefore it is possible to form it so as to avoid being positioned directly thereunder.
Additionally, in the present preferred embodiment, the current sensing portion 26 is surrounded by the source portion 27 as shown in
Additionally, in the present preferred embodiment, the entirety of the current sensing portion 26 is covered with the covered region 25 by the passivation film 10 as shown in
Additionally, in the present preferred embodiment, the interlayer insulating film 54 has the second part 56 that is comparatively thick (for example, 1 μm or more) at a place directly under the sensing-side pad 15 as shown in
Next, a method for manufacturing the semiconductor device 1 will be described with reference to
For example, first, the n− type epitaxial layer 29 is formed on the n+ type base substrate 28 by means of epitaxial growth, so that the semiconductor substrate 2 is formed (step S1).
Thereafter, p type impurity ions are selectively implanted into a surface part of the semiconductor substrate 2, and, as a result, the p− type well 30 is formed (step S2).
Thereafter, n type impurity ions are selectively implanted into each of the cell forming portions 35 and 41, and, as a result, the n+ type source regions 38 and 44 are formed (step S3).
Thereafter, p type impurity ions are selectively implanted into the p− type well 30, and, as a result, the p+ type body contact regions 39, 45 and the p+ type regions 46, 47 are formed (step S4).
Thereafter, the gate insulating film 48 is formed on the surface of the semiconductor substrate 2 by means of, for example, thermal oxidation (step S5).
Thereafter, polysilicon is deposited on the semiconductor substrate 2 according to, for example, a CVD method, and the gate electrode 49 is formed thereon by means of patterning (step S6).
Thereafter, the interlayer insulating film 54 is formed on the semiconductor substrate 2 according to, for example, the CVD method (step S7).
Thereafter, a contact hole that passes through the interlayer insulating film 54 and through the gate insulating film 48 is formed, and then the surface electrode film 4 is formed according to, for example, a sputtering method (step S8 and step S9).
Thereafter, the passivation film 10 with which the surface electrode film 4 is covered is formed, and then the pad openings 11, 12, and 13 are formed by means of patterning (step S10 and step S11).
Through these steps, the aforementioned semiconductor device 1 is obtained.
Although the present invention has been described as above, the present invention can be embodied in other modes.
For example, the gate structure of the semiconductor device 1 may be a trench gate structure shown in
Additionally, the current sensing portion 26 is not necessarily required to have the arrangement of
Besides, various design changes can be made within the scope of the subject matter described in the claims.
The present application corresponds to Japanese Patent Application No. 2015-247727 filed with the Japan Patent Office on Dec. 18, 2015, and the entire disclosure of the application is incorporated herein by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-247727 | Dec 2015 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17456785 | Nov 2021 | US |
| Child | 18311780 | US | |
| Parent | 16891957 | Jun 2020 | US |
| Child | 17456785 | US | |
| Parent | 16061967 | Jun 2018 | US |
| Child | 16891957 | US |
