The present invention relates to semiconductor devices, more specifically to the voltage-sustaining layer of semiconductor high-voltage and/or power devices.
The present invention can be summarized by referring the preferred embodiments described as follows.
1. According to a first aspect of this invention, a semiconductor device is provided, comprising a first main surface (the top surface except the electrode(s) in each figure) and a second main surface (the bottom surface except the electrode(s) in each figure), wherein at least a cell is located between the first main surface and the second main surface, wherein the cell has a first device feature region (p+-region 24 in
The voltage-sustaining region includes at least a semiconductor region (n-region 27 in
The semiconductor region and the (I+C)-region contact directly each other;
The semiconductor device comprising at least two electrodes, wherein:
One electrode is contacted directly with a portion or the total of the first main surface; another electrode is contacted directly with a portion or the total of the second main surface; these two electrodes are located outside of the region between the first main surface and the second main surface.
2. Referring to
The ratio of cross sectional area of the (I+C)-region 38 to cross sectional area of the semiconductor keeps constant (e.g.,
3. Referring to
4. Referring to
the first device feature region includes a semiconductor region of the second conductivity type (e.g., p+-region 24 in
the first device feature region further includes a semiconductor region of the second conductivity type ((e.g., p+-region 24 in
5. Referring
The first device feature region (gate insulator region 32, p+-region 29 and n+-region 30) includes a semiconductor region of the second conductivity type (p+-region 29) contacted directly with the semiconductor region of the first conductivity type (n-region 27) of the voltage-sustaining region;
The first device feature region further includes a semiconductor region of the second conductivity type or a conductor (region 23) being contacted directly with the insulator region ((I+C)-region 38) of the voltage-sustaining region.
Several kinds of devices are described as illustrative embodiments of the present invention.
6. Referring to
The first device feature region has a metal (M region 21) being contacted directly with semiconductor region of the first conductivity type (n-region 27) of the voltage-sustaining region ((I+C)-region 38 and n-region 27).
The first device feature region and the second device feature region are contacted with two conductors respectively serving as two electrodes (electrodes A and K, respectively) of the Schottky diode.
The first device feature region further has a semiconductor region of the second conductivity type or a conductor being contacted (M region 21) directly with the insulator region ((I+C)-region 38) of the voltage-sustaining region.
7. Referring to
The first device feature region includes a metal region (M region 21) being contacted directly with semiconductor region of the first conductivity type (n-region 27) of the voltage-sustaining region (n-region 27 and (I+C)-region 38).
The first device feature region further includes a semiconductor region of the second conductivity type (p-region 22) being contacted directly with semiconductor region of the first conductivity type (n-region 27) of the voltage-sustaining region and the metal region.
The first device feature region and the second device feature region are contacted with two conductors respectively serving as two electrodes (anode A and cathode K) of the JBS rectifier or the MPS rectifier.
8. Referring to
The voltage-sustaining region has at least a semiconductor region of the first conductivity type (n-region 27) serving as a collector region of the BJT;
The semiconductor region of the second conductivity type (p-region 57) of the first device feature region serves as a base region of the BJT.
The first device feature region further includes a semiconductor region of the first conductivity type (n+-region 56) surrounded by the base region except the part on the first main surface, serving as an emitter region of the BJT.
A conductor covering on the semiconductor region of the first conductivity type (n+-region 58) of the second device feature region serves as a collector electrode (electrode C), a conductor covering on the base region (p-region 57) serves as a base electrode (electrode B) and a conductor covering on the emitter region (n+-region 56) serves as an emitter electrode (electrode E).
9. Referring to
The voltage-sustaining region has at least a semiconductor region of the first conductivity type (n-region 43 in
The semiconductor region of the second conductivity type (p+-region 29) of the first device feature region serves as a source-body region of the IGFET.
The first device feature region further includes a semiconductor region of the first conductivity type (n+-region 30) surrounded by the source-body region (p+-region 29) except the part on the first main surface, serving as a source region of the IGFET.
An insulator layer (region 32) covers on the first main surface started from a part of the source region, through an area of the source-body region, ended at a part of the semiconductor region of the first conductivity type of the voltage-sustaining region, serving as a gate insulator of the IGFET.
A conductor covering on the drain region (n+-region 28) serves as a drain electrode (electrode D), a conductor contacted with the source-body region (p+-region 29) and the source (n+-region 30) region serves as a source electrode (electrode S) and a conductor covering on the gate insulator (region 32) serves as a gate electrode (electrode G).
10. Referring to
The semiconductor region of the second conductivity type (p+-region 29) of the first device feature region serves as a source-body region of IGFET in the IGBT.
The first device feature region further includes a semiconductor region of the first conductivity type (n+-region 30) surrounded by the source-body region (p+-region 29) except the part on the first main surface, serving as a source region of the IGFET in the IGBT.
An insulator layer (region 32) covers on the first main surface started from a part of the source region, through an area of the source-body region, ended at a part of the semiconductor region of the first conductivity type of the voltage-sustaining region, serving as a gate insulator of the IGFET in the IGBT.
A conductor covering on the anode region serves as an anode electrode (electrode A), a conductor contacted with the source-body region and the source region serves as a cathode electrode (electrode K) and a conductor covering on the gate insulator serves as a gate electrode (electrode G).
11. Referring to
The semiconductor region of the second conductivity type (p-region 53) of the first device feature region serves as a gate region of the thyristor.
The first device feature region further includes a semiconductor region of the first conductivity type (n-region 52) surrounded by the gate region except the part on the first main surface, serving as a cathode region of the thyristor.
A conductor covering on a part of the gate region and the insulator region ((I+C)-region 38) of the voltage-sustaining region serves as a gate electrode (electrode G) of the thyristor.
A conductor covering on the anode region (p+-region 54) serves as an anode electrode (electrode A) and a conductor covering on the cathode region serves as a cathode electrode (electrode K).
Obviously, the present invention can also be used for many other high-voltage devices, e.g. Light Controlled Thyristor (LCT), Gate Turn-Off Thyristor (GTO), MOS Controlled Thyristor (MCT), Junction Field Effect Transistor (JFET), Static-Induction Transistor (SIT), and so on.
It is noted that the present invention can also be used as a junction edge technique for many kinds of devices.
12. Referring to
13. Referring to
14. Referring to
15. Referring to
16. Referring to
It should be noted that the conductive regions (C) in the (I+C)-region of this patent can be constructed by either metal or semiconductor of any type of conductivity or both, The insulator region (I) in the (I+C)-region of this patent not necessary mean only one type of insulator material, it can be different material in different place in the insulator region.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
With reference to those drawings, from the following detailed description, this invention can be understood more clearly as follows.
a) schematically shows a diode by using n-type semiconductor regions and insulator regions containing conductive regions (I+C) to serve as voltage-sustaining region.
b) schematically shows the conductive regions inside the insulator region having various types of shapes.
c) schematically shows the voltage-sustaining region constructed by (I+C)-region and n-type semiconductor, wherein the conductive regions inside the insulator are strip-type.
d) schematically shows the voltage-sustaining region constructed by (I+C)-region and n-type semiconductor, wherein the conductive regions inside the insulator are rectangular-type.
e) schematically shows the voltage-sustaining region constructed by (I+C)-region and n-type semiconductor, wherein the conductive regions inside the insulator are U-shape.
f) schematically shows the voltage-sustaining region constructed by (I+C)-region and n-type semiconductor, wherein the conductive regions inside the insulator are granular.
a) schematically shows the voltage-sustaining region constructed by (I+C)-region and p-type semiconductor region.
b) schematically shows the voltage-sustaining region constructed by n-type semiconductor region, p-type semiconductor region and (I+C)-regions, wherein the (I+C)-region is located between p-type semiconductor regions.
c) schematically shows the voltage-sustaining region constructed by n-type semiconductor region, p-type semiconductor region and (I+C)-regions, wherein the (I+C)-region is located between p-type semiconductor region and n-type semiconductor region.
a)-3(d), collectively referred to herein as
a) is a schematic diagram that the widths of (I+C)-region and n-type semiconductor region are not necessary equal.
b) is a schematic diagram that the thickness of n-type semiconductor region is larger than that of the (I+C)-region, and the insulator does not reach the n+-region 25 of the second device feature region.
c) is a schematic diagram that the thickness of the (I+C)-region is larger than that of n-type semiconductor region, wherein the bottom of insulator, lower than that of n-region 27, has extended into the n+-region 25 of second device feature region.
d) is another schematic diagram that the thickness of the (I+C)-region is larger than that of n-type semiconductor region, wherein the top of insulator is higher than that of n-region 27.
a)-4(h), collectively referred to as
a) schematically shows an interdigitated pattern;
b) schematically shows a pattern formed by square cells, wherein semiconductor regions are all mutually connected;
c) schematically shows a pattern formed by square cells, wherein the (I+C)-regions are mutually connected;
d) schematically shows a pattern formed by rectangular cells, wherein semiconductor regions are all mutually connected;
e) schematically shows a pattern formed by rectangular cells wherein the (I+C)-regions are mutually connected;
f) schematically shows a mosaic square pattern;
g) schematically shows a hexagonal close-packed pattern, wherein semiconductor regions are all mutually connected;
h) schematically shows a hexagonal close-packed pattern, wherein the (I+C)-regions are all mutually connected.
a)-5(i), collectively referred to as
a) schematically shows an interdigitated pattern;
b) schematically shows a pattern formed by square cells, wherein n-type semiconductor regions are all mutually connected;
c) schematically shows a pattern formed by square cells, wherein p-type semiconductor regions are all mutually connected;
d) schematically shows a pattern formed by rectangular cells, wherein n-type semiconductor regions are all mutually connected;
e) schematically shows a pattern formed by rectangular cells, wherein p-type semiconductor regions are all mutually connected;
f) schematically shows a mosaic square pattern;
g) schematically shows another mosaic square pattern;
h) schematically shows a hexagonal close-packed pattern, wherein n-type semiconductor regions are all mutually connected;
i) schematically shows a hexagonal close-packed pattern, wherein p-type semiconductor regions are all mutually connected.
a)-8(b), collectively referred to as
a) schematically shows a structure of high-voltage Merged P-i-N/Schottky using the voltage-sustaining layer constructed by semiconductor and (I+C)-region;
b) schematically shows another structure of high-voltage Junction Barrier Controlled Schottky using the voltage-sustaining layer constructed by semiconductor and (I+C)-region.
a)-(d), collectively referred to herein as
a) schematically illustrates that an epitaxial layer n-region has been grown on n+-substrate and p+-29 and n+-30 as well as insulator layer 32 have been done;
b) schematically illustrates that a groove with a depth close to the thickness of epitaxial layer is etched in the epitaxial layer;
c) schematically illustrates that the grooves are filled with the (I+C)-region;
d) schematically illustrates that the electrodes are formed;
a)-(c), collectively referred to herein as
a) schematically shows an application of using the (I+C)-region to implement the terminal cell of a p-n junction diode;
b) schematically shows another application of using the (I+C)-region to implement the terminal cell of a p-n junction diode, wherein the insulator is contacted directly with anode electrode A at the first main surface;
c) schematically shows still another application of using the (I+C)-region as junction edge technique, wherein the (I+C)-region is not necessary to be covered by conductor but it covers on a considerable part of p-region;
Various exemplary embodiments of the present invention will now be described in detail with reference to the drawings. It should be noted that the relative arrangement of the components and the steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.
Meanwhile, it should be appreciated that, for the convenience of description, various parts shown in those drawings are not necessarily drawn on scale.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Those techniques and methods as known by one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all of the examples illustrated and discussed herein, any specific values should be interpreted to be illustrative only and non-limiting. Thus, other examples of the exemplary embodiments could have different values.
Notice that similar reference numerals and letters refer to similar items in the following figures, and thus once an item is defined in one figure, it is possible that it need not be further discussed for following figures.
In the present invention, a semiconductor device with voltage-sustaining region constructed by semiconductor and insulator containing conductive region(s) called as (I+C)-region(s), is proposed.
It should be mentioned here that the conductive region(s) inside the (I+C)-region are not necessary to be distributed very evenly, and the size, the shape(s) and the material type(s) of the conductive region(s) inside the (I+C)-region is(are) not restricted.
It should be noted that the conductive regions (C) in the (I+C)-region of this patent can be constructed by either metal or semiconductor of any type of conductivity or both. The metal in the (I+C)-region of this patent is not necessary mean only one type of material, it can be different material in different place in the (I+C)-region. The insulator region (I) in the (I+C)-region of this patent not necessary mean only one type of insulator material, it can be different material in different place in the insulator region.
It should also be mentioned here that the insulator used in the present invention for voltage-sustaining region is not limited to a material with only one single chemical component inside of it.
The technology schemes of the present invention will be described and illustrated in detail with reference to the drawings, wherein the illustrative embodiments of the present invention will be demonstrated in the following. In all of the figures, the same number means the same component or element. The solid bold lines represent the conductor for electrode contacts, S stands for the semiconductor regions and (I+C) stands for the insulator containing the conductive region(s). There is a first device feature region and a second device feature region respectively contacted with the opposite sides of the voltage-sustaining region implemented by using this method.
c) schematically shows a diode by using n-type semiconductor regions 27 and (I+C) regions to serve as voltage-sustaining region, wherein the conductive region(s) in the insulator is strip-type.
d) schematically shows a diode by using n-type semiconductor regions 27 and (I+C) regions to serve as voltage-sustaining region, wherein the conductive region(s) in the insulator is rectangular.
e) schematically shows a diode by using n-type semiconductor regions 27 and (I+C) regions to serve as voltage-sustaining region, wherein the conductive region(s) in the insulator is U-shaped.
f) schematically shows a diode by using n-type semiconductor regions 27 and (I+C) regions to serve as voltage-sustaining region, wherein the conductive region(s) in the insulator is granular.
Obviously, the n-type semiconductor regions in
It should be noted that in the voltage-sustaining region, it is not necessary for the insulators containing conductive region(s) to have the same width and thickness with semiconductor regions. In
There are many structure patterns for the arrangement of the insulators containing conductive region(s) and semiconductor regions.
If the semiconductor mentioned above is silicon, it can be separated with (I+C)-region(s) by a thin silicon dioxide layer 40 between them, as shown in
A Schottky diode can also be implemented by replacing the p+-region 24 in
The present invention can also be used to implement high-voltage Junction Barrier Controlled Schottky (JBS) rectifier or pinch rectifier. Similarly, it can also be used to implement high-voltage Merged P-i-N/Schottky (MPS) rectifier. All of their structures can be schematically shown as
The first device feature region of the devices shown in
The present invention can also be used to implement high-voltage Bipolar Junction Transistor (BJT), as shown in
In the present invention, it is not necessary for the (I+C)-region(s) of the voltage-sustaining region to have the same depth with semiconductor. For example, in
The technique in the present invention can also be used to implement the voltage-sustaining region of thyristor and a specific application is shown in
Obviously, the present invention can also be used for many other high-voltage devices, e.g. Light Controlled Thyristor (LCT), Gate Turn-Off Thyristor (GTO), MOS Controlled Thyristor (MCT), Junction Field Effect Transistor (JFET), Static-Induction Transistor (SIT), and so on.
The present invention can be used not only for the operation region of various kinds of devices, but also for being used as a junction edge technique for many kinds of devices.
c) shows another application of using the (I+C)-region(s) as the junction edge technique. Herein, the insulator 38 containing conductive region(s) is not necessary to be covered by conductor but it covers on a considerable part of p-region 50.
Obviously, all of the n-regions and p-regions in the above examples can be exchanged each other, the device then changes to a device of a conductivity of opposite type.
It should be understood that various other examples of application, which should be included in the scope of the present invention as defined in the claims, will be apparent to those skilled in the art.
Thus, the semiconductor device of this invention has been described in detail. Some well-known details are not described herein in order to prevent obscuring the concept of this invention. From the above description, those skilled in the art may fully understand how to implement the technical solutions disclosed herein.
Although some specific embodiments of the present invention have been demonstrated in detail with examples, it should be understood by a person skilled in the art that the above examples are only intended to be illustrative but not to limit the scope of the present invention. It should be understood by a person skilled in the art that the above embodiments can be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the attached claims.
Number | Date | Country | Kind |
---|---|---|---|
201110387593.8 | Nov 2011 | CN | national |
This application is a continuation-in-part of U.S. patent application Ser. No. 13/689,146 filed on Nov. 29, 2012, which claims the benefit of Chinese patent application Serial No. 201110387593.8 filed on Nov. 30, 2011, both of which are incorporated herein by reference in their entirety.
Number | Date | Country | |
---|---|---|---|
Parent | 13689146 | Nov 2012 | US |
Child | 14796206 | US |