The present application claims priority to Taiwan application No. 112106795, filed on Feb. 23, 2023, the content of which is hereby incorporated by reference in its entirety.
The present invention relates to a semiconductor device, and more particularly to a semiconductor device without resistance trimming pads.
A conventional resistance trimming process is described herein. With reference to
Multiple resistance trimming pads 42, two testing pads 43, multiple fusible wires 44 and other pads (not shown in the drawings) for outward electrical connection are arranged on the surface of each semiconductor device 41. Each semiconductor device 41 at least has a fundamental resistor and multiple trimming resistors for implementing the purpose of impedance matching. It is understandable that forming a resistor layout in the wafer 40 by semiconductor processes is the common knowledge in the art. For conciseness in description, with reference to an example shown in
On the surface of each semiconductor device 41, one fusible wire 44 is connected between two adjacent resistance trimming pads 42. One testing pad 43 is connected to the other testing pad 43 through the fundamental resistor RB, the fusible wires 44, and the resistance trimming pads 42. The resistance trimming resistors RT are respectively connected to the fusible wires 44 in parallel. Under the foregoing connection state, the trimming resistors RT are electrically connected to the fundamental resistor RB, and are respectively short-circuited by the fusible wires 44.
In order to measure and trim the resistance property of each semiconductor device 41, the wafer 40 can be mounted to a tester. The tester has a probe card with multiple probes. The probes respectively contact the testing pads 43 and the resistance trimming pads 42 on the surface of each semiconductor device 41. Because the trimming resistors RT are respectively short-circuited by the fusible wires 44, the measured resistance from the two testing pads 43 of each semiconductor device 41 is equivalent to the resistance of the fundamental resistor RB. At that time, if the measured resistance of each semiconductor device 41 is too low to meet the impedance matching, the tester will apply a current through two adjacent resistance trimming pads 42 of each corresponding semiconductor device 41. The current will directly flow through the corresponding fusible wire 44 which is connected between such two adjacent resistance trimming pads 42. For the fusible wire 44, the current is as a short-circuit current. The heat caused by the current passing through the fusible wire 44 will fuse and interrupt the fusible wire 44. Then, the wafer 40 will be sawed along the X-axis scribe lines L1 and the Y-axis scribe lines L2. The semiconductor devices 41 will be separated from each other, and each semiconductor device 41 becomes a die.
With reference to
After the resistance trimming process as mentioned above, only when it is confirmed that the resistance of each semiconductor device 41 (such as the measured resistance from the two testing pads 43) is fixed, and there is no need to trim the resistance any more, the wafer 40 can be sawed to singulate the semiconductor devices 41. Namely, when the resistance trimming process is finished, the resistance trimming pads 42 do not have a substantive effect. However, the resistance trimming pads 42 still remain on the surface of each semiconductor device 42 and form a part of each semiconductor device 41. So the resistance trimming pads 42 occupying the surface area of each semiconductor device 41 will cause some problems. For example, a part of the surface area of each semiconductor device 41 is occupied by the resistance trimming pads 42, such that the entire surface area of each semiconductor device 41 cannot be reduced effectively. And accordingly, the space utilization of the wafer 40 is limited.
An objective of the present invention is to provide a semiconductor device without the resistance trimming pads, to overcome the problems caused by the resistance trimming pads remaining on the conventional semiconductor device.
The semiconductor device of the present invention has a device body, a fundamental resistor, and at least one trimming resistor. The device body has a surface with two testing pads and without resistance trimming pads. The fundamental resistor is formed in the device body. The at least one trimming resistor is formed in the device body and connected to the fundamental resistor in series between the two testing pads. Residuals of at least one fusible wire that has been fused are connected to the at least one trimming resistor.
The semiconductor device of the present invention never includes the resistance trimming pads which occupy the space. Compared with the prior art, the surface area of the semiconductor device of the present invention can be effectively reduced, such that the die of the semiconductor device of the present invention can be downsized. Besides, from the perspective on a wafer, because each semiconductor device is downsized, the surface of the wafer has a relatively enlarged area available for use. So the space utilization of the wafer is much more flexible.
The structure as well as the resistance trimming process of the semiconductor device of the present invention are described below. Please note that the contents in the drawings, such as component sizes, shapes, ratios, and so on, are schematically illustrated for reference only.
STEP S01: A wafer is provided. With reference to
It is understandable that the entire integrated circuit of each semiconductor device 11 is made based on a designated specification and functions to have a resistor layout. The resistor layout may implement a purpose of impedance matching as an example. The present invention focuses on the resistor layout.
Forming the resistor layout in the wafer 10 by semiconductor processes is the common knowledge in the art. For example, one or multiple resistors can be formed in one layer of each semiconductor device 11 of the wafer 10, or multiple resistors can be respectively formed in multiple layers of each semiconductor device 11 of the wafer 10. With reference to
In an embodiment of the present invention, with reference to
With reference to
In each semiconductor device 11, the fundamental resistor RB and the at least one fusible wire 14 are electrically connected in series between the two testing pads 13. The at least one fusible wire 14 is electrically connected between two of the resistance trimming pads 12, and electrically connected to the at least one trimming resistor RT in parallel. In a first embodiment of the present invention, as shown in
STEP S02: This step is to measure the resistance of each semiconductor device 11 via the two testing pads 13. In an embodiment of the present invention, the wafer 10 can be mounted to a tester. The tester has a probe card with multiple probes. A part of the probes may contact the testing pads 13 of the semiconductor devices 11.
STEP S03: This step is to apply a current through two of the resistance trimming pads 12 of each corresponding semiconductor device 11 according to the measured resistance of each semiconductor device 11. In an embodiment of the present invention,
As a result, the fundamental resistor RB of each semiconductor device 11 is electrically connected to one of the trimming resistors RT in series. With reference to the equivalent circuit as shown in
STEP S04: A singulation process is to singulate the semiconductor devices 11 of the wafer 10 by sawing the wafer 10 along the X-axis scribe lines L1 and the Y-axis scribe lines L2, such that each semiconductor device 11 becomes a die. Because the resistance trimming pads 12 are arranged on the X-axis scribe lines L1 and/or the Y-axis scribe lines L2, the resistance trimming pads 12 are removed while sawing. Hence, with reference to
In STEP S01 of the foregoing first embodiment, each semiconductor device 11 comprises multiple trimming resistors RT and multiple fusible wires 14 as an example. So in STEP S03, the measured resistance of each semiconductor device 11 can be increased step by step by selecting one or more than one of the fusible wires 14 to fuse and interrupt. In a second embodiment of the present invention, with reference to
In summary of the foregoing resistance trimming process, with reference to
The device body 110 has a surface with two testing pads 13. It is understandable that there are also other pads (not shown in the drawings) arranged on the surface of the device body 110 for outward electrical connection. The fundamental resistor RB and the at least one trimming resistor RT are formed in the device body 110 and adapted to implement the impedance matching. The at least one trimming resistor RT and the fundamental resistor RB are connected in series and between the two testing pads 13. With reference to
As the first embodiment of the resistance trimming process as mentioned above, with reference to
In conclusion, the present invention has the following effects:
1. The resistance trimming pads 12 are removed while sawing the wafer 10 in the singulation process. With reference to
2. As the above-mentioned embodiment, each semiconductor device 11 in the wafer 10 may comprise multiple trimming resistor RT and multiple fusible wires 14. So in STEP S03, the measured resistance from the two testing pads 13 of each semiconductor device 11 can be increased step by step by selecting one or some of the fusible wires 14 to fuse and interrupt. By doing so, the resistance trimming mechanism of the present invention is quite flexible.
3. In the present invention, when the wafer 10 is mounted to the tester, the probes of the tester respectively contact the testing pads 13 and the resistance trimming pads 12 of the semiconductor devices 11 at the same time. So the measurement and trimming for the resistance of the semiconductor devices 11 can be performed collaboratively to have high efficiency.
Even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only. Changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
Number | Date | Country | Kind |
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112106795 | Feb 2023 | TW | national |