SEMICONDUCTOR DEVICE

Abstract

A plurality of floating gates are formed on a principal surface of a semiconductor substrate that constitutes a nonvolatile semiconductor memory device through a first gate dielectric film. An auxiliary gate formed on the principal surface of the semiconductor substrate through a third gate dielectric film is formed on one adjacent side of the floating gates. A groove is formed on the other adjacent side of the floating gate, and an n-type diffusion layer is formed on a bottom side of the groove. A data line of the nonvolatile semiconductor memory device is constituted by an inversion layer formed on the principal surface of the semiconductor substrate to be opposed to an auxiliary gate by applying desired voltage to the auxiliary gate, and the n-type diffusion layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a principal part plan view showing a configuration of a memory cell array of a nonvolatile semiconductor memory device according to the first embodiment of the present invention;

FIG. 2 is a principal part cross-sectional view of a semiconductor substrate taken along a line A-A′ shown in FIG. 1;

FIG. 3 is a principal part cross-sectional view of a semiconductor substrate taken along a line B-B′ shown in FIG. 1;

FIG. 4 is a principal part cross-sectional view of a semiconductor substrate taken along a line C-C′ shown in FIG. 1;

FIG. 5 is a principal part cross-sectional view of a semiconductor substrate taken along a line D-D′ shown in FIG. 1;

FIG. 6 is a principal-part cross-sectional view of a semiconductor substrate taken along a line E-E′ shown in FIG. 1;

FIG. 7 is an equivalent circuit diagram of a principal part of a memory circuit for explaining a data read operation performed by the nonvolatile semiconductor memory device shown in FIG. 1;

FIG. 8 is an equivalent circuit diagram of a principal part of a memory circuit for explaining a data write operation performed by the nonvolatile semiconductor memory device shown in FIG. 1;

FIG. 9 is a cross-sectional view of a principal part of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device shown in FIG. 1;

FIG. 10 is a plan view of a principal part of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 9;

FIG. 11 is a cross-sectional view of a principal part of the semiconductor substrate taken along the line B-B′ of FIG. 10;

FIG. 12 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIGS. 10 and 11;

FIG. 13 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 12;

FIG. 14 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 13;

FIG. 15 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 14;

FIG. 16 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 15;

FIG. 17 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 16;

FIG. 18 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 17;

FIG. 19 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 18;

FIG. 20 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 19;

FIG. 21 is a principal part plan view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 19;

FIG. 22 is a principal part cross-sectional view of the semiconductor substrate taken along a line F-F′ of FIG. 21;

FIG. 23 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIGS. 21 and 22;

FIG. 24 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 23;

FIG. 25 is a principal part cross-sectional view of the semiconductor substrate taken along a line corresponding to the line C-C′ of FIG. 1 after the same step as that shown in FIG. 24;

FIG. 26 is a principal part cross-sectional view of a semiconductor substrate showing a modification of a step of manufacturing the nonvolatile semiconductor memory device;

FIG. 27 is a principal part cross-sectional view of the semiconductor substrate taken along a line corresponding to the line C-C′ of FIG. 1 after the same step as that shown in FIG. 26;

FIG. 28 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIGS. 24 and 25;

FIG. 29 is a principal part cross-sectional view of the semiconductor substrate taken along a line corresponding to the line C-C′ of FIG. 1 after the same step as that shown in FIG. 28;

FIG. 30 is a principal part cross-sectional view of a semiconductor substrate showing a modification of a step of manufacturing the nonvolatile semiconductor memory device;

FIG. 31 is a graph showing comparison between roll-off characteristics of the nonvolatile semiconductor memory device shown in FIG. 1 and those of a technique studied by the inventors of the present invention;

FIG. 32 is a principal part plan view showing a configuration of a memory array of a nonvolatile semiconductor memory device according to the second embodiment of the present invention;

FIG. 33 is a principal part cross-sectional view of a semiconductor substrate taken along a line G-G′ of FIG. 32;

FIG. 34 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device shown in FIG. 32;

FIG. 35 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 34;

FIG. 36 is an equivalent circuit of a principal part of a memory circuit for explaining a data read operation performed by the nonvolatile semiconductor memory device shown in FIG. 32;

FIG. 37 is an equivalent circuit of a principal part of a memory circuit for explaining a data write operation performed by the nonvolatile semiconductor memory device shown in FIG. 32;

FIG. 38 is an equivalent circuit diagram of a principal part of the memory circuit in the nonvolatile semiconductor memory device according to the second embodiment;

FIG. 39 is a waveform view showing an example of waveforms of voltages applied to respective electrodes shown in FIG. 38;

FIG. 40 is a principal part plan view showing a configuration of a memory cell array of a nonvolatile semiconductor memory device according to a third embodiment of the present invention;

FIG. 41 is a principal part cross-sectional view taken along a line H-H′ of FIG. 40;

FIG. 42 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device shown in FIG. 40;

FIG. 43 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 42;

FIG. 44 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 43;

FIG. 45 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 44;

FIG. 46 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 45;

FIG. 47 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 46;

FIG. 48 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 47;

FIG. 49 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 48;

FIG. 50 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 49;

FIG. 51 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 50;

FIG. 52 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 51;

FIG. 53 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 52;

FIG. 54 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 53;

FIG. 55 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 54;

FIG. 56 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 55;

FIG. 57 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 56;

FIG. 58 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 57;

FIG. 59 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 58;

FIG. 60 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 59;

FIG. 61 is a principal part plan view showing a configuration of a memory cell array of a nonvolatile semiconductor memory device according to the fourth embodiment of the present invention;

FIG. 62 is a principal part cross-sectional view taken along a line I-I′ of FIG. 61;

FIG. 63 is a principal part cross-sectional view taken along a line J-J′ of FIG. 61;

FIG. 64 is an equivalent circuit diagram of a principal part of a memory circuit for explaining a data read operation performed by the nonvolatile semiconductor memory device shown in FIG. 61;

FIG. 65 is an equivalent circuit diagram of a principal part of a memory circuit for explaining a data write operation performed by the nonvolatile semiconductor memory device shown in FIG. 61;

FIG. 66 is an equivalent circuit diagram of a principal part of a memory circuit for explaining a data erasure operation performed by the nonvolatile semiconductor memory device shown in FIG. 61;

FIG. 67 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device shown in FIG. 61;

FIG. 68 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 67;

FIG. 69 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 68;

FIG. 70 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 69;

FIG. 71 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 70;

FIG. 72 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 71;

FIG. 73 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 72;

FIG. 74 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 73;

FIG. 75 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 74;

FIG. 76 is a principal part cross-sectional view of the semiconductor substrate during a step of manufacturing the nonvolatile semiconductor memory device subsequent to FIG. 75; and

FIG. 77 is a principal part cross-sectional view of the semiconductor substrate showing a modification of a step of manufacturing the nonvolatile semiconductor memory device.

Claims

1. A semiconductor device comprising a memory cell, constituted by a field effect transistor, the field-effect transistor including: a first gate electrode formed on a semiconductor substrate of a first electric conduction type through a first gate dielectric film;a second gate electrode formed on the first gate electrode through a second gate dielectric film;a third gate electrode formed on the semiconductor substrate through a third gate dielectric film; anda diffusion layer of a second electric conduction type formed on a bottom side of a groove formed in the semiconductor substrate,wherein the second gate electrode constitutes a word line, andthe diffusion layer constitutes a data line.

2. The semiconductor device according to claim 1, wherein the data line constituted by the diffusion layer is formed in a direction orthogonal to the word line.

3. The semiconductor device according to claim 1, wherein an inversion layer formed on the semiconductor substrate at a time of applying a voltage to the third gate electrode constitutes the data line.

4. The semiconductor device according to claim 2, wherein when information is written from the memory cell, the data line constituted by the diffusion layer is used, andwhen the information is read to the memory cell, the data line constituted by the inversion layer and the diffusion layer is used, the inversion layer being formed on the semiconductor substrate by applying a voltage to the third gate electrode.

5. A semiconductor device comprising a memory cell, constituted by a field-effect transistor, the field-effect transistor including: a first gate electrode formed on a semiconductor substrate of a first electric conduction type through a first gate dielectric film;a second gate electrode formed on the first gate electrode through a second gate dielectric film; anda diffusion layer of a second electric conduction type formed on the semiconductor substrate,wherein the second gate electrode constitutes a word line,the diffusion layer constitutes a data line, anda first electrode is formed on the data line constituted by the diffusion layer through a dielectric film.

6. The semiconductor device according to claim 5, wherein a potential of the data line constituted by the diffusion layer is controlled by controlling a potential of the first electrode.

7. A semiconductor device including a memory cell, constituted by a field-effect transistor, the field-effect transistor comprising: a first gate electrode formed on a semiconductor substrate of a first electric conduction type through a first gate dielectric film;a second gate electrode formed on the first gate electrode through a second gate dielectric film;a third gate electrode formed on the semiconductor substrate through a third gate dielectric film; anda diffusion layer of a second electric conduction type formed on the semiconductor substrate,wherein the first gate electrode and the third gate electrode are not present on a same plane,the second gate electrode constitutes a word line, the diffusion layer constitutes a data line, anda first electrode is formed on the data line constituted by the diffusion layer through a dielectric film.

8. A semiconductor device comprising a plurality of memory cells each constituted by a field-effect transistor, the field-effect transistor including: a first gate electrode formed on a semiconductor substrate of a first electric conduction type through a first gate dielectric film;a second gate electrode formed on the first gate electrode through a second gate dielectric film;a groove formed in the semiconductor substrate; anda diffusion layer of a second conduction type formed on a bottom side of the groove on the semiconductor substrate,wherein the second gate electrode constitutes a word line, andthe diffusion layer constitutes a data line.

9. The semiconductor device according to claim 8, wherein the plurality of memory cells arranged along the data line are connected in series.

10. The semiconductor device according to claim 9, wherein an isolation is provided between adjacent memory cells of the plurality of memory cells arranged along the word line on the semiconductor substrate.

11. A semiconductor device comprising: (a) a semiconductor substrate including a principal surface and a rear surface opposite to each other in a thickness direction;(b) a plurality of first gate electrodes formed on the principal surface of the semiconductor substrate through a first gate dielectric film;(c) a plurality of word lines extending in a first direction along the principal surface of the semiconductor substrate, and arranged to be aligned to one another in a second direction crossing the first direction;(d) a plurality of second gate electrodes formed by parts of the plurality of word lines, and formed in portions in which the plurality of word lines are overlapped with the plurality of first gate electrodes so as to be insulated from the plurality of first gate electrodes by a second gate dielectric film;(e) a plurality of third gate electrodes arranged in every other area among the adjacent electrodes of the plurality of first gate electrodes aligned in the first direction, formed to extend in the second direction along the principal surface of the semiconductor substrate, and formed on the principal surface of the semiconductor substrate through a third gate dielectric film; and(f) a diffusion layer formed in areas where the third electrodes are not arranged out of a plurality of areas among the adjacent first gate electrodes aligned in the first direction on the principal surface of the semiconductor substrate,wherein the diffusion layer is formed at a deeper position than a position of the principal surface of the semiconductor substrate, to which the third gate electrodes are opposed, on the semiconductor substrate.

12. The semiconductor device according to claim 11, wherein the diffusion layer is formed on a bottom side of a groove formed in areas where the third electrodes are not arranged out of plurality of areas among the adjacent first gate electrodes aligned in the first direction on the principal surface of the semiconductor substrate.

13. A semiconductor device comprising: (a) a semiconductor substrate including a principal surface and a rear surface opposite to each other in a thickness direction;(b) a plurality of first gate electrodes formed on the principal surface of the semiconductor substrate through a first gate dielectric film;(c) a plurality of word lines extending in a first direction along the principal surface of the semiconductor substrate, and arranged to be aligned to one another in a second direction crossing the first direction;(d) a plurality of second gate electrodes formed by parts of the plurality of word lines, and formed in portions in which the plurality of word lines are overlapped with the plurality of first gate electrodes so as to be insulated from the plurality of first gate electrodes by a second gate dielectric film;(e) an isolating unit arranged between adjacent of first gate electrodes of the plurality of first gate electrodes aligned in the first direction; and(f) a plurality of diffusion layers each formed in area among the adjacent first gate electrodes aligned in the second direction on the principal surface of the semiconductor substrate,wherein the adjacent diffusion layers in the second direction among the plurality of diffusion layers differ from each other in a position in a depth direction of the semiconductor substrate.

14. The semiconductor device according to claim 13, wherein one of adjacent diffusion layers among the plurality of diffusion layers aligned in the second direction is formed on the principal surface of the semiconductor substrate, and other one of the adjacent diffusion layers is formed on a bottom side of a groove formed in the principal surface of the semiconductor substrate.