Patent Application
20240128248
The disclosure of Japanese Patent Application No. 2022-163944 filed on Oct. 12, 2022, including the specification, drawings and abstract is incorporated herein by reference in its entirety.
The present disclosure relates to a semiconductor device and, more particularly, to a technique applicable to a semiconductor device capable of transmitting signals between different potentials using a pair of inductors coupled inductively.
There are disclosed techniques listed below.
Patent Document 1 discloses a technique capable of increasing cross-sectional areas of coils without preventing miniaturization in order to reduce a series resistance which occupies most of the parasitic resistance components of the coils configuring the transformer.
For example, a transformer (digital isolator) that enables contactless signal transmission using a pair of inductors coupled inductively is known. Since this transformer allows signal transmission in a contactless state, the electrical noise from one circuit can be suppressed from adversely affecting the other circuit. In addition, in the transformer configured as described above, improving the breakdown voltage so as to enable contactless signal transmission between circuits having different potentials from each other.
In one embodiment, a semiconductor device includes an insulating substrate, and a first inductor formed on the insulating substrate and being a component of a transformer that performs contactless communication between different potentials. Here, the first inductor is configured to be applied with a first potential. The first inductor is formed so that the first inductor can be magnetically coupled with a second inductor configured to be applied with a second potential different from the first potential.
According to one embodiment, the reliability of the semiconductor device can be improved.
In all the drawings for explaining the embodiments, the same members are denoted by the same reference numerals in principle, and repetitive descriptions thereof are omitted. Note that even plan view may be hatched for the sake of clarity. CIRCUIT CONFIGURATION
As shown in
A transmitting circuit TX1 and a receiving circuit RX1 transmits a control signal outputted from the control circuit CC to the drive circuit DR. On the other hand, a transmitting circuit TX2 and a receiving circuit RX2 transmits a signal outputted from the drive circuit DR to the control circuit CC.
The control circuit CC has a function of controlling the drive circuit DR. The drive circuit DR operates the inverter INV that controls the load circuit LOD, based on control from the control circuit CC.
The control circuit CC is supplied with a power supply potential VCC1, and the control circuit CC is grounded by the ground potential GND1. On the other hand, the inverter INV is supplied with a power supply potential VCC2, and the inverter INV is grounded by the ground potential GND2. In this case, for example, the power supply potential VCC1 is smaller than the power supply potential VCC2 supplied to the inverter INV. In other words, the power supply potential VCC2 supplied to the inverter INV is greater than the power supply potential VCC1.
The transformer TR1 formed of a coil CL1a and a coil CL1b inductively (magnetically) coupled to each other is interposed between the transmitting circuit TX1 and the receiving circuit RX1. Thus, a signal can be transmitted from the transmitting circuit TX1 to the receiving circuit RX1 via the transformer TR1. Consequently, the drive circuit DR can receive the control signal outputted from the control circuit CC via the transformer TR1.
As described above, the transformer TR1 electrically isolated using the inductive coupling enables transmitting the control signal from the control circuit CC to the drive circuit DR while suppressing the transfer of the electric noise from the control circuit CC to the drive circuit DR. Therefore, a malfunction of the drive circuit DR caused by the superimposition of the electric noise on the control signal can be suppresses. Thus, the operation reliability of the semiconductor device can be improved.
The coil CL1a and the coil CL1b configuring the transformer TR1 each function as an inductor. The transformer TR1 function as a magnetically coupled element formed of the coil CL1a and the coil CL1b inductively coupled to each other.
Similarly, the transformer TR2 formed of a coil CL2b and a coil CL2a inductively coupled to each other is interposed between the transmitting circuit TX2 and the receiving circuit RX2. Thus, a signal can be transmitted from the transmitting circuit TX2 to the receiving circuit RX2 via the transformer TR2. Consequently, the control circuit CC can receive the signal outputted from the drive circuit DR via the transformer TR2.
As described above, the transformer TR2 electrically isolated using the inductive coupling enables transmitting the signal from the drive circuit DR to the control circuit CC while suppressing the transfer of the electric noise from the drive circuit DR to the control circuit CC. Therefore, a malfunction of the control circuit CC caused by the superimposition of the electric noise on the signal can be suppresses. Thus, the operation reliability of the semiconductor device can be improved.
The transformer TR1 is configured by the coil CL1a and the coil CL1b, and the coil CL1a and the coil CL1b are not connected by conductors but are magnetically coupled. Therefore, when a current flows in the coil CL1a, an induced electromotive force is generated in the coil CL1b in accordance with a change in the current, so that an induced current flows in the coil CL1b. In this case, the coil CL1a is a primary coil, and the coil CL1b is a secondary coil. As described above, the transformer TR1 utilizes the electromagnetic induction phenomenon occurring between the coil CL1a and the coil CL1b. That is, as a result of transmitting a signal from the transmitting circuit TX1 to the coil CL1a of the transformer TR1 to flow a current, the receiving circuit RX1 detects an induced current generated in the coil CL1b of the transformer TR1, so that the receiving circuit RX1 can receive a signal corresponding to the control signal outputted from the transmitting circuit TX1.
Similarly, the transformer TR2 is configured by the coil CL2a and the coil CL2b, and the coil CL2a and the coil CL2b are not connected by conductors but are magnetically coupled. Therefore, when a current flows in the coil CL2b, an induced electromotive force is generated in the coil CL2a in accordance with a change in the current, so that an induced current flows in the coil CL2a. As described above, as a result of transmitting a signal from the transmitting circuit TX2 to the coil CL2b of the transformer TR2 to flow a current, the receiving circuit RX2 detects an induced current generated in the coil CL2a of the transformer TR2, so that the receiving circuit RX2 can receive a signal corresponding to the control signal outputted from the transmitting circuit TX2.
A signal transmission is performed between the control circuit CC and the drive circuit DR using a path from the transmitting circuit TX1 to the receiving circuit RX1 via the transformer TR1 and using a path from the transmitting circuit TX2 to the receiving circuit RX2 via the transformer TR2. That is, the signal transmission can be performed between the control circuit CC and the drive circuit DR by the receiving circuit RX1 receiving the signal transmitted by the transmitting circuit TX1 and by the receiving circuit RX2 receiving the signal transmitted by the transmitting circuit TX2. As described above, the transformer TR1 is interposed in the signal transmission from the transmitting circuit TX1 to the receiving circuit RX1, and the transformer TR2 is interposed in the signal transmission from the transmitting circuit TX2 to the receiving circuit RX2. Thus, the drive circuit DR can drive the inverter INV operating the load circuit LOD in accordance with the signal transmitted from the control circuit CC.
The control circuit CC and the drive circuit DR have different reference potentials. That is, the reference potential is fixed to the ground potential GND1 in the control circuit CC, while the drive circuit DR is electrically connected to the inverter INV as shown in
The inverter INV includes, for example, a high-side IGBT (Insulated Gate Bipolar Transistor) and a low-side IGBT. The drive circuit DR performs the on/off control of the high-side IGBT and the on/off control of the low-side IGBT in the inverter INV resulting in that the inverter INV can control the load circuit LOD.
Specifically, the drive circuit DR performs the on/off control of the high-side IGBT by controlling the potential applied to the gate electrode of the high-side IGBT. Similarly, the drive circuit DR performs the on/off control of the low-side IGBT by controlling the potential applied to the gate electrode of the low-side IGBT.
Here, for example, the on-control of the low-side IGBT is realized by applying “emitter potential (0 V)+threshold voltage (15 V)” to the gate electrode with reference to the emitter potential (0V) of the low-side IGBT connected to the ground potential GND2.
On the other hand, for example, the off-control of the low-side IGBT is realized by applying an “emitter potential (0 V)” to the gate electrode with reference to the emitter potential (0 V) of the low-side IGBT connected to the ground potential GND2.
Therefore, the on/off control of the low-side IGBT is performed according to whether or not applying the threshold voltage (15 V) to the gate electrode with 0 V as a reference potential.
On the other hand, for example, the on-control of the high-side IGBT is performed by whether or not applying “reference potential+threshold voltage (15 V)” to the gate electrode with reference to the reference potential using the emitter potential of the high-side IGBT as a reference potential.
However, the emitter potential of the high-side IGBT is not fixed to the ground potential GND2 as is the emitter potential of the low-side IGBT. That is, the high-side IGBT and the low-side IGBT are connected in series between the power supply potential VCC2 and the ground potential GND2 in the inverter INV. In the inverter INV, when the high-side IGBT is set to on-state, the low-side IGBT is set to off-state, and when the high-side IGBT is set to off-state, the low-side IGBT is set to on-state.
Therefore, when the high-side IGBT is set to off-state, since the low-side IGBT is set to on-state, the emitter potential of the high-side IGBT becomes the ground potential GND2 due to the low-side IGBT set to on-state.
On the other hand, when the high-side IGBT is set to on-state, since the low-side IGBT is set to off-state, the emitter potential of the high-side IGBT becomes an IGBT bus voltage. In this case, the on/off control of the high-side IGBT is performed by whether or not applying “reference potential+threshold voltage (15V)” to the gate electrode with the emitter potential of the high-side IGBT as a reference potential.
As described above, the emitter potential of the high-side IGBT varies depending on whether the high-side IGBT is set to on-state or off-state. That is, the emitter potential of the high-side IGBT varies from the ground potential GND2 (0 V) to the power supply potential VCC2 (for example, 800 V). Therefore, in order to set the high-side IGBT to on-state, the “IGBT bus voltage (800 V)+threshold voltage (15 V)” needs to be applied to the gate electrode with the emitter potential of the high-side IGBT as a reference potential.
Therefore, the drive circuit DR that performs the on/off control of the high-side IGBT needs to detect the emitter potential of the high-side IGBT. Therefore, the drive circuit DR is configured to receive the emitter potential of the high-side IGBT. Consequently, the drive circuit DR receives the reference potential of 800 V, and the drive circuit DR controls to set the high-side IGBT to on-state by applying the threshold voltage of 15 V to the gate electrode of the high-side IGBT with respect to the reference potential of 800 V. Therefore, a high potential of the order of 800 V is applied to the drive circuit DR.
As described above, the drive control unit includes the control circuit CC that handles the low potential (several tens of volts) and the drive circuit DR that handles the high potential (several hundreds of volts). Therefore, the signal transmission between the control circuit CC and the drive circuit DR requires the signal transmission between the different potential circuits. In this regard, the signal transmission between the control circuit CC and the drive circuit DR is performed via the transformer TR1 and the transformer TR2, so that the signal can be transmitted between different potential circuits.
As described above, a large potential difference may be generated between the primary coil and the secondary coil in the transformer TR1 and the transformer TR2. Conversely, since a large potential difference may be generated, the primary coil and the secondary coil magnetically coupled to each other without being connected by a conductor are used for signal transmission. Therefore, in forming the transformer TR1, increasing the breakdown voltage between the coil CL1a and the coil CL1b as much as possible is required from the viewpoint of improving the operation reliability of the semiconductor device. Similarly, in forming the transformer TR2, increasing the breakdown voltage between the coil CL2b and the coil CL2a as much as possible is required from the viewpoint of improving the operation reliability of the semiconductor device.
In
The transceiver circuit portion of the drive control unit described above, for example, is formed separately into two semiconductor chips. Specifically,
In such a two-chip configuration, for example, the transformer TR1 is formed on the same semiconductor chip CHP1 as the transmitting circuit TX1 and the receiving circuit RX2. Therefore, the transformer TR1, the transmitting circuit TX1, and the receiving circuit RX2 can be integrated. Similarly, the transformer TR2 is formed on the same semiconductor chip CHP2 as the drive circuit DR, the receiving circuit RX1, and the transmitting circuit TX2. Therefore, the transformer TR2, the drive circuit DR, the receiving circuit RX1, and the transmitting circuit TX2 can be integrated.
Here, for example, since the transmitting circuit TX1 and the receiving circuit RX2 are formed in the semiconductor chip CHP1, transistors configuring the transmitting circuit TX1 and the receiving circuit RX2 are formed in the semiconductor chip CHP1. Similarly, since the drive circuit DR, the receiving circuit RX1, and the transmitting circuit TX2 are formed in the semiconductor chip CHP2, transistors configuring the drive circuit DR, the receiving circuit RX1, and the transmitting circuit TX2 are also formed in the semiconductor chip CHP2. Therefore, in the semiconductor chip CHP1, the transformer TR1 and the transistors are formed together. Similarly, in the semiconductor chip CHP2, the transformer TR2 and the transistors are formed together.
As described above, in the two-chip configuration, since the transformer and the transistors are formed on one semiconductor chip, the transformer is formed by using the normal CMOS technique for the transistor.
Specifically, in the normal CMOS technique, a transistor is formed on a semiconductor substrate, and a plurality of wiring layers is formed over the transistor. Here, in the normal CMOS technique, a lower layer wiring formed in a lower wiring layer connects transistors next to each other, and has a short connecting length. Therefore, since the parasitic resistance does not need to be considered as much in the lower layer wiring, the lower layer wiring is configured by a local wiring having a narrow width and a small wiring thickness.
On the other hand, in the normal CMOS technique, an upper layer wiring formed in an upper wiring layer connects circuits separated from each other by a distance, and the connecting length of the upper layer wiring becomes long. Consequently, in the upper layer wiring, the parasitic resistance must be considered and configured by a global wiring having a large width and a large wiring thickness. As described above, in the plurality of wiring layers in the normal CMOS technique, a fine local wiring is formed in the lower wiring layer. In the layers above the lower wiring layer, the closer the layer is disposed to the upper wiring layer, the greater the wiring width and the wiring thickness of the wiring formed in the layer will be. That is, in the normal CMOS technique, the wirings formed in the plurality of wiring layers are configured by a local wiring formed in the lower wiring layer, a semi-global wiring formed in the middle wiring layer, and a global wiring formed in the upper wiring layer.
When the transformer is formed on the premise of such a normal CMOS technique, the lower inductor, which is a component of the transformer, is formed using a local wiring formed in the lower wiring layer. On the other hand, the upper inductor, which is a component of the transformer, is formed using a global wiring formed in the upper wiring layer. As a result, an enough distance can be secured between the lower inductor and the upper inductor (the distance in the thickness direction of the semiconductor chip), so that the breakdown voltage of the transformer can be secured.
However, in recent years, it has been desired to further improve the breakdown voltage of the transformer, and a technique for improving the breakdown voltage of the transformer is required.
For example, in the normal CMOS technique, transistors are formed on the semiconductor substrate, and a multilayer wiring layer is formed over the semiconductor substrate in which the transistors are formed. In this case, the thickness of the semiconductor substrate is about 400 μm, while the thickness of the multilayer wiring layer is about 4 μm.
Therefore, when the transformer is formed in the multilayer wiring layer using the normal CMOS technique, a distance between the lower inductor and the upper inductor configuring the transformer is at most about 4 μm. However, when the distance between the lower inductor and the upper inductor is about 4 μm, it is difficult to secure the enough breakdown voltage (galvanic breakdown voltage) between the lower inductor and the upper inductor.
Therefore, on the premise that the normal CMOS technique is used, an attempt has been made to secure a distance between the lower inductor and the upper inductor by increasing the thickness of the multilayer wiring layer. However, when the normal CMOS technique is used, the thickness of the multilayer wiring layer cannot be increased to any extent due to factors such as “warpage” in the semiconductor substrate, and for example, the thickness is limited to set the multilayer wiring layer to about 20 μm. That is, when the normal CMOS technique is employed, the distance between the lower inductor and the upper inductor are limited to about 20 μm.
In this regard, since the breakdown voltage required for the transformer is 3750 V in terms of alternating current (in AC), the breakdown voltage can be ensured by devising even when the transformer is formed using a normal CMOS technique.
However, in order to improve the transmission efficiency, it is desirable to use a high voltage, and therefore, the breakdown voltage required for the transformer is further increased in the future. Specifically, the breakdown voltage required for the transformer is 5000 V in terms of alternating current (AC).
Therefore, the distance between the lower inductor and the upper inductor must be about 100 μm or more, which cannot be dealt with by a technique of forming a transformer using a normal CMOS technique. In other words, in order to realize the transformer having the breakdown voltage of about 5000 V in terms of alternating current, a new designing concept different from the normal CMOS technique is required.
Therefore, in the following, in order to realize the transformer having the breakdown voltage of about 5000 V in terms of alternating current, a technical idea developed based on a new designing concept that is different from the normal CMOS technique will be described.
The basic concept is that the breakdown voltage of the transformer is ensured using a new insulating substrate different from the semiconductor substrate in which the multilayer wiring layer is formed, instead of securing the breakdown voltage of the transformer using the thickness of the multilayer wiring layer (thickness of the laminated insulating films). In other words, the basic concept is that a new insulating substrate is prepared to secure the distance between the lower inductor and the upper inductor by, for example, the thickness of the insulating substrate.
According to this basic concept, by setting the thickness of the insulating substrate to about 100 μm, it is possible to set the distance between the lower inductor and the upper inductor to about 100 μm, so that it is possible to realize a transformer having a breakdown voltage of about 5000V in terms of alternating current.
In the following, an embodiment embodying the basic concept will be described.
In
The transmitting circuit TX1 and the receiving circuit RX2 shown in
The thickness of the semiconductor substrate SUB1 is about 400 μm, and the thickness of the multilayer wiring layer MWL1 is about 4 μm. Therefore, the semiconductor chip CHP1 has a thickness of about 404 μm.
Next, the drive circuit DR, the receiving circuit RX1, and the transmitting circuit TX2 shown in
Subsequently, as shown in
The thickness of the insulating substrate 1S is greater than the thickness of the multilayer wiring layer MWL1. Specifically, the thickness of the semiconductor substrate SUB2 is about 400 μm, the thickness of the multilayer wiring layer MWL2 is about 4 μm, and the thickness of the insulating substrate 1S is about 100 μm. As described above, the insulating substrate 1S having a thickness of about 100 μm is laminated on the semiconductor chip CHP2 having a thickness of about 404 μm.
Further, the configuration of the semiconductor device in the first embodiment will be described.
In the first embodiment, the semiconductor device includes the insulating substrate 1S and the upper inductor TL formed on the insulating substrate 1S and being a component of a transformer that performs contactless communication between different potentials. In this case, the upper inductor TL is electrically connected to wiring present in the multilayer wiring layer MWL1 formed in the semiconductor chip CHP1 and is applied with the first potential. Specifically, the semiconductor device includes the semiconductor chip CHP1 including a circuit (first circuit) that applies the first potential to the upper inductor TL. The upper inductor TL formed on the insulating substrate 1S is electrically connected to a circuit formed in the semiconductor chip CHP1 via the bonding wire W that is an exemplary conductive member. Accordingly, the first potential outputted from the circuit formed in the semiconductor chip CHP1 is applied to the upper inductor TL.
The semiconductor device includes the semiconductor chip CHP2 having the lower inductor BL, and the semiconductor chip CHP2 includes a circuit (second circuit) applying a second potential to the lower inductor BL. Accordingly, the second potential outputted from the circuit formed in the semiconductor chip CHP2 is applied to the lower inductor BL. Consequently, the first potential is applied to the upper inductor TL, while the second potential is applied to the lower inductor BL.
Here, the upper inductor TL is formed so as to be magnetically coupled to the lower inductor BL to which the second potential different from the first potential is applied in the thickness direction of the insulating substrate 1S. Specifically, the insulating substrate 1S has a first surface S1 and a second surface S2 located opposite the first surface S1. The insulating substrate 1S is laminated on the semiconductor chip CHP2 via the adhesive member DAF such that the lower inductor BL faces the second surface S2 while the upper inductor TL is formed on the first surface S1. Thus, the upper inductor TL and the lower inductor BL are configured to be magnetically coupled to each other.
The semiconductor chip CHP2 includes the transistor Q2 formed on the semiconductor substrate SUB2 and the multilayer wiring layer MWL2 formed over the transistor Q2, and the lower inductor BL is formed in the multilayer wiring layer MWL2. For example, the lower inductor BL is formed in the uppermost layer of the multilayer wiring layer MWL2. However, the lower inductor BL may not be disposed in the uppermost layer of the multilayer wiring layer MWL2. For example, when the multilayer wiring layer MWL2 is formed using the normal CMOS technique and the multilayer wiring layer MWL2 includes a local wiring, a semi-global wiring, and a global wiring, the lower inductor BL can be formed in the same wiring layer as either the semi-global wiring or the global wiring.
The semiconductor device in the first embodiment is configured as described above.
A first feature point of the semiconductor device according to the first embodiment is that, for example, as shown in
Thus, according to the semiconductor device of the first embodiment, the breakdown voltage between the upper inductor TL and the lower inductor BL can be ensured by the thickness of the insulating substrate 1S while the upper inductor TL and the lower inductor BL are magnetically coupled to form the transformer. For example, by setting the thickness of the insulating substrate to about 100 μm, the insulating distance between the lower inductor BL and the upper inductor TL can be set to about 100 μm, so that a transformer having a breakdown voltage of about 5000 V in alternating current can be realized.
As described above, in the first feature, the breakdown voltage of the transformer is secured by using a new insulating substrate 1S different from the semiconductor chip CHP2 on which the multilayer wiring layer MWL2 is formed, rather than securing the breakdown voltage of the transformer by the thickness of the multilayer wiring layer MWL2 formed on the semiconductor chip CHP2. That is, in the first feature, the insulating distance between the lower inductor BL and the upper inductor TL is ensured by the thickness of the insulating substrate 1S different from the semiconductor chip CHP2, instead of securing the insulating distance between the upper inductor TL and the lower inductor BL by the multilayer wiring layer MWL2 in the semiconductor chip CHP2 formed using the normal CMOS technique. Thus, according to the first feature, it is possible to secure the breakdown voltage of the transformer that is difficult to realize by using the normal CMOS technique. Thus, according to the first feature, a higher breakdown voltage can be ensured, and thus the reliability of the semiconductor device can be improved.
Furthermore, for example, if a normal CMOS technique is used to ensure the insulating distance between the lower inductor BL and the upper inductor TL, a maximum of 20 μm is a limitation. Therefore, it is difficult to realize a transformer having a breakdown voltage of about 5000 V in alternating current in a technique of forming a transformer using the normal CMOS technique.
On the other hand, according to the first feature, the breakdown voltage of the transformer can be easily secured by adjusting the thickness of the insulating substrate 1S different from the semiconductor chip CHP2 using the normal CMOS technique. For example, by using the insulating substrate 1S, an insulating distance of about 100 μm, which is difficult to realize by the normal CMOS technique, can be easily realized.
Further, by adjusting the thickness of the insulating substrate 1S, it is also easy to design the breakdown voltage of the transformer to a predetermined value. That is, the first feature point has a great technical significance in that it is possible not only to realize a transformer having a breakdown voltage of 5000 V in terms of alternating current but also to provide a design method that facilitates designing the breakdown voltage of the transformer to various values by appropriately adjusting the thickness of the insulating substrate 1S. For example, further increasing the thickness of the insulating substrate 1S can realize a larger breakdown voltage of the transformer. In addition, depending on the required specifications of the transformer, a small breakdown voltage of the transformer can be realized by reducing the thickness of the insulating substrate 1S.
Subsequently, a second feature point of the semiconductor device according to the first embodiment is that, for example, the lower inductor BL formed in the semiconductor chip CHP2 is disposed in the same wiring layer as wiring layer formed with one of the semi-global wiring and the global wiring in the multilayer wiring layer MWL2. In other words, the second feature is that the lower inductor BL is formed in the same layer as the semi-global wiring or the global wiring formed by the normal CMOS technique.
Thus, according to the second feature, the thickness of the lower inductor BL can be made equal to the thickness of the semi-global wiring or the thickness of the global wiring. Since the thickness of the semi-global wiring and the thickness of the global wiring are greater than the thickness of the local wiring, so that the parasitic resistance of the lower inductor BL can be reduced. Therefore, according to the second feature point, it is possible to suppress the deterioration of the signal amplitude of the signal that transmits in the lower inductor BL.
For example, in the normal CMOS technique, the lower layer wiring is configured by the local wiring, while the upper layer wiring is configured by the global wiring. The designing concept such a normal CMOS technique is based on that the lower layer wiring is a wiring connecting adjacent transistors and the parasitic resistance of wiring may not be considered as much while the upper layer wiring is a wiring connecting circuits separated from each other and the parasitic resistance of wiring needs to be considered.
In this regard, in a technique of forming a transformer by using a normal CMOS technique, the lower inductor is formed in a wiring layer that is the same layer as a wiring layer in which a local wiring is disposed. However, since a large current flows through the lower inductor, the influence of the parasitic resistance is large. Specifically, when the lower inductor is formed in wiring layer in the same layer as wiring layer in which the local wiring is disposed, the lower inductor has a high resistance, and consequently, the signal amplitude of the signal that transmits in the lower inductor deteriorates due to the high-resistance parasitic resistance. This is because the local wiring is designed based on the designing concept of the normal CMOS technique that the parasitic resistances need not be considered as much, whereas the low resistance for improving the signal-quality required for the design of the lower inductor is not considered in the designing concept of the normal CMOS technique for the local wiring. That is, although the designing concept of the lower inductor is different from the designing concept of the local wiring in the normal CMOS technique, the signal amplitude of the signal transmitting in the lower inductor BL deteriorates due to the fact that the lower inductor is formed in wiring layer of the same layer as the local wiring.
In this regard, in the second feature point in the second embodiment, in order to realize a configuration in which a low-resistance lower inductor BL is disposed, a novel designing concept is adopted in which the lower inductor BL is formed in the same layer as a semi-global wiring or a global wiring having a low parasitic resistance, unlike a technique of using a normal CMOS technique in which the lower inductor BL is formed in the same layer as a local wiring having a large parasitic resistance. This designing concept can be realized because the first feature point of laminating the insulating substrate 1S on the semiconductor chip CHP2 is adopted so that the insulating substrate 1S formed with the upper inductor TL is disposed facing the lower inductor BL formed on the semiconductor chip CHP2. According to this designing concept, the thickness of the lower inductor BL can be increased, and consequently, the parasitic resistance of the lower inductor BL can be reduced. Thus, in the second feature point, since the parasitic resistance of the lower inductor BL can be reduced, deterioration of the signal amplitude of the signal transmitting in the lower inductor BL can be suppressed. That is, according to the second feature point, it is possible to improve the performance of the semiconductor device.
Next, the details of the insulating structure will be described.
In
The upper inductor TL (coil CL2a) is formed on the insulating film IF1, and an insulating film IF2 is formed so as to cover the upper inductor TL. The upper inductor TL is formed of, for example, a copper film or an aluminum film, and the insulating film IF2 is formed of, for example, an organic insulating film such as a polyimide resin film.
The insulating film IF2 includes a plurality of openings, and a pad PD1 and a pad PD2 are formed on the insulating film IF2 so as to fill the openings. Each of the pad PD1 and the pad PD2 is formed of, for example, a copper film (Cu film) or a laminated film of Au/Ni/Cu.
Here, the insulating substrate 1S is preferably made of a glass substrate. This is because, as shown in
The insulating structure is configured as described above.
The manufacturing method of the insulating structure will be described.
As shown in
Next, a barrier metal film is formed on the insulating film IF1, and then a seed film is formed on the barrier metal film. As a result, a base film BF formed of a barrier metal film and a seed film is formed. At this time, the barrier metal film is formed of, for example, a chromium film, and can be formed by using, for example, a sputtering method. The seed film is formed of, for example, a copper film, and can be formed by using, for example, a sputtering method.
Subsequently, a resist pattern RP is formed on the base film BF by using a photolithography technique. Thereafter, a conductive film CF formed of, for example, a copper film is formed on the base film BF exposed from the resist pattern RP by using a plating method.
Next, as shown in
Thereafter, as shown in
Next, the insulating film IF2 is patterned using a photolithography technique to form openings. Subsequently, as in the case of forming the conductive film CF, a barrier metal film and a seed film are formed on the insulating film IF2. Thereafter, the conductive film formed of, for example, a copper film (Cu film) or a laminated film of Au/Ni/Cu is formed using a photolithography technique and a plating method. Thus, the pad PD1 and the pad PD2 electrically connected to the conductive film CF as shown in
Subsequently, as shown in
Then, as shown in
In the semiconductor device in the above-described first embodiment, the two-chip configuration is employed. However, in the two-chip configuration, for example, the transformer TR1, the transmitting circuit TX1, and the receiving circuit RX2 need to be formed on one semiconductor chip resulting in complicating the manufacturing process of the semiconductor chip CHP1. Alternatively, in the two-chip configuration, for example, the transformer TR2, the drive circuit DR, the receiving circuit RX1, and the transmitting circuit TX2 need to be formed on one semiconductor chip resulting in complicating the manufacturing process of the semiconductor chip CHP2. As a consequence, the manufacturing costs of the semiconductor chip CHP1 and the semiconductor chip CHP2 may increase.
Therefore, it has been studied to realize the above-described semiconductor device not in the two-chip configuration but in the three-chip configuration. Hereinafter, a novel three-chip configuration will be described.
In
Thus, in the three-chip configuration, only the transformer TR1 and the transformer TR2 are formed in the semiconductor chip CHP3. That is, in the three-chip configuration, the semiconductor chip CHP3 can be used regardless of the configuration of the semiconductor chip CHP1 and the semiconductor chip CHP2. As a result, according to the three-chip configuration, the usable variation of the semiconductor chip CHP1 and the semiconductor chip CHP2 can be increased. In other words, the versatility of the semiconductor chip CHP3 in which the transformer TR1 and the transformer TR2 are formed can be improved. Further, since the semiconductor chip CHP3 in which the transformer TR1 and the transformer TR2 are formed does not include a transistor, the semiconductor chip CHP3 can be formed only by wiring process, and thus the manufacturing process can be simplified. Therefore, the three-chip configuration can reduce the manufacturing cost, and thus a highly competitive product can be manufactured.
However, in the above-described three-chip configuration, for example, focusing on the transformer TR2, the coil CL2a (upper inductor) and the coil CL2b (lower inductor) configuring the transformer TR2 are formed in the semiconductor chip CHP3. In this case, the breakdown voltage of the transformer TR2 is ensured by the thickness of the multilayer wiring layer (the thickness of the laminated insulating films) formed on the semiconductor chip CHP3.
However, when both the coil CL2a and the coil CL2b which form the transformer TR2 are formed in the multilayer wiring layer, the distance between the coil CL2a and the coil CL2b is at most about 4 μm. In this regard, when the distance between the coil CL2a and the coil CL2b is about 4 μm, it is difficult to ensure an enough breakdown voltage of about 5000V in terms of alternating current.
Therefore, in the following description, a modified example according to the first embodiment will be described, in which, in a three-chip configuration, the breakdown voltage between the coil CL2a and the coil CL2b (for example, the breakdown voltage 5000 V in terms of alternating current) is secured by using a new insulating substrate different from the semiconductor chip CHP3.
In
Here, each of the die pad DP1 and the die pad DP2 is made of, for example, a copper material. Each of the conductive adhesive PST1, the conductive adhesive PST2, and the conductive adhesive PST3 is made of, for example, silver-paste or solder.
The transmitting circuit TX1 and the receiving circuit RX2 shown in
Next, as shown in
Subsequently, in the semiconductor chip CHP3, the insulating substrate 1S is disposed on the wiring layer WL in which the lower inductor BL is formed, via an adhesive member DAF2. Here, the adhesive member DAF2 is formed of, for example, a die attach film. The insulating substrate 1S is made of a glass substrate. On the insulating substrate 1S, the insulating layer IL and the upper inductor TL (coil CL2a) which is formed on the insulating layer IL and is a component of the transformer are formed. The upper inductor TL is electrically connected, for example, to wiring disposed in the multilayer wiring layer MWL1 of the semiconductor chip CHP1 via a bonding wire W1.
The thickness of the insulating substrate 1S is greater than the thickness of the wiring layer WL. Specifically, the thickness of the semiconductor substrate SUB3 is about 400 μm, the thickness of wiring layer WL is about several μm, and the thickness of the insulating substrate 1S is about 100 μm. As described above, the insulating substrate 1S having a thickness of about 100 μm is laminated on the semiconductor chip CHP3 having a thickness of about 400 μm.
The semiconductor device according to the first modified example includes the semiconductor chip CHP2 having a circuit (second circuit) applying the second potential to the lower inductor BL, and the semiconductor chip CHP3 in which the lower inductor BL is formed. Here, the lower inductor BL formed in the semiconductor chip CHP3 is electrically connected to the circuit (second circuit) formed in the semiconductor chip CHP2 via the bonding wire W2. That is, in plan view, the size of the semiconductor chip CHP3 is larger than the size of the insulating substrate 1S, and the semiconductor chip CHP3 is electrically connected to the semiconductor chip CHP2 via the bonding wire W2 in the non-mounting region of the semiconductor chip CHP3 on which the insulating substrate 1S is not mounted. Specifically, the lower inductor BL, the pad, and the wiring that electrically connects the lower inductor BL and the pad are formed in the uppermost layer of the wiring layer WL, and the insulating substrate 1S is disposed on the semiconductor chip CHP3 so that the pad is exposed from the insulating substrate 1S. Since the pad is formed so as not to overlap with the insulating substrate 1S, the pad electrically connected to the lower inductor BL can be electrically connected to the semiconductor chip CHP2 via the bonding wire W2.
In the semiconductor device of the first modified example configured as described above, as shown in
Thus, according to the semiconductor device of the first modified example, the upper inductor TL and the lower inductor BL are magnetically coupled to form a transformer, and the breakdown voltage between the upper inductor TL and the lower inductor BL can be ensured by the thickness of the insulating substrate 1S.
In addition, in the semiconductor device of the first modified example, as shown in
Thus, according to the semiconductor device of the first modified example, the thickness of the lower inductor BL can be increased. Therefore, in the lower inductor BL, since the parasitic resistance can be reduced, deterioration of the signal amplitude of the signal transmitting in the lower inductor BL can be suppressed.
In
Here, each of the die pad DP1 and the die pad DP2 is made of, for example, a copper material. Each of the conductive adhesive PST1 and the conductive adhesive PST2 is made of, for example, silver-paste or solder. The adhesive member DAFT is formed of, for example, a die attach film.
The transmitting circuit TX1 and the receiving circuit RX2 shown in
Next, as shown in
Here, the lower inductor BL is electrically connected to the wiring disposed in the multilayer wiring layer MWL2 of the semiconductor chip CHP2 via the bonding wire W2.
Subsequently, in the chip CHP3A, the insulating substrate 1S is laminated on the wiring layer WL in which the lower inductor BL is formed, via the adhesive member DAF2. Here, the adhesive member DAF2 is formed of, for example, a die attach film. The insulating substrate 1S is made of a glass substrate. On the insulating substrate 1S, the upper inductor TL (coil CL2a), which is a component of the transformer, is formed together with the insulating layer IL. The upper inductor TL is electrically connected to the wiring disposed in the multilayer wiring layer MWL1 of the semiconductor chip CHP1 via the bonding wire W1.
The thickness of the insulating substrate 1S is greater than the thickness of the wiring layer WL. Specifically, the thickness of the insulating substrate SUB3A is about 400 μm, the thickness of the wiring layer WL is about several μm, and the thickness of the insulating substrate 1S is about 100 μm. As described above, the insulating substrate 1S having a thickness of about 100 μm is laminated on the tip CHP3A having a thickness of about 400 μm.
The semiconductor device in the second modified example includes the semiconductor chip CHP2 including the circuit (second circuit) applying the second potential to the lower inductor BL and the chip CHP3A in which the lower inductor BL is formed. Here, the lower inductor BL formed in the chip CHP3A is electrically connected to the circuit (second circuit) formed in the semiconductor chip CHP2 via the bonding wire W2. That is, in plan view, the size of the chip CHP3A is larger than the size of the insulating substrate 1S, and the chip CHP3A is electrically connected to the semiconductor chip CHP2 via the bonding wire W2 in the non-mounting region of the chip CHP3A on which the insulating substrate 1S is not mounted.
In the semiconductor device configured as described above according to the second modified example, as shown in
Thus, according to the semiconductor device in the second modified example, the upper inductor TL and the lower inductor BL are magnetically coupled to form the transformer, and the breakdown voltage between the upper inductor TL and the lower inductor BL can be ensured by the thickness of the insulating substrate 1S.
In addition, in the semiconductor device of the second modified example, as shown in
Thus, according to the semiconductor device of the second modified example, the thickness of the lower inductor BL can be increased. Therefore, in the lower inductor BL, since the parasitic resistance can be reduced, deterioration of the signal amplitude of the signal transmitting in the lower inductor BL can be suppressed.
Further, according to the semiconductor device of the second modified example, the chip CHP3A uses the insulating substrate SUB3A represented by a glass substrate instead of the semiconductor substrate. Thus, as can be seen from the comparison between
In
Here, each of the die pad DP1 and the die pad DP2 is made of, for example, a copper material. Each of the conductive adhesive PST1 and the conductive adhesive PST2 is made of, for example, silver-paste or solder. Further, the adhesive member DAFT is formed of, for example, a die attach film.
The transmitting circuit TX1 and the receiving circuit RX2 shown in
Next, the drive circuit DR, the receiving circuit RX1, and the transmitting circuit TX2 shown in
Subsequently, as shown in
The upper inductor TL formed on the first surface S1 of the insulating substrate 1S is electrically connected to a circuit (first circuit) formed in the semiconductor chip CHP1 via the bonding wire W1. Further, the through-via TGV1 formed in the insulating substrate 1S is electrically connected to a connection terminal TE1 formed on the first surface S1 of the insulating substrate 1S, similarly, the through-via TGV2 formed in the insulating substrate 1S is electrically connected to a connection terminal TE2 formed on the first surface S1 of the insulating substrate 1S. Further, although not shown in
For example, in
The lower inductor BL includes a pad PD1A formed in one layer of the two layers, a pad PD2A formed in the one layer, and a lead wiring portion DWU formed in the one layer described above and in another one layer of the two layers and electrically connected to the pad PD2A. Here, there are a plurality of through-vias, and the plurality of through-vias includes the through-via TGV1 electrically connected to the pad PD1A and the through-via TGV2 electrically connected to the lead wiring portion DWU.
The semiconductor device in the second embodiment is configured as described above.
In the semiconductor device of the second embodiment, as shown in
In the semiconductor device of the second embodiment, as shown in
Further, in the semiconductor device of the second embodiment, as shown in
Next, an insulating structure including a transformer will be described.
In
Next, the manufacturing method of the insulating structure having a transformer will be described.
First, as shown in
Next, as shown in
Subsequently, as shown in
Thereafter, as shown in
Then, an insulating film PI2 covering the upper inductor TL, the connection terminal TE1, and the connection terminal TE2 is formed on the first surface S1 of the insulating substrate 1S. The insulating film PI2 is formed of, for example, an organic insulating film such as a polyimide resin film, and can be formed by using, for example, a coating method. Thereafter, the insulating film PI2 is polished to expose the upper inductor TL, the connection terminal TE1, and the connection terminal TE2.
In this way, an insulating structure with a transformer can be formed. Further, by separating the insulating structure including the transformer from the supporting substrate 2S, the insulating structure including the transformer can be manufactured.
In
As shown in
In
As described above, in the insulating structures shown in
As described above, in the insulating structure according to the first modified example, for example, as shown in
That is, when the lower inductor BL is formed of a spiral inductor, the lower inductor BL must necessarily be formed of two layers if the lower inductor BL formed on the second surface S2 and the connection terminal TE1 and the connection terminal TE2 formed on the first surface S1 are connected to each other. On the other hand, when the lower inductor BL is formed of a meander inductor, for example, the lower inductor BL can be formed of a single layer as a result of being able to be routed in a single layer instead of two layers as shown in
In
As shown in
On the other hand, as shown in
Here, in plan view, the first wiring portion LU1 and the third wiring portion LU3 intersect with each other, and in plan view, the second wiring portion LU2 and the fourth wiring portion LU4 intersect with each other.
Thus, according to the second modified example, the first inductor FL and the second inductor SL, which are components of the transformer that performs contactless communication between different potentials, are formed so as to be magnetically coupled. According to the second modified example, each of the first inductor FL and the second inductor SL can be configured by the first layer (single layer) formed on the first surface of the insulating substrate 1S and the second layer (single layer) formed on the second surface of the insulating substrate 1S.
The invention made by the present inventor has been described above in detail based on the embodiment, but the present invention is not limited to the embodiment described above, and it is needless to say that various modifications can be made without departing from the gist thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-163944 | Oct 2022 | JP | national |
