SEMICONDUCTOR DEVICE

Abstract

A semiconductor device, including: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a trench formed in the semiconductor region; a trench diffusion layer of the first conductivity type formed along wall surfaces of the trench; and a buried conductor buried in the trench, wherein an insulation film is further disposed between the wall surfaces of the trench and the buried conductor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a top view of a semiconductor device according to a first embodiment of the present invention;

FIG. 1B shows a cross sectional view of a semiconductor device according to a first embodiment of the present invention;

FIGS. 2A through 2D show cross sectional views of steps for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3A shows a top view of a semiconductor device according to a second embodiment of the present invention;

FIG. 3B shows a cross sectional view of a semiconductor device according to a second embodiment of the present invention;

FIG. 4A shows a top view of a semiconductor device according to a third embodiment of the present invention;

FIG. 4B shows a cross sectional view of a semiconductor device according to a third embodiment of the present invention;

FIG. 5A shows a top view of a semiconductor device according to a fourth embodiment of the present invention;

FIGS. 5B and 5C show a cross sectional views of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 6 is a top view of a semiconductor device according to a fifth embodiment of the present invention;

FIG. 7 is a top view of a semiconductor device according to a sixth embodiment of the present invention;

FIG. 8 is a top view of a semiconductor device according to a seventh embodiment of the present invention;

FIG. 9A shows a top view of a semiconductor device according to an eighth embodiment of the present invention;

FIG. 9B shows a cross sectional view of a semiconductor device according to an eighth embodiment of the present invention;

FIG. 10A shows a top view of a semiconductor device according to a ninth embodiment of the present invention;

FIG. 10B shows a cross sectional view of a semiconductor device according to a ninth embodiment of the present invention;

FIG. 11A shows a top view of a semiconductor device according to a tenth embodiment of the present invention;

FIG. 11B shows a cross sectional view of a semiconductor device according to a tenth embodiment of the present invention;

FIG. 12A shows a top view of a semiconductor device according to an eleventh embodiment of the present invention;

FIG. 12B shows a cross sectional view of a semiconductor device according to an eleventh embodiment of the present invention;

FIG. 13A shows a top view of a semiconductor device according to a twelfth embodiment of the present invention;

FIG. 13B shows a cross sectional view of a semiconductor device according to a twelfth embodiment of the present invention;

FIG. 14A shows a top view of a semiconductor device according to a thirteenth embodiment of the present invention;

FIG. 14B shows a cross sectional view of a semiconductor device according to a thirteenth embodiment of the present invention;

FIG. 15A shows a top view of a semiconductor device according to a fourteenth embodiment of the present invention;

FIG. 15B shows a cross sectional view of a semiconductor device according to a fourteenth embodiment of the present invention;

FIG. 16A shows a top view of a semiconductor device according to a fifteenth embodiment of the present invention;

FIG. 16B shows a cross sectional view of a semiconductor device according to a fifteenth embodiment of the present invention;

FIG. 17A shows a top view of a semiconductor device according to a sixteenth embodiment of the present invention;

FIG. 17B shows a cross sectional view of a semiconductor device according to a sixteenth embodiment of the present invention;

FIG. 18A shows a top view of a semiconductor device according to a seventeenth embodiment of the present invention;

FIG. 18B shows a cross sectional view of a semiconductor device according to a seventeenth embodiment of the present invention;

FIG. 19A shows a top view of a semiconductor device according to an eighteenth embodiment of the present invention; and

FIG. 19B shows a cross sectional view of a semiconductor device according to an eighteenth embodiment of the present invention; and

FIG. 20 is a cross sectional view of a conventional semiconductor device.

Claims

1. A semiconductor device, comprising: a semiconductor substrate of a first conductivity type;a semiconductor layer of a second conductivity type formed on said semiconductor substrate;a trench formed in said semiconductor region;a trench diffusion layer of the first conductivity type formed along wall surfaces of said trench; anda buried conductor buried in said trench, whereinan insulation film is further disposed between said wall surfaces of said trench and said buried conductor.

2. The semiconductor device according to claim 1, wherein said trench is disposed reaching said semiconductor substrate.

3. The semiconductor device according to claim 1, comprising a buried layer of the second conductivity type disposed locally between said semiconductor substrate and said semiconductor layer, wherein said trench is shallower than the film thickness of said semiconductor layer but reaches said buried layer.

4. The semiconductor device according to claim 1, wherein said buried conductor is electrically connected with said trench diffusion layer.

5. The semiconductor device according to claim 1, wherein a first diffusion layer of the first conductivity type is formed in said semiconductor layer around the opening of said trench, and the first conductivity type impurity concentration of said first diffusion layer is lower than the first conductivity type impurity concentration of said trench diffusion layer.

6. The semiconductor device according to claim 1, wherein a second diffusion layer of the first conductivity type is formed along said trench diffusion layer which is in the vicinity of the opening of said trench, and the first conductivity type impurity concentration of said second diffusion layer is lower than the first conductivity type impurity concentration of said trench diffusion layer.

7. The semiconductor device of claim 5, wherein said trench has, within the surface of said semiconductor layer, an approximately rectangular shape which bends approximately at a right angle in corner sections, and said first diffusion layer is disposed around said corner sections.

8. The semiconductor device according to claim 1, wherein said trench has, within the surface of said semiconductor layer, a polygonal shape having corner sections whose inner angle exceeds 90 degrees.

9. The semiconductor device according to claim 1, wherein said trench has, within the surface of said semiconductor layer, a shape having arc-like corner sections.

10. The semiconductor device according to claim 7, wherein there is a semiconductor element in an area surrounded by said trench.

11. The semiconductor device according to claim 1, wherein multiple such trenches are formed surrounding an isolation region within the surface of said semiconductor layer, a second diffusion layer of the first conductivity type is formed along said trench diffusion layer which is in the vicinity of the opening of the outer-most trench, andthe first conductivity type impurity concentration of said second diffusion layer is lower than the first conductivity type impurity concentration of said trench diffusion layer.

12. The semiconductor device according to claim 1, comprising a buried layer of the second conductivity type disposed locally between said semiconductor substrate and said semiconductor layer and a circuit portion formed above said buried layer between said semiconductor substrate and said semiconductor layer, wherein said trench is formed surrounding said semiconductor element and reaching said buried layer, andsaid trench diffusion layer and said buried conductor are connected with an area of the second conductivity type which is contained within said circuit portion.

13. The semiconductor device according to claim 1, wherein such trenches are formed, one at the inner circumference and the other at the outer circumference, in such a manner that said trenches surround an isolation region within the surface of said semiconductor layer, and a high-voltage circuit portion or a level shifter circuit portion is disposed in said isolation region surrounded by the inner trench, a low-voltage logic circuit portion is disposed outside the outer trench, and an area of the second conductivity type surrounded by the inner trench and the outer trench is electrically connected with said trench diffusion layer at the outer circumference which is disposed inside said isolation region.

14. The semiconductor device according to claim 3, wherein within said semiconductor layer including a level shifter circuit portion, a high-voltage part of said level shifter circuit portion has a drain of the first conductivity type, said high-voltage part and said semiconductor layer of the second conductivity type form a diode, and said trench is formed surrounding said drain of the first conductivity type.

15. The semiconductor device according to claim 14, wherein a MOSFET including said drain, a source of the first conductivity type and a gate is formed within said semiconductor layer which is surrounded by said trench.

16. The semiconductor device according to claim 15, wherein said MOSFET is designed to normally remain turned on and have such a threshold value in accordance with which said MOSFET turns off upon occurrence of abnormality that an electric potential at said semiconductor layer which is surrounded by said trench increases.

17. The semiconductor device according to claim 1, wherein an upper section of said buried conductor includes an extension area which extends out covering the top of said trench diffusion layer.