Patent Application
20090201474
The present invention relates generally to the fabrication of semiconductor devices, and more particularly to the patterning of material layers of semiconductor devices.
Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon, forming an integrated circuit.
One type of semiconductor lithography involves positioning a patterned mask between a semiconductor workpiece and an energy source to expose portions of a photosensitive material deposited on the workpiece, transferring the mask pattern to the photosensitive material. The photosensitive material is then developed and used as a mask while exposed regions of a material on the workpiece are etched away. The photosensitive material is removed, and additional material layers may be deposited and patterned in a similar fashion. There may be a dozen or more lithography mask levels required to manufacture an integrated circuit, for example.
As semiconductor devices are scaled down or reduced in size, lithography of semiconductor devices becomes more difficult. Planarization of isolated features and nested features may result in uneven topography of a top surface of a semiconductor wafer, which may deleteriously affect lithography processes.
Therefore, what are needed in the art are improved methods of manufacturing semiconductor devices.
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention, which provide novel methods and lithography masks for patterning material layers of semiconductor devices.
In accordance with an embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a workpiece, the workpiece comprising a first thickness in a first region and at least one second thickness in at least one second region. A layer of photosensitive material is disposed over the workpiece, and a lithography mask is provided. The lithography mask has a first phase shift in a first region and at least one second phase shift in at least one second region. The layer of photosensitive material is exposed to energy through the lithography mask, and the layer of photosensitive material is developed, leaving portions of the workpiece exposed. The exposed portions of the workpiece are affected using the layer of photosensitive material as a mask.
The foregoing has outlined rather broadly the features and technical advantages of embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
Metallization layers are usually the top-most material layers of semiconductor devices. The manufacturing of semiconductor devices is typically classified into two phases, a front end of line (FEOL) and a back end of line (BEOL). The BEOL is typically considered to be the point of the manufacturing process where metallization layers are formed, and the FEOL is generally considered to include the manufacturing processes prior to the formation of the metallization layers.
While some integrated circuits have a single top layer of metallization, other integrated circuits comprise multi-level interconnects, wherein two or more metallization layers are formed over a semiconductor wafer or workpiece. Each conductive line layer typically comprises a plurality of conductive lines separated from one another by an insulating material, also often referred to as an inter-level dielectric (ILD). The conductive lines in adjacent horizontal metallization layers may be connected vertically in predetermined places by vias formed between the conductive lines. The first metallization layer in a multi-level interconnect scheme is often referred to as a contact layer, for example.
Damascene processes may be used to form conductive features in metallization layers, e.g., particularly if the conductive features comprise copper, which is a material that is difficult to subtractively etch. In a damascene process, a material such as a dielectric or insulator is deposited over a wafer, and then the material is patterned with a conductive feature pattern. The conductive feature pattern typically comprises a plurality of trenches (for conductive lines), or apertures (for vias), for example. The trenches or apertures are then filled in with a conductive material, and a chemical-mechanical polish (CMP) process and/or etch process is used to remove the excess conductive material from the top surface of the patterned material. The conductive material remaining within the patterned material comprises conductive features such as conductive lines and/or vias.
Damascene processes are typically either single or dual damascene. In a single damascene process, one metallization layer is formed at a time. In a dual damascene process, two adjacent horizontal metallization layers are patterned, e.g., by forming two lithography patterns in two insulating material layers such as dielectric layers or in a single insulating material layer. The two patterns are then filled in with conductive material, and a CMP process is used to remove excess conductive material from over the insulating material, leaving patterned conductive material in the insulating material layers. For example, the patterns may comprise trenches for conductive lines in one insulating material layer portion and apertures for vias in the underlying insulating material layer portion. Thus, in a dual damascene process, conductive line trench patterns and via aperture patterns are filled in one fill step.
After a CMP polish in a damascene process, topography differences may be caused by underlying feature or circuit density differences. The top surface of material layers after a CMP process may not be planar, but rather, may comprise an uneven topography. Feature pattern density affects the result of a CMP process: isolated features may be reduced in height from the CMP process in comparison to closely nested features, for example. When additional material layers are deposited over the features having different heights, the material layers are thinner over the reduced in height isolated features than over the nested features, which can cause focus problems in subsequent lithography processes.
In BEOL lithography process, topography differences between various regions on a chip may consume a large portion of a focus budget for a material layer. Planarizing coatings used before the masking step, e.g., before a layer of photoresist is applied, may not correct topography differences. Topography differences across regions of a semiconductor device may vary by about 100 nm or greater in some applications, which may result in undesired exposure results. The varying height of the topography may result in a single best focus level being inadequate for exposure across an entire wafer, for example.
Thus, improved methods of patterning material layers of semiconductor devices are needed in the art.
The present invention will be described with respect to preferred embodiments in a specific context, namely, in methods of manufacturing semiconductor devices having uneven topographies. Embodiments of the invention may also be applied, however, to other applications that require patterning of materials having uneven topographies, for example.
Embodiments of the present invention provide novel methods of manufacturing semiconductor devices, and semiconductor devices manufactured using the novel methods. Embodiments of the present invention also include novel lithography masks and methods of manufacture thereof, and lithography systems including the lithography masks, to be described further herein.
Embodiments of the present invention will be described with respect to methods of manufacturing semiconductor devices, namely in the patterning of contacts, vias, or other conductive features of semiconductor devices using damascene processes. Embodiments of the present invention may also be used to form features comprising other materials, such as semiconductive or insulating materials, or other materials combined with these material and conductive materials. Embodiments of the invention may be implemented in semiconductor applications such as transistors, memory devices, logic devices, mixed signal devices, and other applications, as examples.
Methods of focus compensation in lithography masks for semiconductor devices with material layers having an uneven topography will be described herein. The novel methods compensate for focus requirement differences between regions of a semiconductor device having different topographies. The compensation of the uneven topography is achieved by tuning the phase of the lithography mask proximate the patterns for features that will be formed in the material layer, based on the topography in various regions of the material layer on the semiconductor device. Embodiments of the present invention utilize an effect of focus difference created by a phase shift of an attenuated phase shifting mask to compensate for topography differences of a semiconductor device, to be described further herein.
With reference now to
A chemical-mechanical polish (CMP) process is used to planarize the workpiece 102 and remove the conductive material 104 from over the top surface of the first insulating material 110a, leaving features 104 formed within the first insulating material 110a, as shown in
To pattern the second insulating material 110b, a layer of photosensitive material 112 is formed over the second insulating material 110b, as shown in
To optimize lithography processes, a top surface of a semiconductor device is required to be planar, in order for features to print as desired across the surface of the semiconductor device. However, in accordance with embodiments of the present invention, features may accurately be printed across a semiconductor device 100 such as the one shown in
Only one first region 106 and one second region 108 are shown in the drawings; however, the semiconductor device 100 (and/or the workpiece 102 or a material layer disposed over the workpiece 102) may comprise a plurality of first regions 106 and a plurality of second regions 108, for example, not shown. The second region 108 of the semiconductor device 100 is also referred to herein as at least one second region 108, for example. The second region 108 may comprise a plurality of regions, with each of the plurality of regions having a different thickness or height, for example.
Likewise, the lithography mask 120 may comprise a plurality of first regions 126 and a plurality of second regions 128, also not shown. The second region 128 of the lithography mask 120 is also referred to herein as at least one second region 128, for example. The second region 128 may comprise a plurality of regions, with each of the plurality of regions having a different phase shift to compensate for the different thicknesses or heights of the second regions 108 of the semiconductor device 100, for example.
The first region of the lithography mask 120 may correspond with the first region of the semiconductor device 100. The first region of the lithography mask 120 may be used to pattern the first region of the semiconductor device 100, for example.
After providing the novel lithography mask 120 comprising a first phase shift Φ1 in the first region 106 and at least one second phase shift Φ2 in the at least one second region 128, the layer of photosensitive material 112 is exposed to energy through the lithography mask 120. The layer of photosensitive material 112 is developed, leaving portions of the workpiece 102 exposed (not shown in
In some embodiments, affecting the portions of the workpiece 102 may comprise etching away the exposed portions of the workpiece 102, (e.g., second insulating material 110b) which will be described further herein with reference to the embodiment shown in
Next, the lithography mask 120 shown in
The attenuated phase shifting material 124 may comprise a partially transmissive material such as MoSi, although other attenuating materials may also be used for the attenuated phase shifting material 124. The attenuated phase shifting material 124 may comprise a thickness of about 100 nm, or about 300 nm or less, as examples, although the attenuated phase shifting material 124 may alternatively comprise other dimensions.
The attenuated phase shifting material 124 comprises patterns in the first region 126 and the at least one second region 128 of the lithography mask 120, as shown. The patterns may comprise a pattern for a plurality of vias or other features of the semiconductor device 100, for example. The patterns in the attenuated phase shifting material 124 will be used to pattern the layer of photosensitive material 112, which may be used as a mask to form features on the semiconductor device 100 or to alter the semiconductor device 100 in the shape of the patterns.
The patterns for the features in the first region 126 of the mask 120 and the at least one second region 128 preferably comprise the same size or dimensions in some embodiments, for example. Alternatively, the patterns for the features in the first region 126 and the at least one second region 128 may comprise different sizes and dimensions.
The lithography mask 120 comprises a first phase shift Φ1 in the first region 126 and at least one second phase shift Φ2 in the at least one second region 128. The different phase shifts Φ1 and Φ2 in regions 126 and 128 of the mask 120 cause different focus levels to be emitted from the lithography mask 120 when it is used during an exposure process of a semiconductor device 100. Thus, the lithography mask 120 advantageously provides a means of tuning the focus levels for different regions 106 and 108 of the semiconductor device 100, providing the ability to expose a semiconductor device at a variety of focus levels in a single exposure process.
The phase shifts Φ1 and Φ2 in the first region 126 and the at least one second region 128 of the lithography mask 120 may be achieved by varying the thickness of the substrate 122, as shown in
Alternatively, the phase shifts Φ1 and Φ2 in the first region 126 and/or the at least one second region 128 of the lithography mask 120 may be achieved by modifying the refractive index of the substrate 122 and/or the attenuated phase shifting material 124 proximate the patterns in the first region 126 and the at least one second region 128. For example, the substrate 122 or the attenuated phase shifting material 124 of the lithography mask 120 may be implanted with ions or atoms of a substance, such as potassium, although other substances may also be used, to modify the optical characteristics of the mask 120 in the desired area. The attenuated phase shifting material 124 or the substrate 122, or both the attenuated phase shifting material 124 and the substrate 122 may include an implanted substance adapted to produce the first phase shift or the at least one second phase shift of the lithography mask 120, for example.
The phase shifts Φ1 and Φ2 in regions 126 and 128 are intentionally varied in accordance with embodiments of the present invention, to provide custom focus levels for regions 106 and 108 of the workpiece 102, providing improved lithography processes, wherein optimal focus levels are achievable for different regions 106 and 108 of the semiconductor device 100.
For example,
For example, in
The thicknesses of the attenuated phase shifting material 224 in regions 226 and 228 may comprise dimensions d5 and d6 such that an amount of phase shifts Φ1 and Φ2 in the first region 226 and the at least one second region 228 comprise a desired focus level depending on the topography of the semiconductor device 100 in the first region 106 and the second region 108. The amount of the phase shifts Φ1 and Φ2 in regions 226 and 228 of the lithography mask 220 is also referred to herein as a background phase shift of the regions 226 and 228 of the lithography mask 220, for example.
The first thickness comprising dimension d5 and the at least one second thickness comprising dimension d6 of the attenuated phase shifting material 224 may be determined using Equation 1 in some embodiments:
wherein T comprises the first thickness d5 or the at least one second thickness d6, wherein PS is the amount of the phase shift Φ1 or Φ2 in the first region 226 or the at least one second region 228 in degrees, wherein λ comprises a wavelength of an exposure process used to pattern a photosensitive material of a semiconductor device 100 (e.g., the layer of photosensitive material 112 shown in
In the embodiment shown in
In this embodiment, the phase shifts Φ1 and Φ2 in regions 326 and 328 of the lithography mask 320 are created by varying the thickness of the substrate 322 of the mask 320. For example, in
A method of manufacturing a semiconductor device 100 in accordance with an embodiment of the present invention will next be described.
Referring next to
The workpiece 102 comprises a material layer 130 to be patterned disposed thereon, as shown, wherein the material layer 130 has an uneven topography (e.g., which may be formed as described for the embodiment shown in
The material layer 130 comprises an insulating material layer in the embodiment shown in
Next, a layer of photosensitive material 112 is formed over the workpiece 102, e.g., over the material layer 130, as shown. The layer of photosensitive material 112 may comprise a photoresist such as a negative or positive photoresist, for example. An optional anti-reflective coating may be formed on the workpiece 102 before the layer of photosensitive material 112 is deposited, not shown. The layer of photosensitive material 112 may be conformal, having substantially the same or similar uneven topography as the material layer 130.
Referring next to
A lithography system is used to expose the layer of photosensitive material 112 over the workpiece 102 and the first material layer 130 to energy (e.g., such as light or energy) through the lithography mask 120 shown in
Next, the layer of photosensitive material 112 is developed, forming patterns in the layer of photosensitive material 112, as shown in
In some embodiments, the apertures 132 for features formed in the material layer 130 may comprise a minimum feature size or critical dimension (CD) of the lithography system or process used to pattern the apertures 132 for the features. Alternatively, the apertures in the material layer 130 may comprise dimensions larger than a minimum feature size, for example.
In a dual damascene process, a second lithography mask may be used to pattern additional feature apertures or trenches in an upper portion of the first material layer 130, as shown in phantom in
A second material layer 136 is formed over the first material layer 130, as shown in
The second material layer 136 may comprise a conductive material in the embodiment shown, to form conductive features within the first material layer 130. The conductive material may comprise copper, a copper alloy, aluminum, an aluminum alloy, tungsten, a tungsten alloy, one or more liner or seed layers, or combinations thereof, as examples, although alternatively, the conductive material may comprise other materials.
Alternatively, the second material layer 136 may comprise an insulating material, a semiconductive material, a conductive material, or multiple layers or combinations thereof, for example. The second material layer 136 may comprise at least one liner, at least one seed layer, at least one metal, at least one semiconductive material, or combinations thereof, as examples, in some embodiments.
A CMP and/or etch process may be used to planarize the semiconductor device 100 top surface, e.g., the top surface 128 of the first material layer 130, removing excess portions of the second material layer 136 from over the top surface 128 of the first material layer 130 and forming features 138a, 138b, and 138c, as shown in
The known or expected topography differences of a semiconductor device 100 may be used to determine a best focus for each topography dimension, and a background focus shift Φ1 or Φ2 may be determined to achieve the best focus for each topography dimension in regions 106 and 108 of a semiconductor device 100 in accordance with embodiments of the present invention.
Embodiments of the present invention provide novel methods of compensating for focus level differences between topographies across a surface of a semiconductor device 100, which can be predicted from upstream processes such as CMP processes and fill layer coatings. The varying focus levels are achieved by tuning the phase shift Φ1 and/or Φ2 of the lithography mask 120, 220, and 320 proximate or around the patterns for vias or other features on the masks 120, 220, 320, based on the simulated or expected topography of material layers below the vias or features.
The underlying material layer topography differences may be caused by varying circuit or feature densities, which may comprise a predictable uneven topography, e.g., after processing steps such as CMP processes. The topography unevenness may be simulated by correlating pattern density effects with the CMP process, for example. The topography information on the wafer may also obtained by measurements made by sensors in the lithography exposure tool, for example. The information obtained from the topography simulations or measurements may be used to create a lithography mask 120, 220, and 320 having the optimal phase shifts Φ1 and Φ2 for the topography measured, in accordance with embodiments of the present invention.
For example, if there is a low or decreased topography in a second region 108 of a semiconductor device 100, a phase shift Φ2 of a second region 128, 228, or 328 of a lithography mask 120, 220, or 320 may be chosen that is less than about 180 degrees in order to achieve a best focus for features to be formed in the second region 108 of the semiconductor device 100, as an example.
Embodiments of the present invention include methods of manufacturing semiconductor devices 100 and semiconductor devices 100 manufactured using the methods described herein. Embodiments of the present invention include lithography masks 120, 220, and 320 including the varying phase shift regions 126, 128, 226, 228, 326, and 328, and lithography systems including and utilizing the novel lithography masks 120, 220, and 320 described herein. Embodiments of the present invention also include methods of fabricating the novel lithography masks 120, 220, and 320 described herein, for example.
Advantages of embodiments of the present invention include providing novel lithography masks 120, 220, and 320 and processes that utilize an effect of focus shift difference created by a phase shift Φ1 and/or Φ2 of a lithography mask 120, 220, or 320, e.g., caused by varying phase shifts Φ1 and/or Φ2 of the attenuated phase shift material 124, 224, or 324 or substrate 122, 222, or 322 of the mask 120, 220, or 320. A single mask 120, 220, or 320 and a single exposure process may be used to pattern features of a semiconductor device 100 that has an uneven topography, with a best focus level being achieved for all topographies of the semiconductor device 100.
A common depth of focus target for via layers is achievable in accordance with embodiments of the present invention. The variable phase shift attenuated phase shift masks 120, 220, or 320 described herein may be used to achieve a common focus for vias on varying topographies in a via first dual damascene scheme, for example.
Exposing the first region 106 of a material layer 130 at a first focus level of energy using a first region 126 of a lithography mask 120 and exposing a second region 108 of a material layer 130 at a second focus level of energy using a second region 128 of a lithography mask 120 may comprise achieving common depth of focus targets for vias 138a formed in the first region 106 of a workpiece 102 and vias 138b and 138c formed in the second region 108 of the workpiece 102, for example.
Alternatively, embodiments of the present invention described herein may be implemented in single damascene structures.
The novel methods, lithography masks 120, 220, or 320 and systems described herein are advantageously easily implemented into existing manufacturing process flows, lithography mask designs, and lithography tools and systems, with few additional processing steps being required for implementation of the invention, for example.
Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
