Patent Application
20100308418
The present invention relates generally to semiconductor devices, and more particularly to the fabrication of transistors.
Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon.
A transistor is an element that is used frequently in semiconductor devices. There may be millions of transistors on a single integrated circuit (IC), for example. A common type of transistor used in semiconductor device fabrication is a metal oxide semiconductor field effect transistor (MOSFET), as an example. A transistor typically includes a gate dielectric disposed over a channel region in a substrate, and a gate electrode formed over the gate dielectric. A source region and a drain region are formed on either side of the channel region within the substrate.
Complementary metal oxide semiconductor (CMOS) devices include both p-channel and n-channel transistors, e.g., a p-channel metal oxide semiconductor (PMOS) transistor and an n-channel metal oxide semiconductor (NMOS) transistor, arranged in complementary configurations. The PMOS and NMOS transistors of CMOS devices in many applications require symmetric threshold voltages (Vt), e.g., where the threshold voltages of the PMOS and NMOS transistors have equal yet opposite magnitudes. Manufacturing CMOS devices requires additional manufacturing steps and material layers to tune the threshold voltages of the PMOS and NMOS transistors, and is therefore more costly and complex than manufacturing a single type of transistor.
Thus, what are needed in the art are improved methods of fabricating semiconductors having two or more types of transistors and structures thereof.
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by embodiments of the present invention, which provide novel methods of manufacturing semiconductor devices and structures thereof.
In accordance with one embodiment, a semiconductor device includes a first transistor in a first region of a workpiece. The first transistor includes a gate dielectric and a cap layer disposed over the gate dielectric. The first transistor includes a gate including a metal layer disposed over the cap layer and a semiconductive material disposed over the metal layer. The semiconductor device also includes a second transistor in a second region of the workpiece. The second transistor includes the gate dielectric and the cap layer disposed over the gate dielectric. The second transistor includes a gate that includes the metal layer disposed over the cap layer and the semiconductive material disposed over the metal layer. A thickness of the metal layer, a thickness of the semiconductive material, an implantation region of a channel region, or a doped region of the gate dielectric of the first transistor achieves a predetermined threshold voltage for the first transistor.
The foregoing has outlined rather broadly the features and technical advantages of embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
As features of semiconductor devices are decreased in size, as is the trend in the semiconductor industry, it becomes important to avoid or minimize depletion effects of transistor gate electrodes. Depletion effects may restrict the formation of an inversion layer and thus may limit electrical performance of a semiconductor device. To avoid depletion effects, additional material layers have begun to be implemented in gate stacks of transistors.
For example, one recent trend in CMOS devices is the use of a high dielectric constant (k) material as a gate dielectric combined with the use of a metal gate material. However, to achieve the desired band-edge work functions and tune the threshold voltages of high k/metal gate CMOS devices, complex gate stacks and processing are required. The use of a thin single capping layer on top of the high k gate dielectric material of the NMOS transistor is known to shift the NMOS transistor work function to the band edge. The capping layers used on NMOS transistors are typically lanthanide series-based metals or metal-oxides. However, in this approach, the capping layer is required to be stripped from the PMOS transistors, which can cause problems.
Another approach for tuning threshold voltages of high k/metal gate CMOS devices is to use two independently integrated cap layers: lanthanide-based metal or metal oxide cap layers for the NMOS transistors and aluminum-based cap layers for the PMOS transistors, as examples. This approach results in stacked cap layers on the NMOS transistors and a single cap layer on the PMOS transistors, together with multiple metal layers for the PMOS transistor gates. The multiple metal layers of the PMOS transistor gate create several interfaces in the gate stack, add a great amount of complexity and cost to the process flow, and result in gate stacks of the PMOS and NMOS transistors having different final heights.
Thus, improved methods of tuning the threshold voltages of transistors of semiconductor devices are needed in the art.
Embodiments of the present invention provide novel methods of fabricating transistor devices, wherein threshold voltage levels are established and tuned for multiple transistors across a surface of a semiconductor device. A single cap layer comprising an aluminum-containing material or TiOxNy is formed on both the PMOS and NMOS transistors of a CMOS device. The manufacturing process requires fewer processing steps and a less complex process flow. Only one cap layer is required, and multiple metal layers are not required in the PMOS transistor gates. The cap layer establishes the threshold voltage of the PMOS transistors, and the threshold voltage of the NMOS transistors is established or adjusted using a thickness of a gate material layer, an implantation process of a channel region of the NMOS transistors, and/or a doped region of a gate dielectric of the NMOS transistors, to be described further herein.
The present invention will be described with respect to preferred embodiments in specific contexts, namely implemented in semiconductor devices including a plurality of NMOS or PMOS transistors. Embodiments of the invention may be implemented in semiconductor applications such as memory devices, logic devices, CMOS devices, and other applications that utilize transistor devices, for example.
The gate dielectric 108 of both transistors 124 and 126 may comprise a first insulating layer 110 and a second insulating layer 112 disposed over the first insulating layer 110. The second insulating layer 112 may include an optional doped region in the first transistor 124 for tuning the threshold voltage of the first transistor 124. A cap layer 114 is disposed over the gate dielectric 108 of the transistors 124 and 126.
The gates 116 of the transistors 124 and 126 comprise a metal layer 118 disposed over the cap layer 114 and a semiconductive material layer 120 disposed over the metal layer 118. The thickness d1 of the metal layer 118 of the first transistor 124 may comprise a different thickness or the same thickness as the thickness d2 of the metal layer 118 of the second transistor 126. The thickness d3 of the semiconductive material layer 120 of the first transistor 124 may comprise a different thickness or the same thickness as the thickness d4 of the semiconductive material layer 120 of the second transistor 126.
In accordance with embodiments of the present invention, the thickness and material selection of the cap layer 114 is used to establish the threshold voltage (Vt) of the second transistor 126 in the second region 106. The threshold voltage of the first transistor 124 in the first region 104 may be tuned or established using the implantation region 123 in the channel region, by altering the thickness d1 of the metal layer 118 of the gate 116, by altering the thickness d3 of the semiconductive material 120 of the gate 116, by forming a doped region in the second insulating layer 112 of the dielectric material 108, or one or more combinations thereof. One or more of these four features of the first transistor 124 may be altered to achieve a predetermined threshold voltage, e.g., a desired threshold voltage for the first transistor 124, depending on the application, for example.
The workpiece 102 comprises a first region 104 and a second region 106 in which a first transistor 124 and a second transistor 126, respectively (see
A plurality of isolation regions 140 are formed in the workpiece 102, as shown in
As one example, the isolation regions 140 may be formed by depositing a hard mask (not shown) over the workpiece 102 and forming trenches in the workpiece 102 and the hard mask using a lithography process. The isolation regions 140 may be formed by depositing a photoresist over the hard mask, patterning the photoresist using a lithography mask and an exposure process, developing the photoresist, removing portions of the photoresist, and then using the photoresist and/or hard mask to protect portions of the workpiece 102 while other portions are etched away, forming trenches in the workpiece 102. The photoresist is removed, and the trenches are then filled with an insulating material such as an oxide or nitride, or multiple layers and combinations thereof, as examples. The hard mask may then be removed. Alternatively, the isolation regions 140 may be formed using other methods and may be filled with other materials.
The workpiece 102 may be implanted with well regions, e.g., using As, B, P, or other dopant materials in the first region 104, the second region 106, the third region 144, and the fourth region 146. Portions of the workpiece 102 may be masked while each region or groups of regions 104, 106, 144, or 146 are implanted with dopants to form the particular well regions required for the various types of transistors 124, 126, 154, and 156 to be fabricated in each region 104, 106, 144, and 146, for example. The well region implantation processes may be adjusted or selected to tailor or affect the threshold voltages of transistors 124, 126, 154, and 156 to be fabricated in each region 104, 106, 144, and 146, in some embodiments, for example. Hard masks and/or photoresists (not shown) used during the implantation of the well regions are then removed.
An optional dielectric layer 148 may be formed over the workpiece 102 and isolation regions 140, if the semiconductor device 100 will include third and fourth transistors 154 and 156 in the third and fourth regions 144 and 146, as shown in
The optional dielectric layer 148 is removed from the first region 104, the second region 106, and other regions where the dielectric layer 148 is not required using lithography, as shown in
An optional implantation process 150 may be used to implant the workpiece 102 with a substance in the first region 104, as shown in
A first insulating layer 110 is formed over the workpiece 102 in the first region 104 and the second region 106, and over the dielectric layer 148 in the third region 144 and the fourth region 146, as shown in
A second insulating layer 112 is deposited over the first insulating layer 110, if present, or over the workpiece 102, if the first insulating layer 110 is not included. The second insulating layer 112 may comprise at least one high k dielectric material layer comprising hafnium, for example, although alternatively, other high k dielectric materials may also be used. The second insulating layer 112 may comprise about 50 Å or less of a high-k dielectric material having a dielectric constant or k value of greater than about 3.9, such as a hafnium-based dielectric material (e.g., HfSiON, HfO, or HfSiO), a doped hafnium-based dielectric material, a Zr-based dielectric material, TiO2, Ta2O5, Sc2O3, Y2O3, CeO2, LaAlO3, SrTiO3, SrZrO3, BaTiO3, other high-k dielectric materials, or combinations and multiple layers thereof, as examples. Alternatively, the second insulating layer 112 may comprise other dimensions and materials, for example. The second insulating layer 112 may be formed using thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), or jet vapor deposition (JVD), as examples, although alternatively, other methods may also be used to form the second insulating layer 112.
An optional doping process may be used to dope the insulating layer 112 in the NMOS region, e.g., in the first region 104, with a lanthanide series-based metal to tune the work-function of the first transistor 124 in the first region 104. A masking material such as a photoresist may be formed over the workpiece 102, and the masking material may be patterned to expose the first region 104, for example, not shown. The doping process may comprise an ion implantation and/or diffusion process, for example. The lanthanide series-based metal may comprise La, LaO, or other metals or metal oxides, as examples. The lanthanide series-based metal may be implanted and then the semiconductor device 100 may be annealed to diffuse the lanthanide series-based metal into the high k dielectric material of the second insulating layer 112, for example. The optional doped region in the second insulating layer 112 of the first transistor 124 may be used to tune the work function of the first transistor 124 in some embodiments, for example. Alternatively, the optional doped region of the second insulating layer 112 of the first transistor 124 in the first region 104 may not be included.
A cap layer 114 is then formed over the second insulating layer 112, as shown in
The type of material and the thickness of the cap layer 114 has an effect on the threshold voltage of the second transistor 126 formed in the second region 106. In some embodiments, the cap layer 114 material and thickness is selected to achieve or establish a predetermined threshold voltage for the second transistor 126. The cap layer 114 material and thickness also may have an effect on the threshold voltages of other transistors 124, 154, and 156 formed in the first region 104, second region 144, and third region 146. Other parameters of the transistors 124, 154, and 156 may be altered to offset or accommodate for the effect of the cap layer 114 on the threshold voltages, such as by forming implantation region 123 (see
The thickness of the cap layer 114 may be the same for all transistors 124, 126, 154, 156 formed in the first region 104, second region 106, third region 144, and fourth region 146 of the workpiece 102 in some embodiments. The thickness of the cap layer 114 may optionally be different for p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) transistors of the semiconductor device 100, not shown in the drawings. For example, the cap layer 114 may be deposited over the entire workpiece 102, and the workpiece 102 may be masked while a top portion of the cap layer 114 is removed in some regions 104, 106, 144, or 146. Alternatively, the cap layer 114 may be thickened in some regions of the workpiece 102, by depositing or growing additional cap layer 114 material while other regions are masked.
A metal layer 118 is formed over the cap layer 114, as shown in
In some embodiments, the metal layer 118 may comprise the same thickness for all of the transistors 124, 126, 154, and 156 formed in the first region 104, second region 106, third region 144, and fourth region 146, respectively, of the workpiece 102. However, in other embodiments, the thickness of the metal layer 118 may be different for at least one transistor 124, 126, 154, 156 formed in the first region 104, second region 106, third region 144, or fourth region 146, respectively, of the workpiece 102. In the embodiment shown in
In some embodiments, the thickness d1 of the metal layer 118 of the first transistor 124 in the first region 104 may be reduced, to tune the threshold voltage of the first transistor 124 due to the presence of the cap layer 114 which is used to tune the second transistor 126 in the second region 106, for example (see
Referring again to
Next, a semiconductive material 120 is formed or deposited over the metal layer 118, as shown in
In some embodiments, the semiconductive material 120 may comprise the same thickness for all of the transistors 124, 126, 154, 156 formed in the first region 104, second region 106, third region 144, and fourth region 146, respectively, of the workpiece 102, not shown. However, in other embodiments, the thickness of the semiconductive material 120 may be different for at least one transistor 124, 126, 154, 156 formed in the first region 104, second region 106, third region 144, or fourth region 146, respectively, of the workpiece 102. In the embodiment shown in
In some embodiments, the thickness d3 of the semiconductive material 120 of the first transistor 124 in the first region 104 may be increased, to tune the threshold voltage of the first transistor 124 due to the presence of the cap layer 114 which is used to tune the second transistor 126 in the second region 106, for example (see
To achieve different thicknesses d3 and d4 for the transistors 124 and 126 and transistors 154 and 156, respectively, the nature of the deposition process of the semiconductive material 120 may be used in some embodiments. For example, in
In some embodiments, the transistors 124, 126, 154, and 156 comprise gates 116 comprised of the metal layer 118 and the semiconductive material 120 that have coplanar top surfaces, as shown in
The thicknesses d3 and d4 of the semiconductive material 120 have an effect on the threshold voltage of the transistors 124, 126, 154, and 156. The different thicknesses d3 and d4 of the semiconductive material 120 result in a change in or a tuning of the threshold voltage values of the transistors 124, 126, 154, and 156 to achieve or establish predetermined threshold voltages for the transistors 124, 126, 154, and 156.
After the deposition of the semiconductive material 120 of the gates 116 of the transistors 124, 126, 154, and 156, the material stack comprised of the semiconductive material 120, metal layer 118, cap layer 114, insulating layers 112 and 110, and dielectric layer 148 is patterned using lithography, as shown in
Transistors 124 and 126 may comprise different types of transistors than transistors 154 and 156. Transistors 154 and 156 may comprise higher voltage transistors than transistors 124 and 126, for example. Transistors 154 and 156 have a gate dielectric 108 comprising dielectric layer 148, second insulating layer 112, and first insulating layer 110 that is thicker than the gate dielectric 108 of transistors 124 and 126 comprising only the first and second insulating layers 110 and 112. Transistor 124 may comprise an NMOS transistor having a threshold voltage of about +300 mV or less or more, and transistor 126 may comprise a PMOS transistor having a threshold voltage of about −300 mV or less or more, as an example. Transistor 154 may comprise an NMOS transistor having a different threshold voltage than +300 mV, and transistor 156 may comprise a PMOS transistor having a different threshold voltage than -300 mV, as an example. The difference in threshold voltage magnitudes between transistors 124 and 126, and transistors 154 and 156, may range from about 50 mV to about 500 mV. The threshold voltage differences of the transistors 124 and 126 and transistors 154, and 156 may alternatively range by other values, depending on the applications.
The transistors 124 and 126 or transistors 154 and 156 may comprise a number of different threshold voltage transistor types. Additional transistor types may also be formed on the semiconductor device 100. The transistors 124 and 126 or 154 and 156 may comprise high voltage transistor devices having a threshold voltage of about 500 mV, medium voltage transistor devices having a threshold voltage of about 300 mV, low voltage transistor devices having a threshold voltage of about 100 mV, super-low voltage transistor devices having a threshold value of less than about 50 mV, and/or zero voltage transistor devices (also not shown) having a threshold value of about 0 mV, as examples. Alternatively, the threshold voltage ranges of the transistors 124 and 126 or 154 and 156 may comprise other values.
In some embodiments, substantially symmetric threshold voltages of transistors 124 and 126 of the semiconductor device 100 are achieved. Transistor 124 may comprise a threshold value of about +300 mV, and transistor 126 may comprise a threshold voltage of about −300 mV, as an example. Likewise, transistors 154 and 156 may comprise substantially symmetric threshold voltages. Alternatively, transistors 124, 126, 154, and 156 may be formed that have substantially asymmetric threshold voltages, in other embodiments.
After the material stack 120, 118, 114, 112, and 110 is patterned, first sidewall spacers 160/162 are formed on the sidewalls of the material stack 120, 118, 114, 112, and 110. The first sidewall spacers 160/162 may comprise a first layer 160 comprising a nitride such as silicon nitride and a second layer 162 comprising an oxide such as silicon dioxide, as examples. Alternatively, the first sidewall spacers 160/162 may comprise other insulating materials. Shallow implantation regions 164 are implanted into the workpiece 102 in the first region 104 and the second region 106. Second sidewall spacers 166 are formed over the first sidewall spacers 160/162, as shown. Deep implantation regions 168 are then implanted into the workpiece 102 in the first region 104 and the second region 106. The implantation regions 164 and 168 function as source and drain regions 164/168 of the transistors 124 and 126.
Insulating material layers and conductive material layers may be formed over the semiconductor device 100 and patterned to complete the fabrication process. Metallization layers (not shown) may be formed that make electrical contact to the source and drain regions 164/168 and gates 116 and interconnect the various components of the semiconductor device 100. Contacts and bond pads may be coupled to the conductive material layers, and individual die of the workpiece 102 may be singulated and packaged, for example, not shown.
Embodiments of the present invention include semiconductor devices 100 manufactured using the methods described herein. Embodiments of the present invention also include methods of fabricating the semiconductor devices 100 described herein.
Embodiments of the present invention have useful applications in semiconductor device 100 designs that require multiple transistors having various threshold voltages across the surface of a workpiece 102. For example, embodiments of the present invention are advantageous when used in designs that require the use of low leakage transistors, which require high threshold voltages, and also fast transistors, which require a low threshold voltage, on a single chip, for example. Other transistors may also be formed on the same chip having regular or medium levels of threshold voltage, for example, using embodiments of the present invention described herein.
Advantages of embodiments of the present invention include providing novel methods of forming semiconductor devices 100 and structures thereof. Novel methods of tuning and adjusting threshold voltages and work functions of transistors 124, 126, 154, and 156 are described herein. Fewer mask levels and processing steps are required to form transistors 124, 126, 154, and 156 of a semiconductor device 100 that have tunable threshold voltages. Because the cap layer 114 is included in the material stack of all transistors 124, 126, 154, and 156 formed on the semiconductor device, damage to the gate dielectric 108 is avoided. Embodiments of the present invention are easily implementable into existing manufacturing process flows, with a reduced number of processing steps being required to fabricate the semiconductor devices 100.
Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
