Semiconductor devices in compensated semiconductor

Description

TECHNICAL AREA

[0003] The present invention relates to semiconductor devices, and more particularly comprises semiconductor devices formed in fully or partially compensated semiconductor regions of substrates, including semiconductor devices which contain junctions that rectify when the semiconductor is doped either N or P-type by either metallurgical or field induced means, optionally including similar means for limiting parasitic current flow. A preferred embodiment is formed in substantially compensated semiconductor and is a simple to fabricate single device which provides operational characteristics similar to conventional dual device CMOS, under described biasing schemes.

BACKGROUND

[0004] To begin, it is noted that recently Allowed Co-Pending patent application Ser. No. 09/716,046, filed Nov. 20, 2000, protects Single Device CMOS (S-CMOS)tm fabricated in partially or fully compensated semiconductor substrates. This Application is to expand protection more generally to semiconductor devices which are fabricated in partially or fully compensated regions of semiconductor in substrates or epi-layers on substrates.

[0005] Continuing, MOSFETS, CMOS, gate voltage controlled direction of rectification, and single device inverting and single device non-inverting MOS semiconductor devices which demonstrate operating characteristics similar to those of multiple device Complementary Metal Oxide Semiconductor (CMOS) systems have been previously described in U.S. Pat. No. 5,663,584 to Welch., and said 584 Patent is incorporated hereinto by reference. Semiconductor devices described in said 584 Patent operate on the basis that materials exist which produce a rectifying junction with semiconductor channel regions when they are doped either N or P-type, whether said doping is achieved via metallurgical or field induced means. Said materials typically form junctions that are termed “Schottky barrier” junctions with semiconductors, (in contrast to P-N Junction), however, said terminology is not to be considered limiting to the present invention based upon technical definitions of the terminology “Schottky barrier”, and where the terminology “Schottky barrier” junction is utilized in this Disclosure it is to be understood that it is used primarily to distinguish a junction described thereby from “P-N” junctions, and more particularly to identify junctions between a semiconductor and element(s) which are rectifying whether N or P-type Doping is present in the semiconductor, and whether said doping is present as the result of metallurgical or field induced means.

[0006] Another Patent, U.S. Pat. No. 5,760,449 to Welch describes Source Coupled Regeneratively Switching CMOS formed from a seriesed combination of N and P-Channel MOSFTES which each demonstrate the special operating characteristics of conducting significant current flow only when the Drain and Gate of a 449 Patent MOSFET are of opposite polarity, and the Gate polarity is appropriate to invert a channel region. Said 449 Patent is incorporated hereinto by reference, as is U.S. Pat. No. 6,091,128 to Welch, (which describes prevention of parasitic current flow in semiconductor substrates), and provisional Applications and Nos. 60/081,705 and 60/090,565. Also disclosed are Patents to Lepselter, U.S. Pat. No. 4,300,152; Koeneke et al., U.S. Pat. No. 4,485,550; Welch, U.S. Pat. No. 4,696,093; Mihara et al., U.S. Pat. No. 5,049,953; Homna et al. U.S. Pat. No. 5,177,568; and Nowak, U.S. Pat. No. 5,250,834. A Japanese Patent to Shirato, U.S. Pat. No. 04,056,360 is also disclosed as it describes the presence of conducting material in a MOSFET Channel region, (in contrast to a current limiting material as in the present invention).

[0007] A recently Allowed and Co-Pending Application of Welch, Serial No. Ser. No. 09/716,046 filed Nov. 20, 2000, claims a Single Device to CMOS fabricated in fully or partially Compensated Semiconductor.

[0008] A relevant article titled “SB-IGFET: An Insulated Gate Field Effect Transistor using Schottky Barrier Contacts for Source and Drain”, by Lepselter & Sze, Proc. IEEE, 56, January 1968, pp. 1400-1402, is also identified in said 584 Patent. Further, a a paper by Lebedov & Sultanov, titled “Some Properties of Chromim-Doped Silicon”, Soviet Physics, Vol. 4, No. 11, May 1971 is identified as it discusses formation of a rectifying junction by diffusion of chromium into P-type Silicon. A paper by Hogeboom & Cobbold, titled “Etched Schottky Barrier MOSFETS Using A Single Mask, Electronics Letters, Vol. 7, No. 5/6, (March 1971) is also included as it describes formation of Schottky barrier MOSFETS by deposition of Aluminum onto semiconductor. Articles which are incorported by reference hereinto, and which describe fabrication of non-scale conventional Schottky-barrier MOSFETS are “Sub-40 nm PtSi Schottky Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistors”, Wang, Snyder & Tucker, Appl. Phys. Lett., Vol. 74, No. 8, (Feb. 22, 1999); and “Experimental Investigation of a PtSi Source and Drain Filed Emission Transistor”, Synder, Helms & Nishi, Appl. Phys. Lett. 67(10) (Sep. 4, 1995). While not being a point of Patentability, it is to be understood that present invention systems whi “Sub-40 nm PtSi Schottky Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistors”, Wang, Snyder & Tucker, Appl. Phys. Lett., Vol. 74, No. 8, (Feb. 22, 1999); and “Experimental Investigation of a PtSi Source and Drain Filed Emission Transistor”, Synder, Helms & Nishi, Appl. Phys. Lett. 67(10) (Sep. 4, 1995). ch incorporate sidewall spacers, as taught in said directly foregoing references, are to be considered within the scope of the present invention as claimed. Also mentioned, and included herein by reference for general insight to semiconductor circuits and systems, is a book titled “Microelectronic Circuits” by Sedra and Smith, Saunders College Publishing, 1991. Likewise mentioned, and included herein by reference for the purpose of providing insight into semiconductor device fabrication, is a book titled “Physics and Technology of Semiconductor Devices”, by Grove, John Wiley & Sons, 1967; and a book titled “Electronic Materials Science: For Integrated Circuits in Si and GaAs”, Mayer & Lau, MacMillan, 1990.

[0009] Even in view of the cited Welch U.S. Pat. Nos. 5,663,584; 5,760,449, 6,091,128 and 6,268,636 Patents, and co-pending CIP applications derived therefrom which describe inverting and non-inverting single device equivalents to conventional CMOS, regeneratively switching N and P-Channel source coupled CMOS, and the blocking of parasitic current flows in semiconductor systems by use of material which forms rectifying junctions with either N or P-type semiconductor whether said doping is metallurgically or field induced; there remains need description of parasitic current limitation, and of single device equivalents to CMOS where essentially homogeneously distributed N and P-type metallurgical dopants are simultaneously present at substantially equal doping levels or at at different doping levels in the semiconductor in which the devices are fabricated.

[0010] More generally and to the point herein, need remains for semiconductor devices formed in partially or fully compensated regions of semiconductor epi-layers or substrates, particulary where impurity scattering is not a major concern, such as where said semiconductor devices operate based on voltage switching rather can current flow.

DISCLOSURE OF THE INVENTION

[0011] The present invention is primarily a semiconductor device in semiconductor, (present as substrate, epi-layer and functional equivalents), comprising at least one junction which is formed by introduction of typically, (though not necessarily), non-semiconductor material(s) to said semiconductor, wherein said typically non-semiconductor material(s) form a rectifying junction with either N and P-type semiconductor, whether said doping is metallurgically or field induced. Said non-semiconductor components can be any functional material(s) or dopants entered to semiconductor by, for instance, a procedure comprising vacuum deposition, ion-implantation and/or pre-deposition and diffusion, each accompanied by appropriate annealing. The semiconductor, prior to the fabrication of present invention semiconductor devices therein, is initially fully compensated (ie. substantially homogeneously contains metallurgical N and P-type dopants at substantially the same levels, or partially compensated (ie. substantially homogeneously contain metallurgical N and P-type dopants at different levels such as within two (2) or three (3) orders of magnitude of one another).

[0012] Most importantly, the present invention comprises inverting and non-inverting devices with operating characteristics similar to dual device seriesed N and P-Channel MOSFETS CMOS systems. In use said inverting and non-inverting present invention devices, comprise two oppositely facing electrically interconnected rectifying diodes in a region of a semiconductor comprising essentially homogeneously distributed N and P-type metallurgical dopants at substantially equal doping levels, or at different doping levels separated selected from a range of, for instance, 1012 to 1019 per centimeter cubed. Use of any functional c mpensated semiconductor is within the scope of the present invention. A basic feature of present invention devices is that a forward direction of rectification of each of said electrically interconnected oppositely facing rectifying diodes changes depending upon what doping type, (N or P), be it metallurgically or field induced, is present in the semiconductor. Said present invention inverting and non-inverting single device equivalents to dual device seriesed N and P-Channel MOSFETS CMOS systems further comprise gate means for field inducing effective doping type in said semiconductor, said gate means being set off from said semiconductor by insulator, and each has a non-electrically interconnected terminal. In use, different voltages are applied to the non-electrically interconnected terminals of each of the oppositely facing rectifying diodes, and a voltage between said applied different voltages, inclusive, is monitored at the electrical interconnection between said two oppositely facing rectifying diodes, which monitored voltage responds as a function of applied gate voltage. Said monitored voltage is essentially electrically isolated from said gate voltage and appears at said electrical interconnection between said two oppositely facing rectifying diodes primarily through the rectifying diode which is caused to be forward biased as a result of semiconductor “doping type” affected by said applied gate voltage. The basis of operation of said inverting and non-inverting gate voltage channel induced semiconductor devices being that said rectifying junctions are each comprised of material(s) that form a rectifying junction to semiconductor when it is doped either N or P-type by either metallurgical or field induced means.

[0013] To aide with understanding of the present invention, an embodiment of an inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, similar to that disclosed in U.S. Pat. No. 5,663,584 and continuations therefrom, is described directly herein. Said inverting gate voltage channel induced-semiconductor device is typically, though not necessarily, formed in a surface region of a single doping type, (ie. no requirement of alternating P and N-type regions), semiconductor which comprises essentially homogeneously N and P-type metallurgical dopants at substantially equal doping levels, or at different doping levels each independently selected from a range such as 1012 to 1019 per centimeter cubed; and comprises two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprises two additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates, to which semiconductor channel region effecting voltage can be applied, are associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use, application a sufficient positive voltage to said gates will attract electrons to said first and second semiconductor channel regions, and application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying, and which drain junctions are rectifying junctions. Said rectifying junctions can each be a Schottky barrier junction comprising a semiconductor and non-semiconductor component. However, any junction which performs the function required, (ie. the formed junction is rectifying when either N or P-type doping is present in the semiconductor, whether metallurgical or field induced), is within the scope of the present invention, emphasis added. And, it is specifically to be understood that such junctions can be formed by ion implantation, or diffusion procedures as reported by Lebedev and Sultanov in the reference thereby cited in the Background Section herein, which reference disclosed diffusion chromium into P-type Silicon and thereby formed rectifying junctions. (It is to be understood, that where ion implantation or diffusion etc. techniques are applied to place junction forming material(s) into a semiconductor, the resulting junctions can still be described as being Schottky barriers, perhaps not in the standard sense of being a metal directly bonded to a semiconductor, but in the sense that a material forms a rectifying junction—other than a P-N junction—in said semiconductor. Also, even where a metal is deposited onto a semiconductor, and annealing is applied to the resulting system, some diffusion of the deposited metal per se. can occur into the semiconductor or a compound can form which extends into the semiconductor, leaving the boundary between what is purely a Schottky barrier and what involves a diffusion formed junction a bit “grey”).

[0014] Continuing, in the directly following, for purposes of description, said rectifying junctions are assumed to be Schottky barrier junctions comprising semiconductor and non-semiconductor components, and a non-semiconductor component of the rectifying Schottky barrier drain junction associated with said first semiconductor channel region of said inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, is electrically interconnected with a non-semiconductor component of the rectifying Schottky barrier drain junction associated with said second semiconductor channel region, and said gates associated with the first and second channel regions are electrically interconnected. During operation the electrically non-interconnected essentially non-rectifying sourc junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region doping type in both said first and second channel regions, and thus which electrically interconnected rectifying Schottky barrier drain junction forward conducts and which does not forward conduct, thereby controlling the voltage present at the non-semiconductor components of the electrically interconnected Schottky barrier drain junctions essentially through said forward conducting rectifying semiconductor Schottky barrier junction. In said inverting gate voltage channel induced semiconductor device an increase in applied Gate voltage leads to a decrease in the voltage present at the non-semiconductor components of the electrically interconnected Schottky barrier drain junctions, which can be accessed via a junction thereto. It is to be noted that said non-semiconductor components of said Schottky barrier drain junctions are present “between” said first and second channel regions, as said term “between” is utilized herein, (ie. electrically between). (Note, special discussion of operational bias characteristics of inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, particularly when formed in essentially semiconductor comprising both N and P-type metallurgical dopants at substantially equal doping levels, (and where a constant polarity voltage source is applied across the electrically non-interconnected essentially ohmic junctions is utilized), is found in the Detailed Description of this Disclosure).

[0015] Particularly where an inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems is formed in intrinsic or substantially compensated semiconductor, the operational description is beneficially slightly revised. Said inverting gate voltage channel induced semiconductor device formed an essentially intrinsic or substantially compensated semiconductor still comprises two junctions, termed source and drain, which are separated by a first semiconductor channel region, and still further comprises two additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates, to which semiconductor channel region effecting voltage can be applied, are still associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use application of sufficient positive voltage to said gates still attracts electrons to said first and second semiconductor channel regions, and application of sufficient negative voltage to said gates still attracts holes t said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions. However, the source junctions are each essentially non-rectifying only when sufficient gate voltage induced doping is present in the channel region adjacent thereto; and the drain junctions are rectifying (Schottky barrier) junctions only when sufficient gate voltage induced doping is caused to be present in the channel region adjacent thereto. Again assuming said “potentially” rectifying junctions are Schottky barrier junctions and each comprises semiconductor and non-semiconductor components, a non-semiconductor component of the “potentially” rectifying (Schottky barrier) drain junction associated with said first semiconductor channel region is again electrically interconnected with a non-semiconductor component of the “potentially” rectifying (Schottky barrier) drain junction associated with said second semiconductor channel region, and said gates are again electrically interconnected. During operation the electrically non-interconnected “potentially” essentially non-rectifying source junctions are held at different, preferably same p larity, voltages. Said voltages can be selected from the gr up consisting of: (positive and negative with respect to ground inclusive of ground). Application of a gate voltage selected from the group consisting of: (positive and negative), affects semiconductor channel region doping type in said first and second channel regions to be a selection from the group consisting of: (essentially non-conductive essentially intrinsic and substantially compensated and doped to the same type selected from the group consisting of: (n-type and p-type), at doping levels selected from the group consisting of: (essentially equal and different in said first and second channels)). Thus is determined which electrically interconnected rectifying (Schottky barrier) drain junction forms in said otherwise essentially intrinsic or substantially compensated semiconductor and forward conducts, thereby controlling the voltage present at the non-semiconductor components of the electrically interconnected (Schottky barrier) drain junctions essentially through said formed forward conducting rectifying semiconductor (Schottky barrier) junction. The basis of operation is that essentially intrinsic or substantially compensated semiconductor is essentially non-conductive but that said (Schottky barrier) junctions associated with said first and second semiconductor channel regions are comprised of material(s) that form a rectifying junction to a semiconductor channel region when it is caused to be doped either N or P-type by field induced means. It is to be understood that the semiconductor channel region and adjacent (Schottky barrier) junction which is not forward conducting can be characterized as a selection from the group consisting of: (being an essentially essentially intrinsic or substantially compensated channel region; being functionally comprised of two regions across which voltage can drop, namely an onset of pinch-off region and an essentially essentially intrinsic or substantially compensated channel region; and being functionally comprised of three regions across which voltage can drop, namely an onset of pinch-off region, a portion of the channel region which is populated with some gate voltage induced carriers, and a reverse biased (Schottky barrier) junction). Additionally, the semiconductor channel region and adjacent (Schottky barrier) junction which is forward conducting can be characterized as comprising a doped channel region and a forward biased (Schottky barrier) junction.

[0016] Of course operation of inverting gate voltage channel induced semiconductor devices with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems formed in a lightly doped single doping type semiconductor is essentially similarly described, or finds description inherent in a combination of said foregoing descriptions of single device equivalent to CMOS formed in doped and in essentially essentially intrinsic or substantially compensated semiconductor.

[0017] A non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems is formed in a single doping type, (ie. no requirment of both N and P-type regions), semiconductor which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), or functional combinations thereof; and comprises two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprises two additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates to which semiconductor channel region effecting voltage can be applied are associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use, application a sufficient positive voltage to said gates will attract electrons to said first and second semiconductor channel regions, and application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying, and which drain junctions are rectifying (Schottky barrier) junctions. Again, for purposes of discussion, assuming the rectifying junctions are Schottky barrier junctions which each comprise a semiconductor and non-semiconductor component, in the non-inverting gate voltage channel induced semiconductor device the non-rectifying source junction associated with said first channel region and the non-rectifying source junction associated with the second channel region are electrically interconnected, and said gates associated with the first and second channel regions are electrically interconnected. During operation non-semiconductor components of electrically non-interconnected rectifying (Schottky barrier) source junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region doping type in both said first and second channel regions, and thus which electrically non-interconnected rectifying (Schottky barrier) source junction forward conducts and which does not forward conduct, thereby controlling the voltage present at the electrically interconnected essentially non-rectifying source junctions through said forward conducting rectifying (Schottky barrier) junction. In said non-inverting gate voltage channel induced semiconductor device an increase in applied Gate voltage leads to an increase in the voltage appearing at the electrically interconnected essentially non-rectifying source junctions. It is to be noted that said essentially non-rectifying source junctions are present “between” said first and second channel regions, as said term “between” is utilized herein.

[0018] Where Intrinsic or substantially compensated, (approximately equal amounts of both N and P-type metalurgical dopants present), semiconductor is utilized, the description is beneficially slightly revised. Said non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems formed in a essentially essentially intrinsic or substantially compensated semiconductor still comprises two junctions, termed source and drain, which are separated by a first semiconductor channel region, and still further comprises two additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates to which semiconductor channel region effecting voltage can be applied are still associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use, application of sufficient positive voltage to said gates still attracts electrons to said first and second semiconductor channel regions, and application of sufficient negative voltage to said gates still attracts holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each potentially essentially non-rectifying when sufficient field-induced doping is attracted into said first and second channel regions, and which drain junctions are potentially rectifying (Schottky barrier) junctions when sufficient field-induced doping is attracted into said first and second channel regions. Again assuming said potentially rectifying junctions are Schottky barrier junctions which each comprise a semiconductor and non-semiconductor component, in the non-inverting gate voltage channel induced semiconductor device the potentially non-rectifying source junction associated with said first channel region and the potentially non-rectifying source junction associated with the second channel region are electrically interconnected, and said gates associated with the first and second channel regions are electrically interconnected. During operation non-semiconductor components of electrically non-interconnected potentially rectifying (Schottky barrier) drain junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region doping type in both said first and second channel regions, and thus which electrically non-interconnected rectifying (Schottky barrier) source junction forms and forward conducts and which does not, thereby controlling the voltage present at the formed electrically interconnected essentially non-rectifying source junctions, through said forward conducting rectifying (Schottky barrier) junction. In said non-inverting gate voltage channel induced semiconductor device an increase in applied Gate voltage leads to an increase in the voltage appearing at the electrically interconnected essentially non-rectifying source junctions which form. It is to be noted that said essentially non-rectifying source junctions are present “between” said first and second channel regions, as said term “between” is utilized herein.

[0019] The basis of operation of both said inverting and non-inverting gate voltage channel induced semiconductor devices is that said (Schottky barrier) junctions are formed from said first and second semiconductor channel regions and material(s) which provide a rectifying junction t a semiconductor channel region when it is doped either N or P-type, whether said doping is achieved via metallurgical or field induced means.

[0020] In both said inverting and non-inverting gate voltage channel induced semiconductor devices the electrically interconnected drain, or electrically interconnected source, junctions comprise an essentially electrically isolated, (from said gates), terminal, and said electrical interconnection between sources, (non-inverting case), or drains, (inverting case), can be considered to be electrically interconnected to a separate or essentially integrated thereinto essentially electrically isolated terminal. In particular said “essentially electrically isolated terminal” can be an integral indistinguishable unit with an electrical interconnection between non-semiconductor components of a Schottky barrier junction which are present outside of, (ie. “between”), first and second channel regions in an inverting single device with operating characteristics similar to multiple device (CMOS) systems, or similarly, with ohmic junctions between first and second channel regions. Such an “essentially electrically isolated terminal” can also be considered to contact said electrically interconnected sources or drains by a “junction” thereto. The concept of an essentially electrically isolated terminal is identified as it provides analogy to conventional (CMOS), but as in conventional (CMOS) its discrete presence is not pivotal. Also, it is specifically noted that the word “between” does not imply a physical, geometrical direct placement of a junction or other contact, but rather refers more to an electrical continuity with junction components “outside” of both channel regions per se. For instance, a junction placed to the right or left or top or bottom of first and/or second channel regions which are located vertically one above the other, is still “between” said first and second channel regions, as it is not within said first or second channel regions. Said otherwise, any geometrical location of any channel regions, contact(s) or juncti n(s) etc., consistent with described functional operation of single device equivalents t multiple device (CMOS) is to be considered within the scope of claimed invention, emphasis added.

[0021] Continuing, an alternative description of an inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, provides that said inverting gate voltage channel induced semiconductor device be formed in a single doping type, (ie. no requirement of both N and P-type regions), semiconductor which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), or functional combinations thereof; and comprise two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprise two additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates, to which semiconductor channel region doping effecting voltage can be applied, are associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use application a sufficient positive voltage to said gates will attract electrons to said first and second semiconductor channel regions, and such that application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying, and which drain junctions are rectifying junctions. In said inverting gate voltage channel induced semiconductor device the rectifying drain junction associated with said first semiconductor channel region is electrically interconnected with the rectifying drain junction associated with said second semiconductor channel region, and said gates associated with said first and second channel

[0022] regions are electrically interconnected. During operation the electrically non-interconnected essentially non-rectifying source junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region doping type in both said first and second channel regions, and thus which electrically interconnected rectifying drain junction forward conducts and which does not forward conduct, thereby controlling the voltage present at the electrically interconnected rectifying drain junctions essentially through said forward conducting rectifying drain junction. The basis of operation of said inverting gate voltage channel induced semiconductor device is that said rectifying drain junctions associated with said first and second semiconductor channel regions thereof are comprised of material(s) that form a rectifying junction to a semiconductor channel region when it is doped either N or P-type by either metallurgical or field induced means.

[0023] An alternative description of a non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, provides that said non-inverting gate voltage channel induced semiconductor device is formed in a single doping type, (ie. no requirement of both N and P-typ regions), semiconductor which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping l vels, or essentially homogeneously simultaneously c ntaining b th N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), or functional combinations thereof; and comprises two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprises two additional junctions, termed source and drain, which are separated by a second semiconductor channel region, wherein gates, to which semiconductor channel region doping effecting voltage can be applied, are associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use application a sufficient positive voltage to said gates will attract electrons to said first and second semiconductor channel regions, and application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying, and which drain junctions are rectifying junctions. The essentially non-rectifying source junction associated with said first channel region and the essentially non-rectifying source junction associated with the second channel region are electrically interconnected, and in which said gates associated with said first and second channel regions are electrically interconnected. During operation the electrically non-interconnected rectifying drain junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region doping type in both said first and second channel regions, and thus which electrically non-interconnected rectifying drain junction forward conducts and which does not forward conduct, thereby controlling the voltage present at the electrically interconnected essentially non-rectifying source junctions through said forward conducting rectifying drain junction. The basis of operation of said non-inverting gate voltage channel induced semiconductor devices being that said rectifying drain junctions associated with said first and second semiconductor channel regions thereof are comprised of material(s) that form a rectifying junction to a semiconductor channel region when it is doped either N or P-type by either metallurgical or field induced means.

[0024] As another alternative description of a non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, said non-inverting gate voltage channel induced semiconductor device is formed in a single doping type, (ie. no requirement of both N and P-type regions), semiconductor which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), or functional combinations thereof; and comprises two junctions, termed source and drain, which are separated by a semiconductor channel region, wherein a gate, to which semiconductor channel region doping effecting voltage can be applied, is associated with said semiconductor channel region, said gate being offset from said semiconductor channel region by insulating material. During use application a sufficient positive voltage to said gate will attract electrons to said semiconductor channel region, and application of sufficient negative voltage to said gate will attract holes to said semiconductor channel region, the purpose of applying such gate voltage being to affect the effective doping type of said semiconductor channel region between said source and drain junctions, which source and drain junctions are both rectifying junctions. Said non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems further comprises an electrical contact to said channel region. During operation the rectifying source and drain junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region doping type in said channel region, and thus which rectifying junction forward conducts and which does not forward conduct, thereby controlling the voltage present at the electrical contact to said channel region essentially through said forward conducting rectifying junction. Again, the basis of operation of said non-inverting gate voltage channel induced semiconductor device being that said rectifying junctions associated with a semiconductor channel region are comprised of material(s) that form a rectifying junction to semiconductor channel region when it is doped either N or P-type by either metallurgical or field induced means.

[0025] Another description of the present invention inverting and non-inverting devices with operating characteristics similar to dual device seriesed N and P-Channel MOSFETS CMOS systems provides that in use, two oppositely facing electrically interconnected rectifying diodes in essentially intrinsic, or substantially compensated, or a single doping type, (ie. no requirement of both N and P-type regions), semiconductor which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), and functional combinations thereof; and are f rmed, each of said electrically interconnected rectifying diodes having an accessible terminal. A forward direction of rectification of each of said electrically interconnected rectifying diodes changes depending upon what doping type, (N or P), be it metallurgically or field induced, is present in the semiconductor, said inverting and non-inverting single device equivalents to dual device seriesed N and P-Channel MOSFETS CMOS systems further comprises gate means for field inducing effective doping type in said semiconductor, said gate means being set off from said semiconductor by insulator; wherein, in use, different voltages are applied to each accessible terminal of each of the oppositely facing rectifying diodes, and a voltage between said applied different voltages, inclusive, is monitored at the electrical interconnection between said two oppositely facing rectifying diodes, which monitored voltage responds as a function of applied gate voltage, said monitored voltage being essentially electrically isolated from said gate voltage and appearing at said electrical interconnection between said two oppositely facing rectifying diodes primarily through the rectifying diode selected from the group consisting of: (said two oppositely facing electrically interconnected rectifying diodes), which is caused to be forward biased as a result of semiconductor doping type modulation by said applied gate voltage.

[0026] A present invention semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems can also be described as being formed in a semiconductor which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or optionally contains a single metallurgical doping type, (eg. 1012 t 1019 per centimeter cubed), and functional combinations thereof; and comprising at least one rectifying junction which is formed from non-semiconductor and semiconductor components, wherein said junction non-semiconductor component is comprised of material(s) which, in use, form a rectifying junction with either N and P-type semiconductor, whether metallurgically or field induced.

[0027] Another description of a present invention inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, provides that said inverting gate voltage channel induced semiconductor device be formed in an essentially intrinsic or substantially compensated or single doping-type, (ie. no requirement of both N and P-type regions), semiconductor and comprise two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprise two additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates, to which semiconductor channel region effecting voltage can be applied, are associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use application a sufficient positive voltage to said gates will attract electrons to said first and second semiconductor channel regions, and such that application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying when sufficient gate voltage induced doping is present in the channel region adjacent thereto, and which drain juncti ns are rectifying junctions when sufficient gate voltage induced doping is caused to be present in the channel region adjacent thereto. A rectifying drain junction associated with said first semiconductor channel region is electrically interconnected with a rectifying drain junction associated with said second semiconductor channel region, and in which said gates are electrically interconnected. During operation the electrically non-interconnected essentially non-rectifying source junctions are held at different voltages, and application of a gate voltage selected from the group consisting of: (positive and negative), affects semiconductor channel region doping type in said first and second channel regions to be a selection from the group consisting of: (essentially non-conductive essentially intrinsic and substantially compensated and doped to the same type selected from the group consisting of: (N-type and P-type), at doping levels selected from the group consisting of: (essentially equal and different)); and thus which electrically interconnected rectifying drain junction in said single doping type, (ie. no requirement of both N and P-type regions), semiconductor forms and forward conducts, thereby controlling the voltage present at the electrically interconnected rectifying drain junctions essentially through said formed forward conducting rectifying drain junction. The basis of operation is that said rectifying junctions associated with said first and second semiconductor channel regions are comprised of materials that form a rectifying junction to a semiconductor channel region when it is caused to be doped either N or P-type by either metallurgical or field induced means.

[0028] It is further noted that the described semiconductor channel region and junction which is not forward conducting is characterized by at least one selection from the group consisting of:

[0029] a. being an essentially essentially intrinsic r substantially c mpensated channel region;

[0030] b. being functionally comprised of two regions across which voltage can drop, namely an onset of pinch-off region and an essentially essentially intrinsic or substantially compensated channel region;

[0031] c. being functionally comprised of three regions across which voltage can drop, namely an onset of pinch-off region, a portion of the channel region which is populated with some gate voltage induced carriers, and a reverse biased rectifying junction.

[0032] Also, the inverting gate voltage channel induced semiconductor device semiconductor channel region and adjacent junction which is forward conducting is characterized as comprising a doped channel region and a forward biased junction.

[0033] Another description of a present invention non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, said non-inverting gate voltage channel induced semiconductor device being formed in an essentially intrinsic or substantially compensated or single doping-type, (ie. no requirement of both N and P-type regions), semiconductor and comprising two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprising two additional junctions, termed source and drain, which are separated by a second semiconductor channel region. Gates, to which semiconductor channel region effecting voltage can be applied, are associated with each of the first and second semiconductor channel regions, said gates each being offset from said first and second semiconductor channel regions by insulating material. During use application a sufficient positive voltage to said gates will attract electrons t said first and second semiconductor channel regions, and application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect the effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying when sufficient gate voltage induced doping is present in the channel region adjacent thereto, and which drain junctions are rectifying junctions when sufficient gate voltage induced doping is caused to be present in the channel region adjacent thereto. In said non-inverting gate voltage channel induced semiconductor device the potentially essentially ohmic source junction associated with said first semiconductor channel region is electrically interconnected with a the potentially ohmic source junction associated with said second semiconductor channel region, and in which said gates are electrically interconnected. During operation the electrically non-interconnected potentially rectifying drain junctions are held at different voltages, and application of a gate voltage selected from the group consisting of: (positive and negative), affects semiconductor channel region doping type in said first and second channel regions to be a selection from the group consisting of: (essentially non-conductive essentially intrinsic and substantially compensated and doped to the same type selected from the group consisting of: (n-type and p-type), at doping levels selected from the group consisting of: (essentially equal and different)); and thus controls formation of a forward conducting rectifying drain junction in said semiconductor, thereby controlling the voltage present at the electrically interconnected potentially ohmic source junctions essentially through said formed forward conducting rectifying junction. The basis of operation being that essentially intrinsic or substantially compensated semiconductor is essentially non-conductive but that said rectifying junctions associated with said first and second semiconductor channel regions are comprised of material(s) that form a rectifying junction to a semiconductor channel region when it is caused to be doped either N or P-type by field induced means.

[0034] The semiconductor channel region and adjacent rectifying junction which is not forward conducting is characterized by at least one selection from the group consisting of:

[0035] a. being an essentially intrinsic or substantially compensated channel region;

[0036] b. being functionally comprised of two regions across which voltage can drop, namely a portion of the channel region which is populated with some gate voltage induced carriers, and a reverse biased rectifying junction.

[0037] The semiconductor channel region and adjacent rectifying junction which is forward conducting is characterized as comprising a field induced doped channel region and a forward biased rectifying junction.

[0038] Any of the above described inverting and non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems can further comprise a voltage bias source connected across said electrically non-interconnected essentially non-rectifying source junctions so that they are held at different voltages, said voltage bias source optionally providing contact to the back of the semiconductor supporting substrate.

[0039] A present invention modulator is described as comprising in use, two oppositely facing electrically interconnected rectifying diodes in a semiconductor which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or contain a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed with no requirement of alternating N and P-type regions), and functional combinations thereof; each of said electrically interconnected rectifying diodes having an accessible terminal, wherein a forward direction of rectification of each of said electrically interconnected rectifying diodes changes depending upon what doping type, (N or P), be it metallurgically or field induced, is present in the semiconductor. Said modulator further comprises gate means for field inducing effective doping type in said semiconductor, said gate means being set off from said semiconductor by insulating material, such that during use application a sufficient positive voltage to said gate will attract electrons to said semiconductor channel region, and such that application of sufficient negative voltage to said gate will attract holes to said semiconductor channel region, the purpose of applying such gate voltage being to affect the effective doping type of said semiconductor channel region between the source and drain junctions, said source junction being essentially non-rectifying, and said drain junction being rectifying, and each of said electrically interconnected rectifying diodes having a non-electrically interconnected terminal, such that, in use, a varying voltage is applied between the non-electrically interconnected terminals of the oppositely facing rectifying diodes, and a varying voltage is monitored at the electrical interconnection between said two oppositely facing rectifying diodes, which monitored varying voltage is a modulated function of said varying voltage applied between the non-electrically interconnected terminals of the oppositely facing rectifying diodes and a varying applied gate voltage, said monitored varying voltage being essentially electrically isolated from said varying applied gate voltage and appearing at said electrical interconnection between said two oppositely facing rectifying diodes primarily through one of said oppositely facing rectifying diodes which is caused to be forward biased as a result of semiconductor doping type modulation caused by application of said varying gate voltage.

[0040] A present invention gate voltage channel induced semiconductor device with operating characteristics similar to a non-latching SCR, can be described as a gate voltage channel induced semiconductor device being formed in a semiconductor substrate which is essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels; or optionally contains a single metallurgical doping type, (eg. 1012 to 1019 per centimeter cubed), or functional combinations thereof, and comprising two junctions, termed source and drain, which are separated by a semiconductor channel region, wherein a gate, to which semiconductor channel region doping effecting voltage can be applied, is associated with said semiconductor channel region, said gate being offset from said semiconductor channel region by insulating material. During use application a sufficient positive voltage to said gate will attract electrons to said semiconductor channel region, and application of sufficient negative voltage to said gate will attract holes to said semiconductor channel region, the purpose of applying such gate voltage being to affect the effective doping type of said semiconductor channel region between the source and drain junctions, said source junction being essentially non-rectifying, and said drain junction being rectifying. Said gate voltage channel induced semiconductor device with operating characteristics similar to a non-latching SCR further comprises a source of voltage, such that during operation a voltage is applied therefrom across said source and drain junctions, and application of a gate voltage affects semiconductor channel region doping type in said channel region, and thus if said rectifying drain junction forward conducts or does not forward conduct, thereby controlling the flow of current through rectifying drain junction between reverse bias and forward bias levels. Again, the basis of operation is that said rectifying drain junction is comprised of material(s) that form a rectifying junction to a semiconductor channel region when it is doped either N or P-type by either metallurgical or field induced means.

[0041] In any of the described present invention semiconductor devices, (eg. inverting and non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, modulators and non-latching SCR's), at least one present junction (eg. source or drain), can be characterized by at least one selection from the group consisting of: (being formed in a region etched into the semiconductor, being formed by a process comprising vacuum deposition of said material(s) onto said semiconductor, being formed by a process comprising diffusion of said material(s) into said semiconductor, being formed by a process comprising ion-implantation of said material(s) into said semiconductor, and being comprised of material(s) which form a barrier height of approximately half the band-gap of the semiconductor and being formed in silicon semiconductor).

[0042] In any of the described present invention semiconductor devices, (eg. inverting and non-inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, modulators and non-latching SCR's), the semiconductor substrate can further comprise at least one region of parasitic current flow blocking material therein which is optionally physically separate from the semiconductor device and prevents parasitic currents from flowing to or away therefrom through said region of parasitic current flow blocking material; which at least one region of parasitic current flow blocking material forms rectifying junctions with both N and P-type field induced semiconductor.

[0043] It is emphasised that any of the foregoing described devices can be formed in regions of semiconductor substrates characterized by being:

[0044] said semiconductor substrate is intrinsic; or

[0045] said semiconductor substrate contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially equal doping levels, (ie. be substantially compensated); or

[0046] said semiconductor substrate contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially different doping levels; or

[0047] optionally said semiconductor substrate contains a single metallurgical doping type, or

[0048] said semiconductor substrate be lightly metallurgically doped, or

[0049] functional combinations thereof.

[0050] Continuing, it is also noted that an inverting gate voltage channel induced semiconductor device can be fabricated by a five mask procedure comprising, in a functional order, the steps of:

[0051] a. providing a silicon epi-layer or substrate selected from the group consisting of: (essentially intrinsic and substantially compensated and doped);

[0052] b. growing a depth of silicon dioxide atop thereof for use as a gate oxide adjacent to a gate voltage field induced channel region;

[0053] c. optionally implanting N or P-type channel doping regions;

[0054] d. etching two source openings through said silicon dioxide to

[0055] e. depositing aluminum atop the silicon dioxide such that it contacts the silicon through the two etched source openings;

[0056] f. etching an “8” shaped pattern around the sources through the aluminum and silicon dioxide to the silicon so that one source is present in each of said regions of said “8” shaped pattern using a second mask and photolithography techniques, (or alternatively etching only a region between the two source openings from step d.);

[0057] g. optionally continuing said etch performed in step f. into said silicon;

[0058] h. depositing a material which forms rectifying junctions with either N or P-type silicon when in contact therewith and annealed, and annealing to form rectifying junctions where said deposited material contacts said silicon;

[0059] i. by selective acid etching removing un-reacted material which was deposited in step h.;

[0060] j. delineating the sources from the gates which surround each of said sources and which are surrounded by said etched “8” pattern, said gates being the aluminum deposited in step e. and remaining present between each said source and said “8” shaped pattern using a third mask and photolithography techniques, (or alternatively around the region between the two source openings from step d.);

[0061] k. depositing insulator over the entire surface of the structure;

[0062] l. etching openings through said insulator to provide access the gates, sources and “8” shaped region, (or alternatively etching only a region between the two source openings from step d.), using a forth mask and photolithography techniques;

[0063] m. depositing aluminum over the entire surface of the deposited insulator;

[0064] n. etching said aluminum deposited in step m. to delineate two sources, “8”, (or alternatively only a region between the two source openings from step d.) and gate contact pads using a fifth mask and photolithography techniques; and

[0065] O. optionally performing a sinter anneal so that aluminum deposited in step m. and delineated into contact pads in step n. makes good electrical contact with regions etched open in step 1. to access said gates, sources and said “8” shaped region, (or alternatively only a region between the two source openings from step d.).

[0066] A simpler, three mask fabrication procedure for Inverting Single Device CMOS is:

[0067] a. providing a silicon epi-layer or substrate selected from the group consisting of: (essentially intrinsic and substantially compensated and doped);

[0068] b. growing oxide on the surface thereof for use as a gate oxide adjacent to a gate voltage field induced channel region;

[0069] c. use a first Mask to open an “8” shape through the silicon dioxide to the silicon, possibly including undercutting of the silicon dioxide, said “8” shape having width and being accessable at the midpoint between the sides of the “8” shape;

[0070] d. deposite a material, (eg. chromium), which when annealed in contact with silicon forms a junction which is rectifying with either N or P-type filed induced silicon, then anneal and then rinse off unreacted deposited, (eg. where chromium is utilized a mixture of perchloric acid and cerric ammonium nitrate and water works well);

[0071] e. using a second mask open regions inside each side of the “8” shape to the silicon, optionally including a step to rough up the silicon surface so as to enhance the ability to form an ohmic junction therewith;

[0072] f. deposit a material, (eg. aluminum) over the entire surface of the essentially intrinsic or substantially compensated silicon.

[0073] g. using a third mask delineate device regions inside each side of the “8” shape from the surrounding regions, and to delineate the material which contacts the midpoint between the sides of the “8” shape from each of the sides of the “8” shape.

[0074] A non-inverting gate voltage channel induced semiconductor device can be fabricated by a procedure comprising, in a functional order, the steps of:

[0075] a. providing a silicon epi-layer or substrate selected from the group consisting of: (essentially intrinsic and substantially compensated and doped);

[0076] b. growing oxide on the surface thereof for use as a gate oxide adjacent to a gate voltage field induced channel region;

[0077] c. optionally implanting N or P-type channel doping regions;

[0078] d. etching an “8” shaped pattern through said silicon dioxide to the silicon using a first mask and phot lithography techniques;

[0079] e. depositing aluminum atop the silicon dioxide such that it contacts the silicon through said etched silicon dioxide;

[0080] f. etching open drain regions inside each of said “8” shaped pattern regions etched open in step d. through said aluminum and silicon dioxide to the silicon using a second mask and photolithography techniques;

[0081] g. optionally continuing said etch performed in step f. into said silicon;

[0082] h. depositing a material which forms rectifying junctions with either N or P-type silicon when in contact therewith and annealed, and annealing to form rectifying junctions where said deposited material contacts said silicon;

[0083] i. by selective acid etching removing un-reacted material which was deposited in step h.;

[0084] j. delineating the gates which surround each of said drains from the surrounding etched “8” pattern, said gates being the aluminum deposited in step e. and remaining present between each said drain and said “8” shaped pattern using a third mask and photolithography techniques;

[0085] k. depositing insulator over the entire surface of the structure;

[0086] l. etching openings through said insulator to provide access said gates, drains and said “8” shaped region using a forth mask and photolithography techniques;

[0087] m. depositing aluminum over the entire surface of the deposited insulator;

[0088] n. etching said aluminum deposited in step m. to delineat two drains, “8” and gate contact pads using a fifth mask and photolithography techniques; and

[0089] O. optionally performing a sinter anneal so that aluminum deposited in step m. and delineated into contact pads in step n. makes good electrical contact with regions etched open in step 1. to access said gates, drains and said “8” shaped region.

[0090] (As for the case of the inverting gate voltage channel induced semiconductor device fabrication procedure, the “8” shaped region can be replaced by a simple opening between what are the drain openings opened in step f.).

[0091] It is to be particularly appreciated that no high cost diffusions are required in the above demonstrative, non-limiting fabrication procedures, and that only very few photolithographic masking steps are required in each. Any metallurgical doping can be entered during ingot growth. The optional ion implants, (when performed), serve to provide a channel depth region of doping and effectively form a doped semiconductor on insulator (the insulator being the essentially intrinsic or substantially compensated semiconductor region beyond the channel region), system where essentially intrinsic or substantially compensated semiconductor is initially present. It is to be understood that current flow limiting, device isolating, non-conductive essentially intrinsic or substantially compensated silicon is preferred, though not limiting, as the beginning semiconductor system for gate voltage channel induced semiconductor devices and that purely field induced doping is sufficient for operability thereof. The presence of both N and P-type dopants in a semiconductor substrate makes it easier to ionize both electrons and holes by applied Gate Voltage, with the appropriate field induced carrier being drawn into the channel region.

[0092] It is also to be understood that fabrication procedures other than those described can also be practiced to the end that present invention inverting or non-inverting gate voltage channel induced semiconductor devices are realized, and that said resulting present invention inverting or non-inverting gate voltage channel induced semiconductor devices remain within the scope of the present invention.

[0093] It is also noted that the present invention has application to semiconductor devices formed in Gallium-Arsonide, as well as in Silicon. In particular it is difficult to dope GaAs greater than about 1018 per cm3, and aluminum does not form a good ohmic junction to semiconductor doped less than about 1020 per cm3. This greatly limits realization of devices in GaAs. However, while it is difficult to form high metallurgical concentrations in N-type GaAs, it is noted that field induced concentrations can be formed in MOSFET-type channel regions, and a highly concentrated channel region adjacent to a metal contact can be driven to be essentially ohmic by application of a sufficiently high, channel region inducing, Gate voltage. The same effect, of course, is available to devices formed in Silicon, and other semiconductors.

[0094] Also, it is noted that copper or other metal can replace aluminum in the recited demonstrative, non-limiting fabrication procedures, and that additional steps can include deposition of materials to help secure deposited metals and formed silicides etc. In fact, a few percent copper in aluminum can greatly reduce electromigration effects which can degrade devices in which aluminum is used as a contact metal in semiconductor devices. Further, polysilicon, ferroelectric containing insulator and other type gates can be formed in place of metal gates in present invention semiconductor devices.

[0095] Further, the present invention comprises a semiconductor system comprising a semiconductor device in a semiconductor substrate characterized by being essentially intrinsic or lightly doped, containing a single metallurgical doping type, or preferably for the purposes of this Disclosure, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels or at different doping levels; said semiconductor device comprising at least one junction(s) selected from the group consisting of:

[0096] P-N rectifying;

[0097] Schottky barrier rectifying; and

[0098] formed from non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component of said at least one junction(s) is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; and

[0099] wherein the semiconductor system further comprises at least one region of parasitic current flow blocking material in said semiconductor substrate, which is physically separate from the semiconductor device and which serves to prevent significant parasitic currents from flowing therethrough when a voltage is present thereacross; wherein said at least one region of parasitic current flow blocking material is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether metalurigically or field induced.

[0100] Said semiconductor system comprising a semiconductor device in a semiconductor substrate can be associated with a semiconductor device which comprises a plurality of junctions arranged as, for instance, a selection from the group consisting of a-j, where said a.-j. are:

[0101] a.

[0102] being essentially ohmic; and

[0103] comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying Junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced.

[0104] b.

[0105] comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; and

[0106] comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced;

[0107] c.

[0108] being essentially ohmic;

[0109] comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semic nductor type is metallurgically or field induced; and

[0110] comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; and

[0111] being essentially ohmic;

[0112] d.

[0113] being substantially ohmic;

[0114] being rectifying;

[0115] being rectifying; and

[0116] being substantially ohmic.

[0117] e.

[0118] comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced;

[0119] being essentially ohmic;

[0120] being essentially ohmic; and

[0121] comprising non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced;

[0122] f.

[0123] being essentially ohmic; and

[0124] being rectifying P-N;

[0125] g.

[0126] being rectifying P-N; and

[0127] being rectifying P-N;

[0128] h.

[0129] being essentially ohmic;

[0130] being rectifying P-N; being rectifying P-N; and

[0131] being essentially ohmic;

[0132] i.

[0133] being rectifying P-N;

[0134] being essentially ohmic;

[0135] being essentially ohmic; and

[0136] being rectifying P-N;

[0137] j.

[0138] being rectifying; and

[0139] being rectifying.

[0140] It is specifically to be understood that a semiconductor substrate can be that which results from pulling an ingot from a melt, followed by cutting and polishing, or can comprise a Bulk and Epi-Layer, wherein the Epi-Layer contains the relevant Doping. For instance, where the terminology “Semiconductor Substrate” is used, it is to be interpreted suficiently broadly to include any functional configuration. This is emphasized where Semiconductor Devices are formed in Compensated Semiconductor, where the compensated Semiconductor comprises an entire Substrate, or an Epi-Layer region atop another portion of a Semiconductor Substrate which is made of other composition. Further, particularly where a semiconductor device is voltage switching and mobility reducing scattering is of lessened importance, the terminology “semiconductor” and/or and/or “semiconductor region” and/or substrate and the like in this Specification is to be interpreted to include both single crystal and amorphous and intermediates therebetween.

[0141] The present invention will be better understood by reference to the Detailed Description Section of this Disclosure, in conjunction with the accompanying Drawings.

SUMMARY OF THE INVENTION

[0142] It is a purpose and/or objective of the present invention to provide examples of application of material which forms rectifying junctions with either N or P-type semiconductor in combination with the presence of at least partially compensated semiconductor in an semiconductor epi-layer or substrate which comprises both N and P-type carriers to enable easy provision, and positioning N and P-type channel region forming carriers via gate voltage application effected field effect means.

[0143] It is another purpose and/or objective yet of the present invention to describe semiconductor devices, the operational basis of which relies upon the fact that certain materials form rectifying junctions with either N or P-type doped semiconductor, whether metallurgical or field induced, in a manner which compliments the description found in U.S. Pat. Nos. 5,663,584; 5,760,449, 6,091,128 and 6,268,636 to Welch.

[0144] It is a further purpose and/or objective yet of the present invention to teach simple fabrication procedures for inverting and non-inverting gate voltage channel induced semiconductor devices which have operating characteristics similar to inverting and non-inverting multiple device conventional (CMOS) systems.

[0145] It is yet another purpose and/or objective of the present invention to make clear that any rectifying or ohmic junction structure geometry, whether present in a region etched into semiconductor or not, and that any gate structure, metal or polysilicon, ferroelectric material containing insulator etc. is within the scope of present invention gate voltage channel induced semiconductor devices which have operating characteristics similar to inverting and non-inverting multiple device conventional (CMOS) systems.

[0146] It is still yet another purpose and/or objective of the present invention to describe biasing and operational characteristics of semiconductor devices which utilize materials which form rectifying junctions with either N or P-type semiconductor, and in particular to describe such operation of inverting gate voltage channel induced semiconductor devices formed in a region of a semiconductor substrate characterized by being essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, (ie. substantially compensated), or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, or containing a single metallurgical doping type at a light or heavy doping level, (eg. 1012 to 1019 per centimeter cubed), and functional combinations thereof; said semiconductor devices having operating characteristics similar to inverting multiple device conventional (CMOS).

[0147] It is a further purpose and/or objective of the present invention to make clear that the preferred embodiment thereof includes inverting and non-inverting single device equivalents to dual device seriesed N and P-Channel MOSFETS CMOS systems formed in semiconductor substrates that do not require the presence of alternating N and P-type doping regions and which comprise two oppositely facing rectifying diodes in essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, (ie. substantially compensated), or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping evels, or containing a single doping type at light or heavy metallurgical doping levels, and functional combinations thereof; wherein said rectifying diode direction of rectification changes depending upon what doping type, (N or P), be it metallurgically or field induced, is present in the semiconductor, said inverting and non-inverting single device equivalents to dual device seriesed N and P-Channel MOSFETS CMOS systems further comprising gate means for field inducing effective doping type in said semiconductor, and wherein a voltage monitored at an electrical contact between said rectifying diodes responds as a function of applied gate voltage, but is essentially electrically isolated therefrom.

[0148] It is a further purpose and/or objective still of the present invention to make clear that a semiconductor device in a semiconductor substrate, comprising at least one junction which is formed from non-semiconductor substrate and semiconductor substrate components, wherein said junction non-semiconductor substrate component is comprised of material(s) which form a rectifying junction with either N or P-type semiconductor, whether metallurgically or field induced, can be fabricated by any functional technique, (eg. procedures comprising vacuum deposition, ion-implantation and/or dopant deposition and diffusion, optionally combined with any accompanying anneals etc.), and remain within the scope of the present invention.

[0149] It is another purpose and/or objective of the present invention to describe application of material(s) which form rectifying junctions with either N or P-type semiconductor to provide modulators and non-latching SCR's in regions of semiconductor substrates characterized as essentially intrinsic, or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, (ie. substantially compensated), or essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, or containing a single doping type at light or heavy metallurgical doping levels, and functional combinations thereof.

[0150] It is yet another purpose and/or objective of the present invention to describe the prevention of parasitic current flows in semiconductor substrates containing semiconductor devices comprised of P-N or Schottky barrier junctions by placing material(s) which form rectifying junctions with either N or P-type semiconductor, whether metallurgically or field induced, in the pathway of potential parasitic current flows.

[0151] It is another purpose and/or objective yet of the present invention to make clear that where a semiconductor device is voltage switching the terminology “semiconductor” and/or and/or “semiconductor region” and/or substrate and the like in this Specification is to be interpreted to include both single crystal and amorphous and intermediates therebetween.

[0152] Other purposes and/or objectives will be evident from a reading of the Disclosure and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0153]
FIG. 1 shows a typical diffused junction (MOSFET) configuration.

[0154]
FIG. 2 shows the presence of a material in an otherwise (MOSFET) current pathway.

[0155]
FIG. 3 shows diagramatically the rectification arrangement system of the present invention where metallurgical doping controls.

[0156]
FIG. 4 shows diagramatically the rectification arrangement system of the present invention where field induced inverted doping controls.

[0157]
FIG. 5 shows a Schottky barrier (MOSFET) configuration.

[0158]

FIGS. 6

a
and 6b show a circuit symbol and side cross-sectional of a non-inverting gate voltage channel induced semiconductor single device equivalent to (CMOS).

[0159]

FIGS. 6

b
-6e show various Schottky barrier and ohmic to semiconductor junction geometries.

[0160]

FIGS. 6

f
and 6g shows two possible gate structures.

[0161]

FIGS. 7

a
and 7b show a circuit symbol and side cross-sectional of an inverting gate voltage channel induced semiconductor single device equivalent to (CMOS).

[0162]

FIGS. 7

b
-7e show various Schottky barrier and ohmic to semiconductor junction geometries.

[0163]

FIGS. 7

f
and 7g shows two possible gate structures.

[0164]
FIG. 8 shows a top view of a semiconductor system comprising an inverting gate voltage channel induced semiconductor single device equivalent, and non-inverting gate voltage channel induced semiconductor single device equivalent to (CMOS), with parasitic current flow blocking material placed therebetween in positions which might otherwise have current flow therebetween.

[0165]

FIG. 9

b
demonstrates prevention of latch-up in PNPN SCR devices.

[0167]
FIGS. 10 and 11 show operational Drain Current (ID) vs. Drain to Source Voltage (VDS), as a function of Gate Voltage (VG) for N-Channel and P-Channel (Schottky barrier MOSFETS) fabricated by the Applicant herein.

[0168]

FIGS. 12

a
and 12b show, respectively, symbols for (CMOS) comprised of N and P-Channel MOSFETS, and a typical (CMOS) switching characteristic curve as a function of Gate Voltage (VG).

[0169]

FIGS. 13

a
and 13b show two biasing schemes for an inverting gate voltage channel induced semiconductor single device equivalent to (CMOS).

[0170]

FIGS. 14

a
and 14b show two switching states for an inverting gate voltage channel induced semiconductor single device equivalent to (CMOS).

[0171]
FIG. 15 shows initial S-CMOS swtiching for a device formed in essentially intrinsic silicion using a Three Mask procedure and a junction forming energy requirement of only 450 Degrees C., for fifteen minutes.

DETAILED DESCRIPTION

[0172] Turning now to the Drawings it is noted that discussion with respect to FIGS. 1-15 provide necessary or beneficial background insight to the present invention. FIG. 1 shows a typical (MOSFET) configuration of a Semiconductor (SC), with an Insulator (I) present atop a surface thereof, atop which Insulator (I), (eg. SiO2 where the semiconductor is silicon), there is present a Gate (G) metal. Also shown, at ends of a Channel Region (CHR) present under said Gate (G), in the Semiconductor (SC), are Source Region (SR) and Drain Region (DR). In conventional Diffused Junction (MOSFETS) the Semiconductor is of a metallurgical doping type (ie. N or P-type), and the Source Region (SR) and Drain Region (DR) are both of the opposite metallurgical doping Type, (ie. P or N-type, respectively). When a voltage is applied between the Gate (G) and the Source Contact (S), and is of a polarity appropriate to invert the Semiconductor metallurgical doping type, then an “inverted” doping type channel appears in the Channel Region (CHR) and current can flow between the Drain Contact (D) and the Source Contact (S). This is as desired. (Note for general purposes that a Negative Polarity Voltage applied Gate to Source will caused accumulation of Holes in a (MOSFET) Channel Region, and that application of a Positive Polarity Voltage Gate to Source will caused accumulation of Electrons in a (MOSFET) Channel Region. Sufficient Positive Polarity Gate to Source Voltage will “Invert” a P-type Channel Region to N-type and sufficient Negative Polarity Gate to Source Voltage will “Invert” an N-type Channel Region to P-type).

[0173] While geometrically similar to what is shown in FIG. 1, FIG. 2 shows an assumed Parasitic (MOSFET) formed in a Semiconductor (SC) surface region. Shown are said Semiconductor (SC), a Parasitic Gate (PG), Parasitic Source Region (PSR) and Parasitic Drain Region (PDR), Insulator (I), and Parasitic Channel Region (PCHR). Also shown in FIG. 2 is the system of the present invention in the form of additional component Material (M) in the Parasitic Channel Region (PCHR), with associated Rectifying Regions (D1) and (D2) adjacent to left and right sides of said Material (M), in said Parasitic Channel Region (PCHR). It is important to note that said Material (M) forms junctions with the Semiconductor (SC) at two locations, (eg. (D1) and (D2)), and that said junctions are oppositely directed, (see FIGS. 3 and 4). In the preferred embodiment of the present invention said Material (M) forms rectifying junctions at Rectifying Regions (D1) and (D2), where said Semiconductor (SC) is either N or P-type because of either metallurgical or field induced doping in the Parasitic Channel Region (PCHR). It is noted that the Parasitic Gate (PG) can be an interconnection trace in an integrated circuit and that the Parasitic Source Region (PSR) and Parasitic Drain Region (PDR) can be a Source and/or Drain of intended (MOSFET's) in an integrated circuit, such as shown in FIG. 1.

[0174] The present invention can include geometries identified by FIGS. 1 and 2, where the (SR) and (DR) or (PSR) and (PDR) and (M) regions are considered to be formed by other than typical N and P-type dopants. For instance, where said (SR) and (DR) regions in FIG. 1 are considered to be doped with a Mid-Bandgap Doping Material for the semiconductor substrate (SC) present, (eg. chromium doping in (SR) & (DR) in silicon (SC)), then the basic structures of present invention non-inverting single device with operating characteristics similar to conventional diffused junction multiple device CMOS systems results. This can be appreciated by comparison of the FIG. 1 device geometry with the present invention device geometries shown in FIGS. 6b, 6c, 6d and 6e. Addition of a Midpoint (MP) to FIG. 1 so interpreted, results in said FIGS. 6b, 6c, 6d and 6e. As well, where the geometry of FIG. 2 is interpreted to have the (PSR) and (PSD) regions comprised of material(s) which form essentially ohmic contacts to the semiconductor substrate (SC) regions, and the Material (M) is a mid-bandgap doping material for the semiconductor substrate (SC) present, (eg. chromium (SR) (DR) in silicon (SC)), then one need only add a Midpoint (MP) contact to arrive at the present invention geometries of FIGS. 7b, 7c, 7d and 7e, where the (M) of FIG. 2 is the Schottky Barrier Forming Material (SBFM) of said FIGS. 7b, 7c, 7d and 7e.

[0175]
FIG. 3 shows that where the Semiconductor (PCHR) of FIG. 2 is P-type oppositely facing rectifying junctions in Rectifying Regions (D1) and (D2) have negative or cathode interconnection, and FIG. 4 shows that where the Semiconductor of FIG. 2 is N-type, oppositely facing rectifying junctions in Rectifying Regions (D1) and (D2) have positive or anode interconnection. The point being that where Material (M) is able to form a rectifying junction with either N or P-type Semiconductor, a current flow in the Parasitic Channel Region (PCHR) of FIG. 2 can not occur because regardless of the Polarity of a current flow driving voltage present between Parasitic Drain (PD) and Parasitic Source (PS), a Reverse Biased diode will appear in said Parasitic Channel Region (PCHR) at one or the other of Rectifying Regions (D1) and (D2).

[0176] It is to be understood that placing a material which forms a rectifying junction with either N or P-type semiconductor, whether metallurgically or field indiced, in a potential parasitic current flow pathway will serve to block current flow therethrough as a reverse baised junction will always appear at one side or the other of said material, regardless of the polarity of the volatge appearing thereacross. The just described approach to preventing parasitic current flow is within the scope of the present invention and is applicable in any semiconductor substrate which comprises junctions selected from the group consisting of:

[0177] P-N rectifying;

[0178] Schottky barrier rectifying; and

[0179] formed from non-semiconductor, and semiconductor substrate, components, wherein said non-semiconductor component of said at least one junction(s) is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced;

[0180] Again, where the semiconductor system further comprises at least one region of parasitic current flow blocking material in said semiconductor substrate, which is physically separate from the semiconductor device it serves to prevent significant parasitic currents from flowing therethrough when a voltage is present thereacross; wherein said at least one region of parasitic current flow blocking material is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether metalurigically or field induced.

[0181] In one sense the method of the present invention involves designing masking and fabrication procedures, and carrying out steps of fabrication, such that the Material (M) shown in the FIG. 2 Parasitic Channel Region (PCHR) is present in regions in, for instance, integrated circuits, wherein potential parasitic current flows can occur but are undesirable. (It is noted that materials which form rectifying junctions with either N or P-type semiconductor can be deposited on and annealed to a semiconductor substrate, or deposited and diffused thereinto, or ion implanted thereinto and activated by anneal etc. Any functional method by which said material(s) can be placed where desired in a semiconductor substrate can be practiced).

[0182] The present invention, as applied in parasitic current flow blocking applications, finds relevant, though not exclusive application in (MOS) systems, (eg. FIG. 1), particularly where Schottky barriers are utilized at Source (S) and Drain (D) of (MOSFETS) (eg. FIG. 5), and wherein device isolation can be problematic. Note, U.S. Pat. No. 5,663,584 to Welch describes (MOSFET) systems, (including single device equivalents to (CMOS)), which utilize Schottky barrier junctions comprised of semiconductor and a material which forms rectifying junctions with either N or P-type semiconductor material. Said 584 Patent is incorporated by reference herein and it is noted, documents conception of the principal behind the present invention as applied to parasitic current flow blocking. It is noted, however, that the 584 Patent disclosed isolation of Drain current flow in inverting single device equivalents to CMOS, particularly as regards FIG. 10q thereof, the essence of which is repeated in FIG. 8 herein. (FIG. 8 shows that device isolation can be effected by material as described). FIG. 5 herein is included to provide general non-limiting, (other possible junction geometries are as shown in FIGS. 6b-6e and 7b-7e), insight to a Schottky barrier (MOSFET) geometry configuration. The major distinction of Schottky barrier (MOSFETS) is that the Source and Drain regions comprise Schottky barrier forming material (SBFM). FIGS. 6b and 7b show, respectively, non-limiting representations of non-inverting and inverting gate voltage channel induced semiconductor single device equivalents to (CMOS), which are described in detail in the 584 Patent. The FIGS. 6b and 7b devices are shown as fabricated upon an insulating substrate (SUB), (which can comprise essentially intrinsic or substantially compensated semiconductor), and it is noted that the identifier “MP” indicates an electrically isolated Midpoint terminal similar to a midpoint of a conventional (CMOS) system. The identifier (CHR) identifies Channel Region(s), (possibly extended (SUB) essentially intrinsic or substantially compensated semiconductor with field induced doping present). Note Schottky barrier junctions in FIGS. 6b and 7b are shown as present in etched semiconductor regions. Again, the shown junctions geometry is not limiting and all junctions, both Schottky barrier and ohmic can be formed in etched semiconductor regions, or only the ohmic or rectifying junctions might be present in etched semiconductor regions. A purpose of using etched semiconductor regions is to place junctions under a Gate to avoid reduced gate voltage control over channel end field induced doping, and accompanying current flow limiting high resistance, however, a similar result can be achieved by diffusing a material into a non-etched semiconductor substrate, (eg. diffuse mid-bandgap chromium into silicon, much like how boron or phospherous is diffused into silicon to provide P and N-type doped regions, rather than deposit chromium onto silicon and annealing the result to form chromium disilicide).

[0183] The Inverting and Non-inverting gate voltage channel induced semiconductor single device equivalents to (CMOS) of FIGS. 7b and 6b are better described, in words, in the Disclosure of the Invention Section of this Disclosure. FIGS. 7a and 6a show, respectively, circuit diagrams for inverting and non-inverting gate voltage channel induced semiconductor single device equivalents to multiple device conventional (CMOS), and correspond to the side cross-sections shown in FIGS. 7b and 6b, respectively. FIGS. 6c-6e and 7c-7e show Figures similar to FIGS. 6b and 7b with additional, non-limiting, junction geometries demonstrated, and FIGS. 6g and 7g show non-limiting polysilicon Gate Structure functional equivalents to FIGS. 6f and 7f Gates, and are to be considered as interchangeably present in FIGS. 6b-6e & 7b-7e. The Gate structure is not determinative of the present invention, but rather the principal of the present invention is that a material be present which forms rectifying junctions with both N and P-type semiconductor whether metallurgically or field induced.

[0184] It is noted with reference to the system of FIG. 6b, that if a voltage is applied between the Midpoint (MP) and one of the Drains (D), or with reference to FIG. 7b, if a voltage is applied between the Midpoint (MP) and one of the Sources (S), then application of a channel region effective doping type Gate (G) voltage can control the direction of rectification which said device would demonstrate. That is a gate voltage channel induced semiconductor gate voltage controlled rectification direction device and gate voltage controlled switch with operating characteristics similar to a non-latching Silicon Controlled Rectifier (SCR) is formed. As well, it is noted that if Schottky barrier (MOSFETS) as shown in FIG. 5 are formed on both N and P-type semiconductor, said resulting P-channel and N-channel Schottky barrier (MOSFETS) can be combined into a (CMOS) system by electrical interconnection of non-semiconductor components of Schottky barriers from the two gate voltage channel induced semiconductor devices, and electrical interconnection of the Gates.

[0185] It should also be appreciated that where compensated semiconductor is present under a Gate (G) such as in FIGS. 6b-6e or 7b-7e, carriers of both N and P-type are readily available for ionization and shuttling into and out of the channle region from the “bulk” portion of the semiconductor. Said carriers have very short distances to travel to form and cancel and form and cancel alternatingly “N” and “P” type Channel Regions. Said lateral shuttling of “N” and “P” cariers serves to form the longitudinally oriented channel regions (CHR) under the Gates (G). This presence of carriers overcomes the somewhat “mystical” question as to where the channel forming carriers come from in Single Device equivalent to CMOS as demonstrated in FIGS. 6b-6e and 7b-7e type devices formed on intrinsic semiconductor. The answer to said “mystical” question is that it is believed that the cariers come from an efffective if perhaps less reliable, (to ionization of impurity atoms essentially homogeneously distributed in the channel regions (CHR)), avalanche at the contacts to the external circuit.

[0186]
FIG. 8 shows a top view of a demonstrative semiconductor system (SC) comprising, sequentially, an Inverting, (see FIGS. 7b-7e for cross-section elevational view), gate voltage channel induced semiconductor single device equivalent, and a Non-inverting, (see FIGS. 6b-6e for cross-section elevational view), gate voltage channel induced semiconductor single device equivalent to (CMOS), and a Schottky barrier (MOSFET). Note that in the Inverting gate voltage channel induced semiconductor single device equivalent to (CMOS) case parasitic current flow blocking material (M) is placed so as to effectively surround ohmic Sources (S), and comprises rectifying Schottky barrier Drain (D) junctions to the semiconductor. Unintended current flow from the Sources (S) of the Non-inverting gate voltage channel induced semiconductor single device equivalent to (CMOS) is thus blocked. It is noted that the encircling Schottky barrier material (M) associated with the (MOSFET) acts as a parasitic current blocking material between Source (S) and Drain (D) therein and Drains and Sources in the Non-inverting gate voltage channel induced semiconductor single device equivalent to (CMOS). Note also the demonstrative presence of Traces (T1) (T10). Traces (T1) and (T2) serve to provide electrical access to electrically non-interconnected Sources (S) of the Inverting gate voltage channel induced semiconductor single device equivalent to (CMOS). Trace (T3) provides electrical interconnection to the Inverting gate voltage channel induced semiconductor device Split Gates (G). Trace (T4) interconnects electrically interconnected Drains (D) of the Inverting gate voltage channel induced semiconductor single device equivalent to (CMOS), (which is analogically similar to an essentially electrically isolated, from the Gate thereof, terminal in a conventional CMOS system), to the Split Gates (G) of the Non-inverting gate voltage channel induced semiconductor single device equivalent to (CMOS). Trace (T5) provides electrical interconnection of the lower Source (S) of the Inverting gate voltage channel induced semiconductor single device equivalent to (CMOS) to the lower Drain (D) of the Non-inverting gate voltage channel induced semiconductor single device equivalent to (CMOS) and Trace (T6) provides access to the upper Drain (D) of the Non-inverting gate voltage channel induced semiconductor single device equivalent to (CMOS). Trace (T7) provides output from the electrically interconnected Sources (S) of the Non-inverting gate voltage channel induced semiconductor single device equivalent to (CMOS). Taken in combination the electrically interconnected Inverting and Non-inverting gate voltage channel induced semiconductor single device equivalents to (CMOS).can be considered an Inverter with an Output Buffer Stage. A voltage input at Trace (T3) will control an inverted signal output at Trace (T7). Also shown is a Schottky barrier (MOSFET) with a surrounding isolating parasitic current blocking material (M). Traces (T8), (T9) and (T10) provide, respectively, electrical access to Drain (D), Gate (G) and Source (S) thereof. Trace (T11) is present to show that “Fan-out” from the Inverting gate voltage channel induced semiconductor single device equivalent to (CMOS) is possible, and the parasitic current blocking material (M) shown thereunder is present to indicate that said Trace (T11) can act as a parasitic MOSFET Gate and can invert semiconductor therebeneath and possibly cause parasitic currents to flow in said inverted semiconductor to a Drain (D) of a partially shown Forth device. Material (M) blocks said current flow as per FIGS. 2, 3 and 4. Trace (T11), (as well as other of the shown Traces), would most likely be present atop a deposited insulator which covers both the Material (M) and the Forth device Drain (D). (Importantly, note that the Forth Device could be a blocked element in an effective parasitic SCR configuration, which U.S. Pat. No. 4,300,152 identifies can be a problem in diffused junction based CMOS. (It is to be understood FIG. 8, (and the other Figures), are not to be interpreted as limiting of present invention placement of parsitic current flow blocking material(s), but rather are demonstrative only of possible application scenarios). Also note that the FIG. 8 can functionally comprise partially or fully compensated semiconductor in an epi-layer or substrate. FIG. 9b demonstrates application of the present invention to prevent parasitic four layer PNPN, (or NPNP), SCR-like device formation from PNP and NPN diffused junction transistors. Material “M” blocks parasitic currents which can cause latch-up.

[0187]

FIG. 9

a
shows that channel regions in gate voltage channel induced semiconductor single device equivalents to (CMOS) need not be physically aligned, and that electrical interconnection of junctions between channel regions need not be physically geometrically between said channel regions. This Figure serves to make clear that electrical contact to an electrical connection between channel regions via a junction can be effected with said junction located anywhere outside both channel regions. A particularly relevant example is where non-semiconductor components of rectifying Schottky barrier junctions to channel regions are electrically interconnected. The non-semiconductor components of the Schottky barrier junctions are interconnected “between” said channel regions, in the relevant electrical sense. While it should go without saying, the word “between” does not in any way imply a requirement of location of a junction or any other equivalent electrical continuity means which is physically, geometrically invariently directly between channel regions. Any functional electrical connection pathway is within the scope of the present invention.

[0188]
FIGS. 10 and 11 show operational Drain Current (ID) vs. Drain to Source Voltage (VDS), as a function of Gate Voltage (VG) for Schottky barrier (MOSFETS) fabricated by the Applicant herein. FIG. 10 is for an N-Channel and FIG. 11 is for a P-Channel (MOSFET). It is to be noted that the Applied Gate VG) and Drain to Source (VDS) voltages are of opposite polarities. This is in contrast to what is the case in all previously known MOSFETS. FIGS. 12a and 12b show, respectively, symbols for (CMOS) comprised of N and P-Channel MOSFETS, and a typical (CMOS) switching characteristic curve as a function of Gate Voltage (VG).

[0189]
FIG. 15 shows initial S-CMOS swtiching characteristics for an inverting Single-CMOS device, (see FIGS. 7a-7e), formed in essentially intrinsic silicion. Note that when approximately ten (10) volts was applied across the device (¢S” to “S”), and was switched on and off at the Gate (G), that the midpoint “MP” shows inverted voltrage switching. Sixty (60) hertz noise is present on the midpoint output signal and the source of such is not yet clear. Additional prototyping fabrication is presently in progress.

[0190] In the foregoing, as regards the Inverting and Non-inverting gate voltage channel induced semiconductor single device equivalents to (CMOS), the rectifying Schottky barrier junctions are identified as Drains, and the essentially non-rectifying junctions are identified as Sources. These terms utilized as they are familiar in (MOS) device settings, but it is to be appreciated that there is no conventional significance to said designation other than to suggest that two (MOSFETS), each formed with one rectifying Schottky barrier junction and one ohmic junction can be combined into Inverting and Non-inverting gate voltage channel induced semiconductor single device equivalents to (CMOS) by appropriate interconnection of Rectifying Drains or Ohmic Sources, respectively. Note that gate voltage channel induced semiconductor single device equivalents to (CMOS) shown in FIG. 8 are formed with electrically interconnected integrated Drains (Inverting device) or integrated Sources (Non-inverting device). In the context of the Inverting and Non-inverting gate voltage channel induced semiconductor single device equivalents to (CMOS), other terminology could just as well have been utilized, (eg. such as “First” and “Second” junctions for Source/(Drain) and Drain/(Source) respectively). As regards the (MOSFET), however, the use of the terms Source and Drain is more conventional as both Source (S) and Drain (D) junctions are rectifying, and it is to be noted that the semiconductor can be either P or N-type where said Schottky barriers are formed using, for instance, silicon semiconductor and chromium disilicide. As better discussed in U.S. Pat. No. 5,663,584 to Welch, other possible candidates for rectifying Schottky barrier formation with silicon include chromium, molybdenum, tungstun, vanadium, titanium and platinum, and silicides thereof. As well, it is to be understood that any Gate technology (eg. metal, polysilicon etc.), and Insulator type (eg. SiO2 etc.), and depth (eg. 20-3000 Angstroms), and any fabrication procedure which results in claimed systems is to be considered within the scope of the systems claimed.

[0191] It is noted that the inverting and non-inverting gate voltage channel induced semiconductor single device equivalents to (CMOS) can be utilized as modulators where both applied Gate (G) and Drain or Source voltages are simultaneously varied, and the voltage at the Midpoint (MP) monitored.

[0192] Continuing, the terminology “single device equivalents to (CMOS)” is to be understood to mean that each said “single device” is fabricated on a single type doping semiconductor, which can be N-type, P-type, Intrinsic or substantially Compensated and any other functional substrate type. That is to be interpreted to mean that there is no need to provide alternating N and P-type doped regions wherein P-Channel and N-Channel gate voltage channel induced semiconductor devices, respectively, are formed. Note that this is not to be taken to mean that various doping type regions such as N-type, P-type, Intrinsic and Substantially Compensated, can not be simultaneously co-present in a semiconductor substrate in which a present invention “single device equivalent to (CMOS)” is fabricated. For instance, a gate voltage channel induced semiconductor device being formed in a region of a semiconductor substrate characterized as at least one selected from the group consisting of:

[0193] being essentially intrinsic;

[0194] containing both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially equal doping levels;

[0195] containing both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially different doping levels, (eg. within three (3) orders of magnitude of one another); and

[0196] containing a single metallurgical doping type;

[0197] and functional combinations of said listed selections such as essentially intrinsic with a present invention device fabricated into a region of said essentially intrinsic wherein is present a metallurgically doped channel region of a functional depth, (eg. around one-hundred Angstroms or so), just below an insulator-semiconductor interface, (such as is easily achieved by low energy ion-implantation). This can be considered as exemplified by FIGS. 6b and 7b where the channel region (CHR) is considered to be N or P-type doping in the surface region of an essentially intrinsic or substantially compensated semiconductor substrate (SUB). Also, the terminology “gate voltage channel induced semiconductor device” is typically referred to in industry by the standard terminology “Metal Oxide Semiconductor or (MOS) device”. The reason for providing both N and P-type dopants, at substantially equal or different doping levels, substantially homogeneously simultaneously in a region of a semiconductor substrate is to make the carriers easily available for forming a channel region under the infulence of applied Gate Voltage.

[0198] While unlikely that confusion and undue interpretative limitation should develop, the terminology “gate voltage channel induced semiconductor device” has been adopted herein to make clear that the “Gate” can be other than just Metal per se., (eg. the Gate can be polysilicon or contain ferroelectric materials etc.). That is, in FIGS. 6b and 7b the “G” and “I” combinations are to be broadly interpreted as symbolically including any functional Gate/Insulator type structure, and FIGS. 6a and 7a are to be interpreted as generically symbolically representing the scope of the present invention as regards any Gate structure and rectifying and/or ohmic Junction structure etc. That is, any rectifying or ohmic Source or Drain junction can be present at a surface of a semiconductor, or in a region etched into a semiconductor. Further, where the terminology Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or Metal Oxide Semiconductor (MOS) has been retained in this Disclosure and in the claims, it is to be understood that Gates in described devices can be other than just Metal per se., (eg. polysilicon, ferroelectric material containing insulator etc.) and do remain within the scope of said terminology. And, it is to be understood that any means for providing electrical discontinuity between Gate and Source and Drain regions in any device described in this Disclosure is to be considered within the scope of the present invention as claimed. This includes, for instance, use of thick oxide or use of oxide side wall spacers etc. That is, the Doctrine of equivalents is to be considered liberally applicable. The basis of operation of the present invention is that certain materials form rectifying junctions with either N or P-type semiconductor whether said doping is metallurgically or field induced. Other elements and aspects of the present invention are not critical to said basis of operation and therefore are highly open to Doctrine of Equivalents, function maintaining substitution, particularly on an element by element basis. That is, for instance, substitution of a polysilicon or ferroelectric material containing insulator or other Gate for a metal Gate does not materially change the present invention, nor does the forming of an ohmic or rectifying junction at a semiconductor surface or in an etched semiconductor region. While said demonstrative variations do provide geometrically different devices, they do not alter the basic underlying principal of operation of the present invention.

[0199] It is further noted that FIGS. 6d-6e and 7d-7e show various rectifying and ohmic junctions in isotropically etched semiconductor substrate regions, said semiconductor substrate etched regions are to be interpreted sufficiently broadly so as to include anisotropically etched semiconductor substrate regions as shown in FIG. 7b under the Mid-Point (MP), wherein Schottky barrier forming material (SBFM) is accessed via contact metalization. FIGS. 6d-6e and 7d-7e are to demonstrat various etched and non-etched junction geometry locations, and not to exclude other possible junction geometries.

[0200] It is further to be understood that while gate voltage can be applied in inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems with respect to the back of a semiconductor substrate, (see FIG. 13a), and thereby provide essentially equal gate voltage driving force for field inducing carriers into both channel regions, (eg. right and left channel regions (CHR) in FIG. 7b for instance); when said inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, (ie. Single Device CMOS), is biased with the electrically non-interconnected essentially non-rectifying source junctions (eg. see top and bottom sources (S) in FIGS. 7a and 13b for instance), are held at different voltages, (eg. one at ground and the other offset therefrom either positively or negatively), particularly when undoped essentially intrinsic or equally doped substantially compensated silicon is utilized as the starting semiconductor substrate material, then some special considerations apply regarding how the inverting gate voltage channel induced semiconductor device operates. This is because the gate voltage driving force effectively present for field inducing carriers into a channel region which is off during at a time during a switching procedure, is less than that present for field inducing carriers into a channel region which is on, as said gate voltage driving force effectively present for field inducing carriers into a channel region which is off, is with respect to voltage present at the mid-point thereof, (eg. see (MP) in FIGS. 7a and 7b, for instance).

[0201] To elaborate, it is again stated that the inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems is basically two (Schottky barrier) junctions which comprise Semiconductor and Non-semiconductor element(s), wherein the non-semiconductor element(s) are electrically interconnected, (and ohmically accessed at (MP)), to provide a series system in which the rectifying (Schottky barrier) junctions, (formed by SBFM in FIG. 7b), are faced in opposition to one another. The (Schottky barrier) junctions are both made from a non-semiconductor material(s), (eg. Chromium Disilicide), which forms rectifying junctions with either N or P-type Silicon, (the non-limiting semiconductor used in fabrication efforts to date). Assuming silicon as the semiconductor, when a voltage is applied across the seriesed system of (Schottky barrier) junctions, assuming doping of the same type, (N or P), is present in the silicon associated with both (Schottky barrier) junctions, one said (Schottky barriers) junction is forward, and one said (Schottky barrier) junction is, by necessity, reverse biased. Now, said Single Device CMOS also has a Gate (G) associated with the silicon associated with both (Schottky barrier) junctions, and application of Gate Voltage serves to change the type of doping present in said silicon, (see elsewhere herein for description of Device Structure), hence the voltage at the interconnection of the (Schottky barrier) junctions. In the Inverting Single Device CMOS the voltage at the interconnection of the (Schottky barrier) junctions is caused to decrease when the Gate Voltage is increased, and vice-versa. And note that where essentially intrinsic or substantially compensated semiconductor is utilized, until voltages are applied to the metallurgical structure, no doping, hence, rectifying junctions are present in the metallurgical structure. That is—-the device, interpreted as requiring of electrons or holes in the s miconductor, does not even exist until Voltages are applied!

[0202] Assuming Chromium Disilicide is utilized, the metallurgical structure of a present invention Inverting Single Device CMOS, in an operational setting, can be described as:

[0203] Power Supply

[0204] A. (+V) applied to top source (S) in FIG. 7a

[0205] Top Half of Single Device CMOS Structure, Sequentially:

[0206] B. ohmic contact—first silicon channel (CHR) region—first chromium disilicide junction

[0207] C. ohmic contact to mid point (same contact as in bottom half)

[0208] Bottom Half of Single Device CMOS Structure, Sequentially:

[0209] C. ohmic contact to mid point (same contact as in top half)

[0210] D. second chromium disilicide junction—second silicon channel (CHR) region—ohmic contact—

[0211] Power Supply

[0212] E. (GND) applied to bottom source (S) in FIG. 7a.

[0213] (For demonstration purposes it is assumed that a positive polarity bias voltage to ground is utilized and that the gate voltage switches between said positive polarity bias voltage and ground to effect and inverted output result. However, a negative voltage to ground is to be considered as equivalent, as is the case where ground is eliminated and both positive and negative voltage sources are utilized).

[0214] It can be stated that where essentially intrinsic or substantially compensated silicon is the starting substrate, application of Gate Voltages is the enabling “Spirit” that causes Field-induced first and second silicon channel region doping adjacent to chromium disilicide junctions, and causes the Single Device Equivalent to CMOS to “appear” out of the mere “carrierless” metallurgical “body”, and remain as long as Gate Voltages are applied near (+V) or GND.

[0215] The Gate Voltage induced doping in a silicon channel region adjacent to a forward conducting Chromium Disilicide-Field Induced Doped Silicon (Schottky barrier) junction to said field induced doped silicon channel region, will invariably be highly concentrated and the resulting (Schottky barrier) will be driven very strongly “ON” by a full (+V to GND) (Δ V), and we can set the level of (+V) to force this. Now, If this also caused high doping in the silicon channel region of the “OFF” half silicon channel region (Schottky barrier) junction, we would probably have a high leakage current reversed bias situation. This, however, is not what happens!

[0216] The semiconductor channel region in an “OFF” half of the Single Device Equivalent to CMOS, will not see a full (+V to GND) (Δ V), as the (Δ V) in the “OFF” half of the Single Device Equivalent to CMOS is with respect to Voltage supported by what is a reverse biased junction—(that is, if the Applied Gate Voltage induces carriers in the first place so as to form the (Schottky barrier) junction!). That there will be some carriers induced in the silicon channel region of the “OFF” half of the device, (which ever half that might be depending on Gate Voltage being set to +V or GND), is seemingly assured as onset of a “Pinch-Off” Region will be present in the “OFF” half silicon channel region. This is where the complexity comes into play. Three Regions of voltage drop can be relatively easily identified in the channel region of the “OFF” half of the Single Device CMOS:

[0217] 1. Pinch-Off Region, near the ohmic contact to silicon channel region Δ V′;

[0218] 2. Ohmic Drop due to Current Flow through silicon channel region which has some conducting carriers Gate Voltage Induced therein (limited to a maximum of a resulting Reverse Biased (Schottky barrier) Junction Leakage Current which said doping in said Channel Region which is limited by effective reverse biased (Schottky barrier) junction Δ V″.

[0219] 3. Drop across the “OFF” Reverse biased (Schottky barrier) Junction V-ΔV.

[0220] Now, only Voltage Drops identified as present in Region 1 (Δ V′) and Region 2 (Δ V″) constitute a Gate Voltage effected total (Δ V) which total (Δ V) can field induce carriers to be present in an “OFF” half silicon channel region of a Single Device Equivalent to CMOS.

[0221]

FIGS. 14

a
and 14b show two switching states for an inverting gate voltage channel induced semiconductor single device equivalent to (CMOS). In FIG. 14a the lower channel region (SC2) is “on” and “M” is at (GND) through a forward biased junction (D2) and heavily doped channel region (SC2), while the upper channel region (SC1) is “off”, with two regions of voltage drop Δ V′, and Δ V″ described above represented. In FIG. 14b the upper channel region (SC1) is “on” and “M” is at the applied (+or − V) through a forward biased junction (D1) and heavily doped channel region (SC1), while the upper channel region (SC1) is “off” with two regions of voltage drop Δ V′, and Δ V″ described above represented.

[0222] Also, note that even if no carriers are induced in an “OFF” half of a Single Device Equivalent to CMOS because the V carrier attracting voltage is too small, (see FIGS. 14a and 14b), to cause formation of a reverse biased rectifying junction in the essentially intrinsic or substantially compensated semiconductor, the result is an essentially non-conducting essentially intrinsic or substantially compensated silicon channel region adjacent to where the reverse biased junction would be formed if it did form, and current can't flow directly through an essentially intrinsic or substantially compensated channel region as no carriers exist therein to carry said current flow. Thus either a semiconductor channel region will be essentially intrinsic or substantially compensated and non-conducting or a reverse biased junction will be present in an “off” half of the single device equivalent to CMOS. This means that can be no short circuit from Source (+V) to (GND)), much as is the case in conventional CMOS where one of the seriesed N and P-Channel devices is always, (but for an extremely brief instant at switching), non-conducting.

[0223] Now, viewed as a Black-box, the Single Device CMOS output at the interconnected (non-semiconductor elements of the (Schottky barriers) rectifying junctions, will follow the forward biased (Schottky barrier) junction, so except for possible high frequency transients which might be induced therein, the redistribution of voltage drops in the identified three Regions of the “OFF” half of the Single Device CMOS silicon channel region will not be of major concern. And, as onset of Pinch-off will occur in the silicon channel region of an “OFF” half Single Device CMOS silicon channel region, we have a damping effect will ensure a (Δ V) silicon region steady state induced doping will be “predestined”, (assuming we don't switch the devices faster than it takes to reach it). That is, positive feedback run-away should not be possible. Further since on Intrinsic Silicon, (and substantially Compensated), there is not a Threshold Voltage (VT) to subtract from an applied Gate Voltage (VG), and as a result the half of the Single Device CMOS that is turning “ON” in a Gate Voltage Switching, will lead the device that is turning “OFF”. This is believed as doping which must be inverted in an “OFF” half of a Single Device CMOS during a switching which will make it the “ON” half, is lower than that in the then “ON” half. This could lead to a direct short disaster were it not for the fact that the silicon in an “ON” device returns to essentially Intrinsic, (or substantially Compensated), after the charge in a channel region that was associated with the “ON” half of the Single Device CMOS is depleted, and then is expected to go opposite doping type and form a current flow blocking reverse bias (Schottky barrier) junction in said “OFF” half). Especially in the presence of substantially uniformly distributed N and P-type Dopants in the semiconductor region in which the S-CMOStm device is fabricated, which can be relatively easily ionized and alternatingly contribute to both N and P Channel formation, it is believed that this “ON” influence leading “OFF” will lead to faster operation in Single Device CMOS than is possible in Conventional CMOS. In conventional CMOS oppositely directed Fermi-Potentials must be overcome, thereby requiring less Gate Voltage Magnitude to turn off an on P or N-Channel device, than required to turn on the accompanying N or P-Channel device. The Single Device CMOS we might see some charge from an “ON” half silicon channel region, (which is turning “OFF”), be “attracted” into the silicon channel region which is turning “ON”. This should be viewed while realizing that even conventional CMOS has some current drain in operation. And, with small device scaling, the charge which is available to be “attracted” will be small. It must be understood that the presently described operational scenario is convoluted. Why this is, is best demonstrated by just diving in with examples. First, as mentioned, without applied Gate and (+V) voltages at the top ohmic junction to top silicon channel region, the devices formed in Intrinsic or substantially Compensated silicon are mere “bodies” without any animating “Spirit”. Application of Gate and (+V) causes the Single Device CMOS to “appear”. The full (+V) drops across the Gate of the half of the Single Device CMOS that turns on, (bottom half for Gate at (+V) and top half for Gate at GND). However, the amount of Gate Voltage which can induce carriers in the “OFF” half of the Single Device CMOS is limited as the carrier inducing portion of the applied Gate voltage is referenced to a voltage which rides “atop”, (if the Gate Voltage is at +V), or “below” (if the Gate Voltage is at GND), a reverse biased (Schottky barrier) junction, (if carriers are induced to be present at all in the “OFF” half silicon channel of the Single Device CMOS). If no carriers are induced to be present in an “OFF” half silicon channel region, there will be no reversed bias (Schottky barrier) junction even formed—but the silicon channel associated therewith will be non-conducting Intrinsic or substantially Compensated. This is very desirable. Onset of Pinchoff in the “OFF” half silicon channel region, however, seemingly ensures that some applied Gate voltage will be available to induce carriers to be present in the silicon channel region of the “OFF” half of the Single Device CMOS (whichever half that is at a time—top for Gate volts=(+V) and bottom for Gate volts=GND), thus the “OFF” half of the Single Device CMOS will have a functional reverse biased (Schottky barrier) junction region present therein, along with the onset of Pinchoff Region, and a somewhat conductive silicon channel Region. How voltages will divide across said three regions will be a very complex function of time. But, if the reverse bias (Schottky barrier) junction forms, it must be appreciated that most voltage drop will probably appear across it. This could mean that if the Gate voltage is set to (+V), the Gate Voltage and the (+V) applied to the top ohmic junction to the top silicon channel could be at the same voltage and thus no Gate driving voltage will exist to induce carriers presence. (Reverse Feedback). If the reverse bias (Schottky barrier) junction is leaky though, and some carriers are present in the “OFF” half silicon channel region, some current could flow through what could become a high resistance “OFF” half silicon channel region of the Single Device CMOS, thereby leading to a voltage drop which will cause some voltage drop across the “OFF” half silicon channel region, thereby causing some, (positive feedback type), Gate Voltage silicon channel region carrier inducing influence. This will increase the carriers present in the “OFF” half silicon channel region, thus the conductance of it, and reduce the voltage drop across it effected by current flow through it, thereby reducing the Gate voltage carrier inducing effect—but current flow could increase and offset the effect. Also, more carriers in the “OFF” half silicon channel region, mean that the formed (Schottky barrier) junction will be more “leaky”, thereby allowing more current to flow through the formed reverse bias (Schottky barrier) junction, but more carriers mean higher conductivity in the “OFF” half silicon channel region, so less voltage drop thereacross. It is possible that the:

[0224] “more-carriers-higher-reverse-bias-(Schottky-barrier) junction-leakage-current”, and

[0225] “more-carriers-less-channel-resistance

[0226] “more-carriers-higher-reverse-bias-(Schottky-barrier) junction-leakage-current”, and

[0227] “more-carriers-less-channel-resistance and-voltage-drop-due-to-current-flow-therethrough”

[0228] effects will cancel each other to some extent, and trend to a steady state value for the amount of Gate Voltage which drops across the Gate, (Δ V), and can induce carriers into an “OFF” half silicon channel region of a Single Device CMOS. The reverse bias (Schottky barrier) junction will probably drop most (+V) across it, and a smaller drop across an onsetting Pinchoff will possibly account for most the rest. The portion of (+V) which drops across the silicon channel region due to current flow therethrough (limited to a maximum of the reverse leakage of the reverse biased (Schottky barrier) junction which is formed by the presence of Gate voltage induced carriers), will probably be relatively small, and will probably not greatly effect the voltage at the reverse biased (Schottky barrier) junction against which the applied Gate Voltage plays, to form the “OFF” half silicon channel region carrier inducing effect. Various geometries and Gate Oxide depths etc. might help diminish any adverse effects, and enhance desirable ones, whatever desirable effects turn out to be upon close examination. Of course, where metallurgical doped semiconductor is utilized as a starting substrate, a similar analysis is applicable in that an “OFF” channel region is less heavily doped by field induced means than an “ON” channel region, in operation.

[0229] It is again noted for focus that where the semiconductor is compensated, that is has both N and P-type carriers present substantially hogeneously distributed therein in the region thereof wherein the S-CMOStm device is fabricated, channel formation near the mid-bandgap dopant region is facilitated. That is, channel forming carriers are realized via ionization of dopants rather than via avalanche from Source or Drain junctions. And the nearby presence of opposite type carriers make switching channel region effective doping type easier and possibly faster than can be achieved where avalanche is the basis of operation.

[0230] It is also noted that if one of the electrically non-interconnected source junctions (S) of an inverting single device equivalent to CMOS, as in FIGS. 7a and 7b, is tied to a back of the substrate contact, (as would be the case if in FIG. 13a one of the voltage sources was to be replaced with a short circuit), then the effective channel gate voltage is effectively “decoupled” from the voltage present atop the reverse biased (Schottky barrier) junction as regards its ability to cause carriers to be attracted into the first and second channel regions. Under such a biasing scheme both the first and second channel regions would be more similarly affected by applied gate voltage to the end that approximately equal numbers of carriers would be attracted into each of said first and second channel regions. This enables a simplified analysis, but perhaps less optimum operation in that the “off” channel region during a point in a switching cycle would be more highly populated with carriers, with attendant higher reverse bias (Schottky barrier) junction leakage current etc.

[0231] A similar analysis of the non-inverting single device equivalent to CMOS device is far less involved, because it is the essentially ohmic junctions which are electrically interconnected. Thus, in a FIG. 13b type bias arrangement, one of the first and second channel regions, which is “off”, does not sit atop a reverse biased junction and thereby limit the applied gate to channel carrier attraction voltage, while the other, (second and first respectively), “on” channel region does not. Rather, where a FIG. 13b biasing arrangement, is applied to a non-inverting single device equivalent to CMOS device, both first and second channel regions sit atop a reverse biased (Schottky barrier) junction, and said fist and second channel regions are ohmically interconnected to one another, (and in fact can be a merged, ohmically accessed, single channel region). However, it is noted that an onset of pinch-off region will exist near the forward biased (Schottky barrier) junction which is present at the end of the channel region opposite that at which is present the reverse biased junction, and will serve to drop some voltage thereacross, thereby providing some channel region carrier attracting voltage drop from the gate to the channel region. The operation of the non-inverting single device equivalent to CMOS in a FIG. 13b biasing arrangement will thus depend on the relative impedance of the pinch-off region and the reverse bias (Schottky barrier) junction as well as the current flow therethrough. Particularly in a FIG. 13a type biasing arrangement, however, the applied gate voltage is referenced to the back of the semiconductor substrate, and will not be limited in its ability to attract carriers into the first and second channel regions by referencing to the top of a reverse biased junction which sits at essentially the applied gate voltage less a voltage drop across an onset of pinch-off region. During operation, the presence of the onset of pinch-off region near the forward biased junction forms a voltage divider with the reverse biased (Schottky barrier) junction, to the end that most voltage drops across the inherently higher impedance reverse biased junction. Reasonably assuming that the total impedance of the onset of pinch-off region plus the reverse biased junction is sufficiently high so that current flow through the non-inverting single device equivalent to CMOS is low, it is expected that said non-inverting single device equivalent to CMOS will operate well in a FIG. 13a type biasing circuit, at least as a sequentially last stage buffer in an integrated circuit environment, assuming that the voltage drop across the onset of pinch-off region is small and tolerable.

[0232] It is noted that FIGS. 6b-6e and 7b-7e are not to be interpreted that any specific junction geometry is required. In particular, while the (SBFM) in FIGS. 6c and 7c is shown extending a bit into the surface of the semiconductor and the ohmic contact is not, this is not to be considered as limiting. Both or neither type junction can extend or not into the semiconductor surface, but the shown configuration is relevant as the (SBFM) will possibly be more chemically differentiated from the semiconductor than will be the case at an ohmic junction. In particular nothing herein is to be interpreted to require etching into the semiconductor to form a disclosed invention device.

[0233] Also, FIGS. 6b-6e and 7b-7e are not drawn to scale, and can be considered to show substrates per se., or epi-layers on substrates, wherein the devices are fabricated.

[0234] It is to be understood that while traces T1-T11 as shown in FIG. 8, and metal Gates and (SBFM) contacting metalizations as many Figures represent are typically aluminum, any functional material such as copper, polysilicon (preferably doped to provide high conductivity), and silicides can be used.

[0235] It is noted that materials which form rectifying junctions with either N or P-type doped semiconductor, are typically identified as forming “Schottky barrier junctions” with the semiconductor, and said materials are typically non-semiconductor. However, the present invention is not to be considered as limited thereto and by said terminology and semantics. Any material which forms rectifying junctions with either N or P-type semiconductor as applied in a claimed semiconductor device, is to be considered within the scope of the present invention, regardless of how said material is applied to a semiconductor substrate.

[0236] It is emphasized that throughout this Disclosure the terms “Schottky barrier” as used to describe a junction, is to be read as a very relevant exemplary type of junction applicable to fabricating present invention semiconductor devices, rather than as a limitation thereon. Again, the present invention requires only that junction forming material(s) utilized provide rectifying characteristics when either N or P-type semiconductor is present in combination therewith, whether said N or P-type doping is metallurgical or filed induced, and regardless of how said material(s) are included with said semiconductor, (eg. by vacuum deposition, ion implantation, deposition and diffusion etc. as combined with appropriate anneals etc.).

[0237] It is also to be understood that where the terminology “gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems” and the like is utilized in this Disclosure, it is meant to indicate that only a single doping type, (eg. P or N-type or Essentially Intrinsic or Substantially Compensated (simultaneously containing both N and P-type metallurgical dopants at equal or different levels essentially homogeneously distributed threwithin), or P-type on Insulator or Intrinsic Semiconductor or N-type on Insulator or Intrinsic Semiconductor, etc. must be present in a semiconductor substrate to allow realization of the “gate voltage channel induced semiconductor device”. This is to contrast to the case where separate alternating N and P-type semiconductor regions must be present to allow realization of multiple device, (eg. P and N-Channel MOSFETS connected in series), Complementary Metal Oxide Semiconductor (CMOS) system which requires both P and N-channel MOSFETS be present in functional combination. Said terminology “gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems” does not mean that a “single doping type” semiconductor in which it is fabricated can not have essentially intrinsic or substantially compensated regions, or regions of opposite type doping present therein at locations therein removed from the location of a present invention gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) system.

[0238] It is also to be understood that the terminology “doped” or “doping” is utilized herein to refer to gate voltage caused field induced carriers in a channel region as well as to metallurgically caused doping. And, it is to be noted that the terminology “application of a gate voltage affects semiconductor channel region doping type in both said first and second channel regions . . . ” simply means that applied gate voltage can cause accumulation of carriers in a channel region. For instance, an applied gate voltage need not cause accumulation of carriers in both channels region of a present invention gate voltage channel induced semiconductor device to the same extent, but if carriers are induced, the same type, (eg. electron or hole), will be induced in each of said channel regions.

[0239] It is also to be understood that where a junction associated with a first semiconductor channel region in a present invention device is recited as being electrically interconnected with the a junction associated with said second semiconductor channel region in a present invention device, said language is to be interpreted to be applicable, as appropriate to either integrated or component level interconnections. That is any electrical continuity is within the scope of said language.

[0240] Also, while, the terminology “insulator” or “insulation material” applied in association with a gate in a present invention system typically identifies such as silicon dioxide, (where silicon is the semiconductor), it is to be understood that any material which is essentially electrically non-conducting and can support an applied voltage such that field induced carriers appear in an associated adjacent channel region is to be considered within the scope of the present invention, whether it is grown or deposited. In particular it is disclosed that any material which can be implemented in a MOS type Gate insulator is within the scope of the present invention. Ferroelectric materials suggested in the literature include, but are not limited to, for instance, SrBi2Ta2O9 (SBT) which has a Cubic Pervoskite structure. Other ferroelectric materials are BaMgF4 (BMF) and Pb(ZrxTi1-x)O3 (PZT), Triglycerine Sulfate (TGS), Pb(ZrTi)O3, BaTiO3, Guanidinium Aluminum Sulfate Hexahydrate. Additionally, it is noted that some polymers which demonstrate ferroelectric characteristics, and which can be functionally included in a MOS type Gate insulator where temperature breakdown can be avoided, are within the scope of the present invention. It is emphasized however, that as stated in Co-Pending application Ser. No. 09/246,871 filed Feb. 08, 1999, it is not the presence of specific material(s) in MOS-type Gate Insulator Material which establishes Patentability, (in the present effort), but rather it is inclusion of any functional material(s) in a Gate Insulator in semiconductor devices which comprise mid-bandgap material(s), (eg. chromium, molybdenum, tungstun, vanadium, titanium, platinum and silicides thereof), which form rectifying junctions with either N or P-type silicon semiconductor, whether said “doping” is metallurgically or field induced, (ie. semiconductor devices disclosed in U.S. Pat. Nos. 5,663,584, 5,760,449 and 6,091,128 to Welch), which provides Patentability and establishes the scope of the present invention.

[0241] It is also emphasized that where the terminology “essentially intrinsic semiconductor” is utilized, said terminology is to be considered sufficiently broad to, where functionally applicable, include “substantially compensated semiconductor” wherein substantially equal amounts of both N and P-type metallurgical dopants are present. To emphasize this point, it is specifically noted that in substantially compensated semiconductor essentially equal amounts of P and N-type dopants are simultaneously present in region(s) of the semiconductor, thereby causing said semiconductor to appear with a resulting doping a bit similar to that in essentially intrinsic semiconductor. However, for the purposes of this Specification the terminology substantially compensated semiconductor shall be interpreted to include semiconductor in which are simultaneously present at least some N-type and some P-type Metallurgical Doping, whether of exactly equal or somewhat different doping levels. The purpose of providing both types of dopants simultaneously present being to make applied Gate Voltage Field Induction of electrons and holes in channel regions in the semiconductor more easy to accomplish.

[0242] It is also noted that no know reference with priority over this Application makes it obvious to homogeneously distribute N and P-type metallurgical dopants in a semiconductor substrate in which Semiconductor Devices are then Fabricated. While fabrication of devices in homogeneously distributed single type dopant semiconductor substrates is known, and while it is also known to enter opposite type metallurgical dopant in a channel region, as is done by ion implantation in conventional CMOS MOSFETS to adjust threshold, homogeneously distributing both N and P-type dopants in a semiconductor substrate is not obviated thereby. Entered threshold adjusting opposite type dopants are simply never entered to the semiconductor substrate so as to be substantially homogeneously distributed therein in any procedure known to the Applicant. Further, no reference with priority over this Application remotely obviates homogeneously distributing both N and P-type dopants in a semiconductor substrate in which an inverting single device with operating characteristics similar to dual device seriesed N and P-Channel MOSFETS CMOS systems is fabricated, for threshold adjustment, or for any purpose for that matter. For emphasis, no known reference remotely suggests fabrication of devices of any type in semiconductor which homogeneously contains both N and P-type dopants, (either in the entire Substrate of in an Epi-Layer in which Semiconductor Devices are formed), let alone fabrication of the inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems therein.

[0243] It is also noted that epi-layers can be present on semiconductor or other than semiconductor material substrate materials, (eg. insulators). It is the presence of partially or fully compensated semiconductor, (in which semiconductor devices are formed), in/on a substrate of any type which is the focus in the present invention.

[0244] It is also noted that the terminology “Metallurgical Dopants” refers to impurities entred to a semiconductor which become a part of its material structure. Said terminology differentiates over “Field Induced” carriers which are attracted via applied Gate Voltage into place and which recombine when the Gate Voltage is removed. Note however that an applied Gate Voltage can attract into place carriers provided by ionized metallurgical dopants.

[0245] Finally, it is speculated that fabrication of semiconductor devices in partially or fully compensated semiconductor regions of a substrate has not been known as current flow therethrough is impeded by the scattering mobility reducing presence of impurities present therein. However, in semiconductor devices wherein current flow is not desired, (eg. CMOS-type voltage switching devices), impurity scatering of current carriers is not a detrimental effect. In this light, where functional, the terminology “semiconductor” and/or “semiconductor region” and/or substrate and the like in this Specification is to be interpreted to include both single crystal and amorphous and intermediates therebetween.

[0246] Having hereby disclosed the subject matter of the present invention, it should be apparent that many modifications, substitutions, and variations of the present invention are possible in light thereof. It is to be understood that the present invention can be practiced other than as specifically described and should be limited in scope and breadth only by the appended claims.

Claims

1. A semiconductor system comprising a semiconductor device in a semiconductor region of a substrate characterized by at least one selection from the group consisting of: said semiconductor region contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially equal doping levels; and said semiconductor region contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially different doping levels; said semiconductor device comprising at least one junction(s) characterized by at least one selection from the group consisting of: P-N rectifying; Schottky barrier rectifying; and formed from non-semiconductor, and semiconductor, components, wherein said non-semiconductor component of said at least one junction(s) is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced.
2. A semiconductor system comprising a semiconductor device in a semiconductor region of a substrate characterized by at least one selection from the group consisting of: said semiconductor region contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially equal doping levels; and said semiconductor region contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially different doping levels; said semiconductor device comprising a plurality of junctions, each being characterized by a selection from the group consisting of: P-N rectifying; Schottky barrier rectifying; and formed from non-semiconductor, and semiconductor, components, wherein said non-semiconductor component of said at least one junction(s) is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; and arranged as a selection from the group consisting of a-g: a. being essentially ohmic; and comprising non-semiconductor, and semiconductor, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; b. comprising non-semiconductor, and semiconductor, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; and comprising non-semiconductor, and semiconductor, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; c. being essentially ohmic; comprising non-semiconductor, and semiconductor, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; comprising non-semiconductor, and semiconductor, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; and being essentially ohmic; d. being substantially ohmic; being rectifying; being rectifying; and being substantially ohmic; e. being rectifying; and being rectifying; f. being substantially ohmic; and being rectifying; comprising non-semiconductor, and semiconductor, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced; being essentially ohmic; being essentially ohmic; and comprising non-semiconductor, and semiconductor, components, wherein said non-semiconductor component is comprised of at least one material(s) which forms rectifying junctions with both N and P-type semiconductor, whether said semiconductor type is metallurgically or field induced;
3. Inverting and non-inverting devices with operating characteristics similar to dual device seriesed N and P-Channel MOSFETS CMOS systems; comprising in use, two oppositely facing electrically interconnected rectifying diodes in a semiconductor region of a substrate characterized by at least one selection from the group consisting of: said semiconductor region contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially equal doping levels; and said semiconductor region contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially different doping levels; wherein a forward direction of rectification of each of said electrically interconnected rectifying diodes changes depending upon what doping type, (N or P), be it metallurgically or field induced, is present in the semiconductor, said inverting and non-inverting single device equivalents to dual device seriesed N and P-Channel MOSFETS CMOS systems further comprising gate means for field inducing effective doping type in said semiconductor, said gate means being set off from said semiconductor by insulator and each of said electrically interconnected rectifying diodes having an electrically non-interconnected terminal; and wherein, in use, different voltages are applied to the non-electrically interconnected terminal of each of the oppositely facing rectifying diodes, and a voltage between said applied different voltages, inclusive, is monitored at the electrical interconnection between said two oppositely facing rectifying diodes, which monitored voltage responds as a function of applied gate voltage, said monitored voltage being essentially electrically isolated from said gate voltage and appearing at said electrical interconnection between said two oppositely facing rectifying diodes primarily through the rectifying diode which becomes forward biased; the basis of operation of said gate voltage channel induced semiconductor devices being that said rectifying junctions are comprised of material(s) that form a rectifying junction to semiconductor when it is doped either N or P-type by either metallurgical or field induced means.
4. A semiconductor device formed in a semiconductor region characterized as single crystal or amorphous or an intermediate thereto, in which are essentially homogeneously simultaneously present both N and P-type metallurgical dopants, said semiconductor device comprising at least one rectifying junction which is formed from non-semiconductor and semiconductor components, wherein said junction non-semiconductor component is comprised of material(s) which, in use, form a rectifying junction with both N and P-type semiconductor, whether metallurgically or field induced.
5. An inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, said inverting gate voltage channel induced semiconductor device being formed in a semiconductor epi-layer or substrate characterized by a selection from the group consisting of: said semiconductor contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially equal doping levels; and said semiconductor contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially different doping levels; said inverting gate voltage channel induced semiconductor device comprising two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprising two additional junctions, termed source and drain, which are separated by a second semiconductor channel region, wherein gates, to which semiconductor channel region field induced effective doping effecting voltage can be applied, are associated with each of the first and second semiconductor channel regions, said gates being offset from said first and second semiconductor channel regions by insulating material; such that during use application a sufficient positive voltage to said gates will attract electrons to said first and second semiconductor channel regions, and such that application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect field induced effective doping type of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying, and which drain junctions are rectifying junctions; in which inverting gate voltage channel induced semiconductor device the rectifying drain junction associated with said first semiconductor channel region is electrically interconnected with the rectifying drain junction associated with said second semiconductor channel region, and in which said gates associated with said first and second channel regions are electrically interconnected; such that during operation the electrically noninterconncted essentially non-rectifying source junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region effective doping type in both said first and second channel regions by field induced means, and thus which electrically interconnected rectifying drain junction forward conducts as a result of semiconductor type metallurgically present or field induced by said applied gate voltage, thereby controlling the voltage present at the electrically interconnected rectifying drain junctions essentially through said forward conducting rectifying drain junction; the basis of operation of said inverting gate voltage channel induced semiconductor device being that said rectifying drain junctions associated with said first and second semiconductor channel regions thereof are comprised of at least one material that forms a rectifying junction to a semiconductor channel region when it is either N or P-type by either metallurigical or field induced means, and the presence of at least partially compensated semiconductor which comprises both N and P-type carriers enables easy provision of N and P-type channel region forming carriers via gate voltage application effected field effect means.
6. An inverting gate voltage channel induced semiconductor device as in claim 5, in which the semiconductor further comprises at least one region of parasitic current flow blocking material which prevents parasitic currents from flowing to or away therefrom through said at least one region of parasitic current flow blocking material, said at least one region of parasitic current flow blocking material being present at at least one selection from the group consisting of: physically a part of the inverting gate voltage channel induced semiconductor device and comprising an extention of the electrical interconnection between the rectifying drain junction associated with said first semiconductor channel region and the rectifying drain junction associated with said second semiconductor channel region; and physically separate from the inverting gate voltage channel induced semiconductor device; said at least one region of parasitic current flow blocking material forming rectifying junctions with both N and P-type metallurgical or field induced semiconductor.
7. An inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems, said inverting gate voltage channel induced semiconductor device being formed in a compensated semiconductor epi-layer or substrate characterized by a selection from the group consisting of: said semiconductor contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially equal doping levels; and said semiconductor contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially different doping levels; said inverting gate voltage channel induced semiconductor device comprising two junctions, termed source and drain, which are separated by a first semiconductor channel region, and further comprising two additional junctions, termed source and drain, which are separated by a second semiconductor channel region, wherein gates, to which semiconductor channel region effecting voltage can be applied, are associated with each of the first and second semiconductor channel regions, said gates being offset from said first and second semiconductor channel regions by insulating material; such that during use application of a sufficient positive voltage to said gates will attract electrons to said first and second semiconductor channel regions, and such that application of sufficient negative voltage to said gates will attract holes to said first and second semiconductor channel regions, the purpose of applying such gate voltage being to affect field induced effective doping of said first and second semiconductor channel regions between respective source and drain junctions, which source junctions are each essentially non-rectifying when sufficient field induced effective doping is present in the channel region adjacent thereto, and which drain junctions are each rectifying when sufficient field induced effective doping is present in the channel region adjacent thereto; in which inverting gate voltage channel induced semiconductor device the drain junction associated with said first semiconductor channel region is electrically interconnected with the drain junction associated with said second semiconductor channel region, and in which said gates associated with said first and second channel regions are electrically interconnected; such that during operation the electrically noninterconncted source junctions are held at different voltages, and application of a gate voltage affects semiconductor channel region effective doping in said first and second channel regions by field induced means, and thus which electrically interconnected rectifying drain junction in said semiconductor forms, as a result of semiconductor type field induced by said applied gate voltage, and forward conducts, thereby controlling the voltage present at the electrically interconnected drain junctions essentially through said formed forward conducting rectifying drain junction; the basis of operation being that the drain junctions associated with said first and second semiconductor channel regions are comprised of at least one material that forms a rectifying junction to a semiconductor channel region when it is caused to be either N or P-type by field induced means, and the presence of at least partially compensated semiconductor which comprises both N and P-type carriers enables easy provision of N and P-type channel region forming carriers via gate voltage application effected field effect means.
8. An inverting gate voltage channel induced semiconductor device as in claim 7, in which the semiconductor further comprises at least one region of parasitic current flow blocking material which prevents parasitic currents from flowing to or away therefrom through said at least one region of parasitic current flow blocking material, said at least one region of parasitic current flow blocking material being present at at least one selection from the group consisting of: physically a part of the inverting gate voltage channel induced semiconductor device and comprising an extention of the electrical interconnection between the rectifying drain junction associated with said first semiconductor channel region and the rectifying drain junction associated with said second semiconductor channel region; and physically separate from the inverting gate voltage channel induced semiconductor device; said at least one region of parasitic current flow blocking material forming rectifying junctions with both N and P-type metallurgical or field induced semiconductor.
9. An inverting gate voltage channel induced semiconductor device in claim 7 in which the semiconductor channel region and, when formed, adjacent drain junction which is not forward conducting, is characterized by at least one selection from the group consisting of: a. being functionally comprised of two regions across which voltage can drop, namely an onset of pinch-off region and a channel region; b. being functionally comprised of three regions across which voltage can drop, namely an onset of pinch-off region, a portion of the channel region which is populated with some gate voltage field induced carriers, and a formed reverse biased rectifying junction.
10. An inverting gate voltage channel induced semiconductor device as in claim 7, in which the semiconductor channel region and adjacent formed rectifying drain junction which is forward conducting is characterized as comprising a field induced carrier containing channel region and a forward biased rectifying junction.
11. An inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems as in claim 5, in which the semiconductor is silicon and at least one of the drain junctions comprises at least one material which forms a barrier height of approximately half the band-gap of the semiconductor with said semiconductor.
12. An inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems as in claim 7, in which the semiconductor is silicon and at least one of the drain junctions comprises at least one material which forms a barrier height of approximately half the band-gap of the semiconductor with said semiconductor.
13. An inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems as in claim 5, which further comprises a voltage bias source connected across said electrically noninterconncted essentially non-rectifying source junctions so that they are held at different voltages, each voltage being selected from the group consisting of: +V; −V; and Ground; said voltage bias source providing a selection from the group consisting of: having contact to the back of said substrate; and not having contact to the back of said substrate.
14. An inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems as in claim 7, which further comprises a voltage bias source connected across said electrically noninterconncted essentially non-rectifying source junctions so that they are held at different voltages, each voltage being selected from the group consisting of: +V; −V; and Ground; said voltage bias source providing a selection from the group consisting of: having contact to the back of said substrate; and not having contact to the back of said substrate.
15. An inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems as in claim 5, in which at least one source or drain junction is characterized by at least one selection from the group consisting of: being formed in a region etched into the semiconductor, being formed by a process comprising vacuum deposition of said at least one material onto said semiconductor, being formed by a process comprising diffusion of said at least one material into semiconductor, being formed by a process comprising ion-implantation of said at least one material into said semiconductor, and being comprised of said at least one material which forms a barrier height of approximately half the band-gap of the semiconductor.
16. An inverting gate voltage channel induced semiconductor device with operating characteristics similar to multiple device Complementary Metal Oxide Semiconductor (CMOS) systems as in claim 7, in which at least one source or drain junction is characterized by at least one selection from the group consisting of: being formed in a region etched into the semiconductor, being formed by a process comprising vacuum deposition of said at least one material onto said semiconductor, being formed by a process comprising diffusion of said at least one material into said semiconductor, being formed by a process comprising ion-implantation of said at least one material into said semiconductor, and being comprised of said at least one material which forms a barrier height of approximately half the band-gap of the semiconductor.
17. An inverting single device with operating characteristics similar to dual device seriesed N and P-Channel MOSFETS CMOS systems comprising two oppositely facing electrically interconnected rectifying diodes in a semiconductor epi-layer or substrate characterized by a selection from the group consisting of: said semiconductor contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially equal doping levels; and said semiconductor contains both N and P-type metallurgical dopants essentially homogeneously distributed therein at substantially different doping levels; wherein a forward direction of rectification of each of said electrically interconnected rectifying diodes changes depending upon what type, N or P, be it metallurgically or field induced, is present in the semiconductor, said inverting single device with operating characteristics similar to dual device seriesed N and P-Channel MOSFETS CMOS systems further comprising gate means for field inducing effective doping type in said semiconductor, said gate means being set off from said semiconductor by insulator and each of said electrically interconnected rectifying diodes having an electrically non-interconnected terminal; and wherein, in use, the electrically non-interconnected terminals of the oppositely facing rectifying diodes are held at different voltages, and a voltage between said applied different voltages, inclusive, is monitored at the electrical interconnection between said two oppositely facing rectifying diodes, which monitored voltage responds inversely to applied gate voltage, said monitored voltage being essentially electrically isolated from said gate voltage and appearing at said electrical interconnection between said two oppositely facing rectifying diodes primarily through the rectifying diode which is caused to be forward biased as a result of semiconductor type metallurgically present or field induced by said applied gate voltage; the basis of operation of said inverting single device with operating characteristics similar to dual device seriesed N and P-Channel MOSFETS CMOS systems being that said two oppositely facing electrically interconnected rectifying diodes are each comprised of at least one material that forms a rectifying junction to semiconductor when it is either N or P-type by either metallurigical or field induced means, and the presence of at least partially compensated semiconductor which comprises both N and P-type carriers enables easy provision of N and P-type channel region forming carriers via gate voltage application effected field effect means.
18. An inverting single device as in claim 17, in which the semiconductor further comprises at least one region of parasitic current flow blocking material which prevents parasitic currents from flowing to or away therefrom through said at least one region of parasitic current flow blocking material, said at least one region of parasitic current flow blocking material being present at at least one selection from the group consisting of: physically a part of the inverting single device comprising an extention of the electrical interconnection between the two oppositely facing electrically interconnected rectifying diodes; and physically separate from the inverting single device; said at least one region of parasitic current flow blocking material forming rectifying junctions with both N and P-type metallurgical or field induced semiconductor.
19. An inverting single device as in claim 17, in which the semiconductor is silicon and the two oppositely facing electrically interconnected rectifying diodes comprise at least one material that forms a barrier height of approximately half the band-gap thereof with said silicon.
20. An inverting single device as in claim 17, which further comprises a voltage bias source connected across said electrically noninterconncted terminals of the oppositely facing rectifying diodes so that they are held at different voltages, each voltage being selected from the group consisting of: +V; −V; and Ground.
21. An inverting single device as in claim 17, in which at least one said electrically interconnected rectifying diode comprising rectifying junction is characterized by at least one selection from the group consisting of: being formed in a region etched into the semiconductor, being formed by a process comprising vacuum deposition of said at least one material onto said semiconductor, being formed by a process comprising diffusion of said at least one material into said semiconductor, being formed by a process comprising ion-implantation of said at least one material into said semiconductor, and being comprised of said at least one material which forms a barrier height of approximately half the band-gap of the semiconductor.
22. A semiconductor system as in claim 1 in which the semiconductor region is characterized as being at least one selection from the group consisting of: single crystal; amorphous; intermediate to single crystal and amorphous.
23. A semiconductor system as in claim 2 in which the semiconductor region is characterized as being at least one selection from the group consisting of: single crystal; amorphous; intermediate to single crystal and amorphous.
24. A semiconductor system as in claim 3 in which the semiconductor region is characterized as being at least one selection from the group consisting of: single crystal; amorphous; intermediate to single crystal and amorphous.
25. A semiconductor system as in claim 5 in which the semiconductor epi-layer or substrate is characterized as being at least one selection from the group consisting of: single crystal; amorphous; intermediate to single crystal and amorphous.
26. A semiconductor system as in claim 7 in which the semiconductor epi-layer or substrate is characterized as being at least one selection from the group consisting of: single crystal; amorphous; intermediate to single crystal and amorphous. semiconductor epi-layer or substrate
27. A semiconductor system as in claim 17 in which the semiconductor epi-layer or substrate is characterized as being at least one selection from the group consisting of: single crystal; amorphous; intermediate to single crystal and amorphous.

Parent Case Info

[0001] This Application is a CIP of patent applications and patent Ser. No. 08/250,906 filed May 31, 1994, (abandoned); Ser. No. 08/368,149 filed Dec. 29, 1994, (now U.S. Pat. No. 5,663,584); Ser. No. 08/578,336 filed Dec. 26, 1995, (now U.S. Pat. No. 5,760,449); Ser. No. 09/033,695 filed Mar. 03, 1998, (now U.S. Pat. No. 6,091,128); Ser. No. 09/246,871 filed Feb. 08, 1999) (now U.S. Pat. No. 6,628,636); Ser. No. 09/716,046 filed Nov. 20, 2000; (Allowed and Co-Pending); and claims Benefit of Provisional Applications Ser. No. 60/059,270 filed Sep. 18, 1997; Ser. No. 60/081,705 filed Apr. 15, 1998; Ser. No. 60/090,085 filed Jun. 20, 1998; Ser. No. 60/090,565 filed Jun. 24, 1998; Ser. No. 09/246,871 filed Feb. 08, 1999; & Ser. No. 60/196,580 filed Apr. 13, 2000; and also claims benefit of Disclosure Documents Nos. 402672 and 433236.

Government Interests

[0002] The invention in this application was conceived and developed in part under support provided by a grant from the Energy Related Inventions Program of the United States Federal Department of Energy, Contract No. DE-FG47-93R701314. The United States Government has certain rights in this invention.

Continuation in Parts (6)

	Number	Date	Country
Parent	08250906	May 1994	US
Child	10603334	Jun 2003	US
Parent	08368149	Dec 1994	US
Child	10603334	Jun 2003	US
Parent	08578336	Dec 1995	US
Child	10603334	Jun 2003	US
Parent	09033695	Mar 1998	US
Child	10603334	Jun 2003	US
Parent	09246871	Feb 1999	US
Child	10603334	Jun 2003	US
Parent	09716046	Nov 2000	US
Child	10603334	Jun 2003	US

Semiconductor devices in compensated semiconductor

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Abstract

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Claims

Parent Case Info

Government Interests

Continuation in Parts (6)