Semiconductor integrated circuit device and method of manufacturing the same

Abstract

A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 illustrates a circuit diagram of a static memory cell of a semiconductor integrated circuit device according to an embodiment of the invention;

FIG. 2 illustrates a layout of the semiconductor integrated circuit device according to an embodiment of the invention;

FIG. 3 illustrates a cross-sectional view taken along lines A-A′, B-B′, and C-C′ of FIG. 2; and

FIGS. 4A to 10 illustrate views of stages in a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the invention.

Claims

1. A semiconductor integrated circuit device, comprising: a semiconductor substrate;a static memory cell on the semiconductor substrate, the static memory cell including a plurality of pull-up transistors and pull-down transistors, which form a latch, and a plurality of pass transistors used to access the latch;a tensile stress film on the pull-down transistors; anda compressive stress film on the pass transistors.

2. The semiconductor integrated circuit device as claimed in claim 1, wherein each of the tensile and compressive stress films comprises an SiN or SiNx film.

3. The semiconductor integrated circuit device as claimed in claim 2, wherein a ratio of N—H bonding to Si—H bonding in the SiN or SiNx film that comprises the tensile stress film is smaller than the ratio in the SiN or SiNx film that comprises the compressive stress film.

4. The semiconductor integrated circuit device as claimed in claim 1, wherein a tensile stress of the tensile stress film is about 500 MPa or more.

5. The semiconductor integrated circuit device as claimed in claim 1, wherein an absolute value of a compressive stress of the compressive stress film is about 500 MPa or more.

6. The semiconductor integrated circuit device as claimed in claim 1, wherein each of the pull-down transistors and the pass transistors comprises an NMOS transistor.

7. The semiconductor integrated circuit device as claimed in claim 6, wherein an electron mobility of each pull-down transistor is higher than that of each pass transistor.

8. The semiconductor integrated circuit device as claimed in claim 1, wherein each of the pull-up transistors comprises a PMOS transistor.

9. The semiconductor integrated circuit device as claimed in claim 1, wherein the compressive stress film is additionally on the pull-up transistors.

10. A method of manufacturing a semiconductor integrated circuit device, comprising: providing a semiconductor substrate;forming a static memory cell on the semiconductor substrate, the static memory cell including a plurality of pull-up transistors and pull-down transistors, which form a latch, and a plurality of pass transistors used to access to the latch;forming a tensile stress film on the pull-down transistors; andforming a compressive stress film on the pass transistors.

11. The method as claimed in claim 10, wherein each of the tensile and compressive stress films comprises an SiN or SiNx film.

12. The method as claimed in claim 11, wherein a ratio of N—H bonding to Si—H bonding in the SiN or SiNx film that serves as the tensile stress film is smaller than the ratio in the SiN or SiNx film that serves as the compressive stress film.

13. The method as claimed in claim 10, wherein each of the pull-down transistors and the pass transistors comprises an NMOS transistor, and each of the pull-up transistors comprises a PMOS transistor.

14. The method as claimed in claim 13, wherein an electron mobility of each pull-down transistor is higher than that of each pass transistor.

15. The method as claimed in claim 10, wherein the tensile stress film is formed by a low pressure chemical vapor deposition process.

16. The method as claimed in claim 10, wherein the compressive stress film is formed by a pressure enhanced chemical vapor deposition process.

17. The method as claimed in claim 10, wherein the tensile stress film is formed under lower pressure than the compressive stress film.

18. The method as claimed in claim 10, wherein the tensile stress film is formed under higher temperature than the compressive stress film.

19. The method as claimed in claim 10, further comprising forming a compressive stress film on the pull-up transistors.

20. The method as claimed in claim 19, wherein the forming of the tensile stress film on the pull-down transistors and forming of the compressive stress film on the pull-up transistors and the pass transistors comprises: forming the tensile stress film on the surface of the semiconductor substrate;removing the tensile stress film from the pull-up transistors and the pass transistors;forming the compressive stress film on the surface of the semiconductor substrate; andremoving the compressive stress film from the pull-down transistors.

21. The method as claimed in claim 19, wherein the forming of the tensile stress film on the pull-down transistors and the forming of the compressive stress film on the pull-up transistors and the pass transistors comprises: forming the compressive stress film on the surface of the semiconductor substrate;removing the compressive stress film from the pull-down transistors;forming the tensile stress film on the surface of the semiconductor substrate; andremoving the tensile stress film from the pull-up transistors and the pass transistors.