Claims
- 1. A semiconductor memory device comprising:
a memory cell constituted by a single transistor of a first MISFET and formed on a memory cell forming region, said memory cell including a first gate insulating film, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, a control gate electrode of said first MISFET formed on said second gate insulating film, a first semiconductor region formed in a substrate and serving as a source region, and a second semiconductor region formed in said substrate and serving as a drain region; and a second MISFET for a peripheral circuit formed on a peripheral circuit forming region, said second MISFET including a third gate insulating film, a gate electrode of said second MISFET formed on said third gate insulating film, and a third semiconductor region formed in said substrate and serving as a drain region, wherein said third gate insulating film has a thickness greater than that of said first gate insulating film, wherein said first semiconductor region has an impurity concentration greater than that of said second semiconductor region and said third semiconductor region, wherein said first semiconductor region extends under said floating gate electrode such that a junction depth of said first semiconductor region into said substrate is greater than that of a junction depth of said second semiconductor region, wherein in a writing operation hot carriers generated in said substrate are injected in said floating gate electrode, and wherein in an erase operation said carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
- 2. A semiconductor memory device according to claim 1, wherein said second MISFET is included in a decoder circuit.
- 3. A method of manufacturing a semiconductor memory device including a memory cell constituted by a single transistor of a first MISFET, and a second MISFET for a peripheral circuit, comprising the steps of:
(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with (i) a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film, and with (ii) a third gate insulating film of said second MISFET formed on said peripheral circuit forming region, and a gate electrode of said second MISFET formed on said third gate insulating film, wherein said third gate insulating film has thickness greater than that of said first gate insulating film; (b) introducing arsenic into said memory cell forming region for forming a first semiconductor region in said substrate; (c) introducing arsenic into said memory cell forming region for forming a second semiconductor region in said substrate, wherein a dose introduced in said step (b) is higher than the dose in said step (c), wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said second semiconductor region; (d) introducing phosphorus into said peripheral circuit forming region for forming a third semiconductor region in said substrate, wherein a dose introduced in said step (b) is higher than the dose in said step (d); (e) after said steps (b), (c), and (d), forming first side wall spacers on both of opposing side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both of opposing side surfaces of said gate electrode of said second MISFET; and (f) after said step (e), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region of n-type conductivity in said substrate, wherein said third and fourth semiconductor regions together serve as a drain region of said second MISFET, wherein a junction depth of said first semiconductor region into said substrate is greater than that of a junction depth of said second semiconductor region, wherein carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
- 4. A method of manufacturing a semiconductor memory device according to claim 3,
wherein in a writing operation hot carriers generated in said substrate are injected in said floating gate electrode, and wherein in an erase operation said carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
- 5. A method of manufacturing a semiconductor memory device according to claim 3, wherein said impurity introduced in said step (f) is arsenic.
- 6. A method of manufacturing a semiconductor memory device including a memory cell constituted by a single transistor of a first MISFET, and a second MISFET for a peripheral circuit, comprising the steps of:
(a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with (i) a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film, and with (ii) a third gate insulating film of said second MISFET formed on said peripheral circuit forming region, and a gate electrode of said second MISFET formed on said third gate insulating film, wherein said third gate insulating film has thickness greater than that of said first gate insulating film; (b) introducing arsenic into said memory cell forming region for forming a first semiconductor region in said substrate; (c) introducing arsenic into said memory cell forming region for forming a second semiconductor region in said substrate, wherein a dose introduced in said step (b) is higher than the dose in said step (c), wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said second semiconductor region, wherein in said step (b) said arsenic is introduced by using a first mask film covering said second semiconductor region as a mask, wherein in said step (c) said arsenic is introduced by using a second mask film covering said first semiconductor region as a mask; (d) introducing phosphorus into said peripheral circuit forming region for forming a third semiconductor region in said substrate, wherein a dose introduced in said step (b) is higher than the dose in said step (d); (e) after said steps (b), (c), and (d), forming first side wall spacers on both of opposing side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both of opposing side surfaces of said gate electrode of said second MISFET; and (f) after said step (e), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region of n-type conductivity in said substrate, wherein said third and fourth semiconductor regions together serve as a drain region of said second MISFET, wherein a junction depth of said first semiconductor region into said substrate is greater than that of a junction depth of said second semiconductor region, and wherein carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
- 7. A method of manufacturing a semiconductor memory device according to claim 6,
wherein in a writing operation hot carriers generated in said substrate are injected in said floating gate electrode, and wherein in an erase operation said carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
- 8. A method of manufacturing a semiconductor memory device according to claim 6, wherein said impurity introduced in said step (f) is arsenic.
Priority Claims (1)
Number |
Date |
Country |
Kind |
63-284587 |
Nov 1988 |
JP |
|
Parent Case Info
[0001] This application is a continuation of U.S. application Ser. No. 09/873,451, filed Jun. 5, 2001, which, in turn, is a divisional of U.S. application Ser. No. 09/282,204, filed Mar. 31, 1999, now U.S. Pat. No. 6,255,690; which was a divisional of U.S. application Ser. No. 08/885,184, filed Jun. 30, 1997, now U.S. Pat. No. 5,904,518; which was a divisional of application Ser. No. 08/422,941, filed Apr. 17, 1995, now U.S. Pat. No. 5,656,839; which was a divisional of application Ser. No. 08/179,960, filed Jan. 11, 1994, now U. S. Pat. No. 5,407,853; which was a divisional of application Ser. No. 07/704,739, filed May 20, 1991, now U.S. Pat. No. 5,300,802; and which, in turn, was a continuation of application Ser. No. 07/433,983, filed Nov. 9, 1989, now abandoned; and the disclosures of all of which are incorporated herein by reference.
Divisions (5)
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Number |
Date |
Country |
Parent |
09282204 |
Mar 1999 |
US |
Child |
09873451 |
Jun 2001 |
US |
Parent |
08885184 |
Jun 1997 |
US |
Child |
09282204 |
Mar 1999 |
US |
Parent |
08422941 |
Apr 1995 |
US |
Child |
08885184 |
Jun 1997 |
US |
Parent |
08179960 |
Jan 1994 |
US |
Child |
08422941 |
Apr 1995 |
US |
Parent |
07704739 |
May 1991 |
US |
Child |
08179960 |
Jan 1994 |
US |
Continuations (2)
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Number |
Date |
Country |
Parent |
09873451 |
Jun 2001 |
US |
Child |
10164626 |
Jun 2002 |
US |
Parent |
07433983 |
Nov 1989 |
US |
Child |
07704739 |
May 1991 |
US |