The present disclosure relates to a semiconductor integrated circuit device provided with standard cells.
As a method for forming a semiconductor integrated circuit on a semiconductor substrate, a standard cell method is known. The standard cell method is a method in which basic units (e.g., inverters, latches, flipflops, and full adders) having specific logical functions are prepared in advance as standard cells, and a plurality of such standard cells are placed on a semiconductor substrate and connected through interconnects, thereby designing an LSI chip.
Also, for higher integration of a semiconductor integrated circuit device, it is proposed to use, for standard cells, buried power rails (BPRs) that are power lines laid in a buried interconnect layer, not power lines laid in a metal interconnect layer formed above transistors as conventionally done.
U.S. Patent Application Publication No. 2019/0080969 (FIG. 1E) discloses a configuration of a block constituted by standard cells, in which buried power rails are used and connected to sources of transistors and further connected to power lines laid in an upper interconnect layer.
Since buried power rails are buried in a substrate, they cannot be formed in regions where the sources, drains, and channels of transistors are present. Buried power rails however need to have a sufficient current supply capability for transistors. Also, in order to prevent manufacturing variations, transistors such as fin field effect transistors (FETs) and nanosheet FETs are restricted in their sizes and placement positions in microfabrication processes in some cases.
An objective of the present disclosure is providing a semiconductor integrated circuit device using buried power lines in which buried power lines having a sufficient line width can be laid without blocking regular placement of fin FETs.
According to one mode of the present disclosure, a semiconductor integrated circuit device includes a plurality of standard cells each having a fin field effect transistor (FET), wherein a plurality of fins constituting the fin FET extend in a first direction and placed on ones of virtual grid lines equally spaced in a second direction vertical to the first direction, the plurality of standard cells include a first standard cell and a second standard cell larger in size in the second direction than the first standard cell, the first standard cell includes a first buried power line extending in the first direction, the second standard cell includes a second buried power line extending in the first direction, the second buried power line being larger in size in the second direction than the first buried power line, and a center position of each of the first and second buried power lines in the second direction is on one of the virtual grid lines or at a center position between adjacent ones of the virtual grid lines.
According to the above mode, in a semiconductor integrated circuit device, a plurality of fins constituting a fin FET extend in the first direction and are placed on virtual grid lines equally spaced in the second direction. The first and second standard cells include buried power lines: the second standard cell larger in size in the second direction includes a buried power line larger in size in the second direction. With this, a sufficient current supply capability for fin FETs can be obtained. Also, the center positions of the buried power lines of the first and second standard cells in the second direction are on virtual grid lines or at the center positions between adjacent virtual grid lines. With this, buried power lines having a sufficient line width can be laid without blocking regular placement of fin FETs.
According to the present disclosure, in a semiconductor integrated circuit device using buried power lines, buried power lines having a sufficient line width can be laid without blocking regular placement of fin FETs.
An embodiment of the present disclosure will be described hereinafter with reference to the accompanying drawings. In the following embodiment, it is assumed that the semiconductor integrated circuit device includes a plurality of standard cells (hereinafter simply called cells as appropriate) and at least some of the standard cells include fin field effect transistors (FETs).
In the present disclosure, “VDD” and “VSS” refer to the power supply voltages or the power supplies themselves. Also, hereinafter, in the plan views such as
The inverter cells of
In the inverter cell of
The layout structures of the inverter cells shown in
In the inverter cell of
Two fins 21A extending in the X direction are provided in a p-type transistor region on an N-well, and two fins 22A extending in the X direction are provided in an n-type transistor region on a P-substrate. A gate interconnect 31A extends in the Y direction over the p-type transistor region and the n-type transistor region. As shown in
A local interconnect 41A extending in the Y direction is provided on left end portions of the fins 21A in the figure. The left end portions of the fins 21A are connected to the power line 11A through the local interconnect 41A and a via 51A. A local interconnect 42A extending in the Y direction is provided on left end portions of the fins 22A in the figure. The left end portions of the fins 22A are connected to the power line 12A through the local interconnect 42A and a via 52A. A local interconnect 43A extending in the Y direction is provided on right end portions of the fins 21A and 22A in the figure. The right end portions of the fins 21A and 22A are mutually connected through the local interconnect 43A.
A metal interconnect 61A into which an input A is given is connected to the gate interconnect 31A through a via. A metal interconnect 62A from which an output Y is output is connected to the local interconnect 43A through a via.
The inverter cell of
In the inverter cell of
Three fins 21B extending in the X direction are provided in a p-type transistor region on an N-well, and three fins 22B extending in the X direction are provided in an n-type transistor region on a P-substrate. A gate interconnect 31B extends in the Y direction over the p-type transistor region and the n-type transistor region. The gate interconnect 31B is formed to surround each of the fins 21B and 22B on three sides. The three fins 21B and the gate interconnect 31B constitute a fin FET P1, and the three fins 22B and the gate interconnect 31B constitute a fin FET N1.
A local interconnect 41B extending in the Y direction is provided on left end portions of the fins 21B in the figure. The left end portions of the fins 21B are connected to the power line 11B through the local interconnect 41B and a via 51B. A local interconnect 42B extending in the Y direction is provided on left end portions of the fins 22B in the figure. The left end portions of the fins 22B are connected to the power line 12B through the local interconnect 42B and a via 52B. A local interconnect 43B extending in the Y direction is provided on right end portions of the fins 21B and 22B in the figure. The right end portions of the fins 21B and 22B are mutually connected through the local interconnect 43B.
A metal interconnect 61B into which an input A is given is connected to the gate interconnect 31B through a via. A metal interconnect 62B from which an output Y is output is connected to the local interconnect 43B through a via.
The layout structures of the 2-input NAND cells shown in
In the 2-input NAND cell of
Two fins 23A extending in the X direction are provided in a p-type transistor region on an N-well, and two fins 24A extending in the X direction are provided in an n-type transistor region on a P-substrate. Gate interconnects 32A and 33A extend in the Y direction over the p-type transistor region and the n-type transistor region. The two fins 23A and each of the gate interconnects 32A and 33A constitute each of fin FETs P11 and P12. The two fins 24A and each of the gate interconnects 32A and 33A constitute each of fin FETs N11 and N12.
The 2-input NAND cell of
In the 2-input NAND cell of
Three fins 23B extending in the X direction are provided in a p-type transistor region on an N-well, and three fins 24B extending in the X direction are provided in an n-type transistor region on a P-substrate. Gate interconnects 32B and 33B extend in the Y direction over the p-type transistor region and the n-type transistor region. The three fins 23B and each of the gate interconnects 32B and 33B constitute each of fin FETs P11 and P12. The three fins 24B and each of the gate interconnects 32B and 33B constitute each of fin FETs N11 and N12.
The inverter cell of
Similarly, the inverter cell of
In the block A, a cell C1A is the inverter cell of
In the block B, a cell C1B is the inverter cell of
In the block A, in any adjacent cells in the Y direction, the distance between the centers of the fins of these cells closest to each other is 3×Pg. Also, the center position of each of the power lines 1A and 2A is at the center between adjacent virtual grid lines GL. It is therefore possible to secure the width Wb1 of the power lines 1A and 2A to a maximum extent. The width Wb1 of the power lines 1A and 2A is expressed by
Wb1=3×Pg−2×Sb−Wf.
In the block B, in any adjacent cells in the Y direction, the distance between the centers of the fins of these cells closest to each other is 4×Pg. Also, the center position of each of the power lines 1B and 2B is on a virtual grid line GL. It is therefore possible to secure the width Wb2 of the power lines 1B and 2B to a maximum extent. The width Wb2 of the power lines 1B and 2B is expressed by
Wb2=4×Pg−2×Sb−Wf.
That is, the width Wb2 of the power lines 1B and 2B is larger than the width Wb1 of the power lines 1A and 2A by Pg.
The cells constituting the block B have a larger number of fins than the cells constituting the block A. Therefore, the cells in the block B operate at a higher speed, but consume larger power, than the cells in the block A. However, since the power lines 1B and 2B are larger in width than the power lines 1A and 2A as described above, a sufficient current can be supplied to the cells in the block B.
Also, vias 51B and 52B for the power lines 11B and 12B of the inverter cell of
In the layout of
As described above, in the semiconductor integrated circuit device according to this embodiment, a plurality of fins constituting a fin FET extend in the X direction and are placed on virtual grid lines GL equally spaced in the Y direction. Standard cells include buried power lines: a standard cell larger in size in the Y direction includes a buried power line larger in size in the Y direction. With this, a sufficient current supply capability for fin FETs can be obtained. Also, the center position of each of the buried power lines of the standard cells in the Y direction is on a virtual grid line GL or at the center position between adjacent virtual grid lines GL. With this, buried power lines having a sufficient line width can be laid without blocking regular placement of fin FETs.
(Alteration)
In the inverter cell of
Four fins 21C extending in the X direction are provided in a p-type transistor region on an N-well, and four fins 22C extending in the X direction are provided in an n-type transistor region on a P-substrate. A gate interconnect 31C extends in the Y direction over the p-type transistor region and the n-type transistor region. The gate interconnect 31C is formed to surround each of the fins 21C and 22C on three sides. The four fins 21C and the gate interconnect 31C constitute a fin FET P1, and the four fins 22C and the gate interconnect 31C constitute a fin FET N1.
A local interconnect 41C extending in the Y direction is provided on left end portions of the fins 21C in the figure. The left end portions of the fins 21C are connected to the power line 11C through the local interconnect 41C and a via 51C. A local interconnect 42C extending in the Y direction is provided on left end portions of the fins 22C in the figure. The left end portions of the fins 22C are connected to the power line 12C through the local interconnect 42C and a via 52C. A local interconnect 43C extending in the Y direction is provided on right end portions of the fins 21C and 22C in the figure. The right end portions of the fins 21C and 22C are mutually connected through the local interconnect 43C.
A metal interconnect 61C into which an input A is given is connected to the gate interconnect 31C through a via. A metal interconnect 62C from which an output Y is output is connected to the local interconnect 43C through a via.
The inverter cell of
The width Wb3 of the power lines 11C and 12C is expressed by
Wb3=5×Pg−2×Sb−Wf.
That is, Wb3 is larger than Wb2 by Pg.
Also, vias 51C and 52C for the power lines 11C and 12C are even larger in size than the vias 51B and 52B for the power lines 11B and 12B of the inverter cell of
Therefore, the inverter cell of
While the semiconductor integrated circuit device was illustrated as including standard cells having fin FETs in the above description, the transistors of the standard cells are not limited to fin FETs. For example, the present disclosure is also applicable to a semiconductor integrated circuit device including standard cells having nanosheet FETs.
According to the present disclosure, in a semiconductor integrated circuit device using buried power lines, buried power lines having a sufficient line width are laid without blocking regular placement of fin FETs. The present disclosure is therefore useful for improving the integration degree and performance of system LSI, for example.
Number | Date | Country | Kind |
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2021-021737 | Feb 2021 | JP | national |
This is a continuation of International Application No. PCT/JP2022/002398 filed on Jan. 24, 2022, which claims priority to Japanese Patent Application No. 2021-021737 filed on Feb. 15, 2021. The entire disclosures of these applications are incorporated by reference herein.
Number | Date | Country | |
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Parent | PCT/JP2022/002398 | Jan 2022 | US |
Child | 18447032 | US |