BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
FIG. 1 is a block diagram showing a principal part of a NAND-type flash memory;
FIG. 2 is a view showing a layout of a memory cell array part;
FIG. 3 is a view showing a layout of a cell unit;
FIG. 4 is a view showing a circuit example of a memory cell array part;
FIG. 5 is a view showing a layout as a reference example;
FIG. 6 is a view showing a contact part between a word line and a connecting line;
FIG. 7 is a view showing a layout as a first embodiment;
FIG. 8 is a view showing a contact part between a word line and a connecting line;
FIG. 9 is a view showing a contact part between a word line and a connecting line;
FIG. 10 is a view showing a layout as a second embodiment;
FIG. 11 is a cross-sectional view along a line XI-XI of FIG. 10;
FIG. 12 is a cross-sectional view along a line XII-XII of FIG. 10;
FIG. 13 is a cross-sectional view along a line XIII-XIII of FIG. 10;
FIG. 14 is a view showing a layout as a third embodiment;
FIG. 15 is a view showing a layout as the third embodiment;
FIG. 16 is a view showing a layout as a fourth embodiment;
FIG. 17 is a view showing a layout as the fourth embodiment;
FIG. 18 is a view showing a cross-sectional shape of a contact part;
FIG. 19 is a view showing a cross-sectional shape of a contact part; and
FIG. 20 is a view showing a cross-sectional shape of a contact part.