This application relates generally to semiconductor manufacturing. In particular, this application relates to tools for analyzing and optimizing semiconductor design and performance.
A primary challenge of semiconductor manufacture is to determine the optimal transistor architecture within the ranges of key constraints that produces the best combination of optimal performance and manufacturability. Prototype transistor architectures are manufactured across varying geometries and processing values, and thousands of parameters, both physical and electrical, are collected for tens of locations across each of tens of wafers that form a run of experiment. A conventional manner of device analysis is to prepare a certain set of spreadsheets that specifies the data to be extracted from the database along with the application of statistics functions per material grouping and the charting of raw data. Such specification is fed into the scripts/spreadsheet macros that extract the required data, forming the material grouping, apply the statistics functions, and generate the charts. Certain custom analysis on the resulting data may be available, but requires a separate set of specifications and another round of execution. The conventional device analysis automation is deficient because it only achieves automation in a fragmentary manner such as only per module—e.g., MOS, Salicide, scribeline, etc.—where no integrated, uniform operation is supported and only at one level, mainly per material grouping (e.g., per wafer), leaving out the analysis that would be necessary to comprehend the entire data space. It does not support problematic trend investigation by bringing in new perspectives (for example the location sensitivity), and how related test structure and/or location is performing in other groups and other tests.
The following description can be better understood in light of Figures, in which:
Together with the following description, the Figures demonstrate and explain the principles of the methods, tools, systems, apparatus and methods described herein. In the Figures, the thickness and configuration of components may be exaggerated for clarity. The same reference numerals in different Figures represent the same component.
The following description supplies specific details in order to provide a thorough understanding. Nevertheless, the skilled artisan would understand that the methods, systems and devices described herein can be implemented and used without employing these specific details. Indeed, the devices, systems, and associated methods can be placed into practice by modifying the systems and methods and can be used in conjunction with any apparatus and techniques conventionally used in the industry.
In the early phases of technology development if semiconductors, the data being collected is prone to significant variations both within wafer and across wafers. In analyzing this large volume of data with significant variations, the following are critical and may be provided in a single solution according to some embodiments described herein: (a) faster info-turn; and (b) that the mode of variations is to be made explicitly visible, and presented in a manner conducive to the identification of the cause of such variations. In this context of device/transistor performance analysis, the problem of what the essential automation primitives are and how they should be put together as a software tool may be addressed by embodiments described herein. Specifically, the same embodiments allow a user to define the data analysis that spans across the multiple levels of granularity inherent to the subject, i.e., per die, material group, and aggregate, with an easy-to-use software package with a graphical user interface (GUI), yet in a declarative style, allowing the user to specify concisely what is being analyzed at each level of granularity and how the output is used in other analyses and graphical presentations.
Additionally, a user may efficiently form the data set that flows through the multiple levels, by extracting, filtering, and aligning a large volume of data, both electrical and physical parameters, then forming an analysis pipeline that encompasses multiple types of analyses for different modules (MOS, Salicide, scribeline, etc.), and for different business needs (e.g., transistor matching). A typical execution may involve over 250 sets of die-level parameters per polarity across a run of 25 wafers, resulting in over 100,000 raw data points per run, generating thousands of statistics function application instances and thousands of charts during the course.
Also, a user may exercise analytics that determine the value where the correlated indicator crosses a given threshold, which is made available across the multiple levels of analysis, regardless of the types of analyses conducted. A user may also exercise engineering judgment through the graphical results, identifying ad-hoc range of focus, carrying out further analysis on it.
Some functionality and features for software architecture, design and implementation that enable efficient transistor performance analysis across multiple levels of parameter granularity with interactive drill-down, drill-across capability, for use during semiconductor technology development that may be provided in some embodiments may include: drill-down on selected data points from the charts generated by the software, rendering those points in wafer maps and a radial chart, to enable the visualization of variation mode; linking of the data points selected on a single chart with those that share properties of interest across all other charts, to facilitate identifying correlated effects; highly modular, robust software architecture with uniform data model that is amenable to introduction of new analytics while insulating the analysis tool software logic from the variations of commercial-off-the-shelf (COS) components; template configuration user interface (UI) that allows for analysis that spans across the multiple levels—per die through the aggregate results based on material grouping—to be specified while making the output of one level, interspersed with the formulas thereof, usable in the next level via simple, uniform operations, e.g., drag-and-drop, copy-and-paste, and auto-fill; a single automated execution of the specification that produces analyses for multiple modules (e.g., MOS, Salicide, scribeline, etc.) and for various business needs (e.g., transistor matching); and integration of analytics across all the levels that determines the value where the correlated indicator crosses a given threshold.
Some embodiments may include analysis tools that include: highly modular, robust architecture to enable analysis across the multiple granularity of transistor performance data, i.e., per die, material group, and aggregate, that are inherent to the subject; GUI-based template module to specify the analysis across the multiple levels in a uniform set of operations where the output of one level is fed into the next; execution subsystem modules to execute the template specified with the GUI in a pipeline fashion based on uniform data representation including data extraction, analysis (statistics function application), and charting for visualization and interactive analysis; an analysis module that allows for integration of analytics called pass-fail analysis (
Turning to the figures,
Output/interaction module 140 may include vendor statistics module 142, which may allow for packaging and display of workbook spreadsheets and analysis charts presenting specific data points and data trends resulting from analysis tool 100. Additionally, output/interaction module 140 may include interface add-in module 144, event handler module 146, and framework abstraction layer module 148. Each module may be present as illustrated in
Analysis tool 100 may be provided such that it carefully insulates the device analysis from the underlying output/interaction module 140 as a vehicle to carry out the analysis.
In some embodiments, analysis tool 100 may provide pipeline 200 for analyzing and generating usable data as illustrated in
Data for each die on the wafer may be analyzed per die in single die analysis 214 and presented in die level data 242. Similarly, wafer level data may be analyzed per material grouping 220 and presented in wafer level data 246 and aggregate level data 248 for multiple wafers in a production process. Per material grouping 220, stat function application and charting may also be executed to organize and further analyze collected data. Aggregate grouping 230 may be presented in aggregate level data 248 and may also provide for custom analytics and charting as desired by one of ordinary skill in the art. Uniform data representation 240, including die level data 242, wafer level data 246, and aggregate level data 248 may then be used to general presentation sheets in presentation sheet generation step 250.
In some embodiments, data may be provided by analysis tool 100 through use of template maker UI module 126 by users, such as engineers and technicians to specify the analytics to be applied to E-Test data from database 116 and data extraction module 112, including statistics function application, chart generation, correlating to the FAB measurement data as well as split conditions. The particular analytics specification desired by a user may be provided in templates 128. Execution UI module 124 may provide for a Graphical User Interface (GUI) to allow a user to easily specify the material to be analyzed (lots and wafers), to organize the grouping thereof, and then to invoke the execution of the analysis and charting as specified in the template. Execution UI module 124 may interact with the execution engine 130, data manipulation module 132, and analysis/chart module 134, thru user interface control logic 122. The GUI may support the prefetching of parameter names to be rendered for analysis from the E-Test 116, FAB 114, and SPC 118 databases, based on any desired characterizing input, such as the ID of the lot that is measured for the target tests. The prefetched parameters may be placed in a graphically represented reservoir in the GUI, to be dragged and dropped graphically into particular analysis groupings, with ad-hoc filtering being applied.
In some embodiments, the data grouping to which certain analytics is applied may range from die level data 242, to wafer level data 246, to aggregate level data derived from the material group. The user may specify what needs to be done, while the GUI identifies the output variables from one level and presents them to be used further. The GUI may also support the notion of test family, where a series of E-Test parameters (and custom parameters such as constants and formulas) may be referenced by a single “family name”, which can be used in any parts of the template as if it were a single parameter name. This may provide a convenience in defining tens if not hundreds of kinds of charts, and conciseness in understanding what the analytics defined in the template is intended for.
Execution UI module 124 may be used to execute the analytics as specified in a selected template from templates 128, where the execution may form pipeline 200 based on uniform data representation 240, from data extraction 212, along with the augmentation thereof, through single die analysis 214, per material grouping 220, to aggregate grouping 120. During the processing, the custom formulas may also be evaluated based on the results at the given data level (i.e., die level data 242, wafer level data 246, aggregate level data 248), which in turn may become part of the input to the next level. Such analytics can in effect encompass multiple types of analyses and charting, arising from the multiple modules, e.g., MOS, Salicide, scribeline, etc., and the business needs, e.g., transistor matching.
In some embodiments, based on uniform data representation 242, analysis stages 212, 214, 220, 240 may be pipelined coherently, which may also enable straightforward introduction of new analytics, such as a “pass-fail” analysis example as shown in
In some embodiments, analysis tool 100 may provide drill-down capability. Drill-down capability may include the selection of data points to be made interactively in a performance data chart,
Similarly, analysis tool 100 may provide graph-linking capability, allowing the selection of data points to be made interactively, along with the choice of any desired property or properties of concern, in die-location or test structure or both, then have the data points that share the property of concern in all the charts presented with the marker/style also chosen interactively, illustrated in
In addition to any previously indicated modification, numerous other variations and alternative arrangements may be devised by those skilled in the art without departing from the spirit and scope of this description, and appended claims are intended to cover such modifications and arrangements. Thus, while the information has been described above with particularity and detail in connection with what is presently deemed to be the most practical and preferred aspects, it will be apparent to those of ordinary skill in the art that numerous modifications, including, but not limited to, form, function, manner of operation and use may be made without departing from the principles and concepts set forth herein. Also, as used herein, examples are meant to be illustrative only and should not be construed to be limiting in any manner.