Claims
- 1. A semiconductor memory wherein polling data and read data are selectively switched and output via an output buffer in an automatic algorithm operation of a write/erase, said memory:an address change detection unit for detecting a change of an address, and outputting an activated address change detection signal for a period until data sense operation of said read data ends after the change of the address is detected; a selection unit for selectively switching said polling data and said read data by a polling signal, and outputting its data to said output buffer; and a delay unit for inhibiting said polling signal from being transferred to said selection unit while said address change detection signal is activated.
- 2. The memory according to claim 1, wherein said delay unit delays said polling signal based on said activated address change detection signal in switching data to be transferred to said output buffer from said polling data to said read data by changing an address from a given block to another block in a suspend read performed in operating by said automatic algorithm.
- 3. The memory according to claim 1, wherein said selection unit outputs said polling data to said output buffer when said polling signal is activated and outputs said read data to said output buffer when said polling signal is not activated.
- 4. The memory according to claim 1, wherein said delay unit comprises first switching unit for switching said polling signal, and switching control unit for keeping said first switching unit off until said time at which data sense operations ends.
- 5. The memory according to claim 3, wherein said selection unit comprises first output unit for inputting the output of said delay unit and outputting said polling data, and second output unit for inputting an inverted output of said delay unit and outputting said read data.
- 6. An output signal control method in a semiconductor memory wherein polling data and read data are selectively switched and output via an output buffer in operating by an automatic algorithm of a write/erase, said method comprising the step of delaying a signal so as to inhibit a polling signal from being transferred to a selection unit, which switches said polling data and said read data by a polling signal and outputs its data to said output buffer, while a change of an address is detected, an address change detection signal is activated and output for a period until data sense operation ends after the change of the address is detected, and said address change detection signal is activated.
- 7. An output signal control circuit wherein polling data and read data are selectively switched and output via an output buffer in a semiconductor memory operating by an automatic algorithm of a write/erase, said circuit comprising:a selection unit for selectively switching said polling data and said read data by a polling signal, and outputting its data to said output buffer; and a delay unit for inhibiting said polling signal from being transferred to said selection unit while an address is changed, an address change detection signal which is activated for a period until data sense operation of said read data ends is input, and said address change detection signal is activated.
Priority Claims (1)
Number |
Date |
Country |
Kind |
10-371902 |
Dec 1998 |
JP |
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Parent Case Info
This application is a division of Ser. No. 09/452,718 filed Dec. 3, 1999 now U.S. Pat. No. 6,545,919.
US Referenced Citations (6)
Foreign Referenced Citations (4)
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1-173387 |
Jul 1989 |
JP |
5-54681 |
Mar 1993 |
JP |
8-63970 |
Mar 1996 |
JP |
328601 |
Mar 1998 |
TW |