Patent Application
20210082949
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-168051, filed on Sep. 17, 2019; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor memory device and a method for manufacturing the semiconductor memory device.
In a process for manufacturing a three-dimensional nonvolatile memory, a stacked body of conductive layers is formed by, for example, replacing a plurality of insulating layers with the conductive layers. For example, in order to pass a contact connecting the upper and lower structures of the stacked body, a part of the stacked body can be maintained as insulating layers without being replaced with conductive layers. At this time, it is desired to more easily inhibit the replacement with the conductive layers.
In general, according to one embodiment, a semiconductor memory device includes a substrate, a plurality of belt-like portions arranged abreast to each other above the substrate and extending in a first direction along the substrate, a first stacked body disposed between the belt-like portions and stacked a plurality of first conductive layers via a first insulating layer, a second stacked body disposed in a region in the first stacked body and stacked a plurality of second insulating layers via the first insulating layer, a first pillar extending in the first stacked body in a stacking direction of the first stacked body and forming a memory cell at an intersection with at least a part of the first conductive layers, and a plurality of second pillars extending in the stacking direction on both sides of the second stacked body facing the belt-like portions and arranged in the first direction, in which the second pillars each include a plate-like portion disposed at a height position of each of the first conductive layers, and the adjacent second pillars are connected to each other by the plate-like portion.
Exemplary embodiments of a semiconductor memory device and a method for manufacturing the semiconductor memory device will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments. In addition, constituent elements in the following embodiments include those that can be easily conceived by those skilled in the art or that are substantially the same.
(Configuration Example of Semiconductor Memory Device)
The substrate SB is, for example, a semiconductor substrate, such as a silicon substrate. On the substrate SB, the peripheral circuit CUA including a transistor TR and wiring is disposed.
The peripheral circuit CUA contributes to the operation of a memory cell to be described later. The peripheral circuit CUA is covered with an insulating layer 50. On the insulating layer 50, a source line SL is disposed. On the source line SL, a plurality of word lines WL is stacked.
In the word lines WL, a plurality of pillars PL penetrating the word lines WL in the stacking direction is disposed. At the intersections of the pillars PL and the word lines WL, a plurality of memory cells is formed. As a result, the memory portion MEM is configured by three-dimensionally disposing the memory cells.
In the memory portion MEM, a through contact region OXB including no word line WL is disposed. In the through contact region OXB, contacts C4 that connect the peripheral circuit CUA below the memory portion MEM to upper layer wiring and the like above the memory portion MEM are disposed.
The ends of the word lines WL are formed in a step shape. At the end of each word line WL, a contact CC that connects the word line WL to the upper layer wiring and the like is disposed. As a result, the word lines WL stacked in multiple layers can be led out individually.
Next, a detailed configuration example of the semiconductor memory device 1 is described with reference to
As illustrated in
On the source line SL, a stacked body LMa, in which word lines WL as conductive layers and insulating layers IL are alternately stacked in multiple layers, is disposed. On the stacked body LMa, a stacked body LMb, in which word lines WL as conductive layers and insulating layers IL are alternately stacked in multiple layers, is disposed via a bonding layer Bi. Each word line WL is, for example, a tungsten layer, a molybdenum layer, or the like. Each insulating layer IL and the bonding layer Bi are, for example, SiO2 layers or the like.
In the example of
On the source line SL, a plurality of contacts LI is disposed. Each contact LI penetrates an insulating layer 53 on the stacked body LMb and the stacked bodies LMa and LMb, and reaches the source line SL. By disposing the contacts LI each including a conductive layer 20 on the source line SL in this manner, the contacts LI function as, for example, source line contacts. The contacts LI are each configured in a belt-like shape extending in the X direction, and divide the stacked bodies LMa and LMb in the Y direction.
Each contact LI has an insulating layer 52 covering the sidewall of the divided stacked bodies LMa and LMb. The inside the insulating layer 52 of each contact LI is further filled with the conductive layer 20. The insulating layer 52 is, for example, a SiO2 layer or the like. The conductive layer 20 is, for example, a polysilicon layer, a tungsten layer, or the like. Note that, the stacked bodies LMa and LMb may be divided in the Y direction by belt-like insulating layers constituted only by, for example, SiO2 layers, instead of the contacts LI.
In the stacked bodies LMa and LMb between the two contacts LI, a plurality of pillars PL as first pillars is disposed. Each pillar PL penetrates the stacked bodies LMa and LMb and the bonding layer Bi and reaches the source line SL. Each pillar PL includes a bonding portion Bp in the bonding layer Bi.
Each pillar PL includes a memory layer ME, a channel layer CN, and a core layer CR in this order from the outer peripheral side of the pillar PL. The channel layer CN is also disposed at the bottom of the pillar PL, and the channel layer CN is connected to the source line SL at the lower end of the pillar PL. The memory layer ME is a stacked layer of, for example, a SiO2 layer/SiN layer/SiO2 layer, the channel layer CN is, for example, an amorphous silicon layer, a polysilicon layer, or the like, and the core layer CR is, for example, an SiO2 layer or the like.
On the stacked body LMb, the insulating layer 53 is disposed. On the insulating layer 53, an insulating layer 54 is disposed. The channel layer CN of each pillar PL is connected to upper layer wiring, such as a bit line or the like, by a plug CH penetrating the insulating layers 53 and 54. The conductive layer 20 of each contact LI is connected to the upper wiring by a plug VO penetrating the insulating layer 54.
With the above configuration, at respective intersections of the pillars PL and the word lines WL, a plurality of memory cells MC is formed. By applying a predetermined voltage from the word lines WL, accumulating charges in the memory cells MC, and the like, data is written in the memory cells MC. By applying a predetermined voltage from the word lines WL, data written in the memory cells MC is read.
As described above, the semiconductor memory device 1 is configured as a three-dimensional nonvolatile memory in which, for example, the memory cells MC are three-dimensionally disposed.
As illustrated in
The through contact region OXB as a second stacked body does not include word lines WL at the positions corresponding to the word lines WL of the stacked bodies LMa and LMb. Instead, the insulating layers NL, such as SiN layers or the like, are disposed, in the through contact region OXB, at the height positions corresponding to the word lines WL. That is, the through contact region OXB is configured by alternately stacking the insulating layers NL and the insulating layers IL in multiple layers.
For example, a plurality of contacts C4 are disposed in the through contact region OXB. Each contact C4 penetrates the insulating layer 53 above the through contact region OXB, the through contact region OXB, and the source line SL, and has a lower end connected to lower layer wiring and the like constituting the peripheral circuit CUA. Each contact C4 includes an insulating layer 55 on the outer peripheral side of the contact C4. The inside the insulating layer 55 of each contact C4 is filled with a conductive layer 30. The insulating layer 55 is, for example, a SiO2 layer or the like. The conductive layer 30 is, for example, a tungsten layer or the like. For example, the conductive layer 30 is connected to the upper layer wiring and the like through a plug VO penetrating the insulating layer 54.
On each side of the through contact region OXB in the Y direction, a replacement inhibition portion INr is disposed. The replacement inhibition portion INr includes a plurality of pillars HST as second pillars arranged in the X direction. Each pillar HST penetrates the boundary between the stacked bodies LMa and LMb and the through contact region OXB in the stacking direction of the stacked bodies LMa and LMb and reaches the source line SL. Each pillar HST includes a bonding portion Bt in the bonding layer Bi.
Each pillar HST includes dummy layers MEd, CNd, and CRd in this order from the outer peripheral side of the pillar HST. The dummy layer CNd is also disposed at the bottom of the pillar HST. The dummy layer MEd may be disposed at the bottom of the pillar HST. The dummy layer MEd is made of the same material as, for example, the memory layer ME. The dummy layer CNd is made of the same material as, for example, the channel layer CN. The dummy layer CRd is made of the same material as, for example, the core layer CR. Each pillar HST has a lower end connected to the source line SL similarly to each pillar PL and each columnar portion HR.
The diameter and pitch of the pillars HST at the height position of each insulating layer IL are substantially equal to the diameter and pitch of the pillars PL described above, for example.
A plurality of flat plate-like portions DSC protrudes from the side surface of each pillar HST at the height positions of the word lines WL. Each plate-like portion DSC has a shape formed by, for example, overlapping the end portion of a disk-like member extending concentrically with the side surface of each pillar HST with the end portions of the adjacent pillars HST in a top view.
As a result, the adjacent pillars HST are connected to each other by the end portions of the plate-like portions DSC at the same height position. In addition, the insulating layers IL are continuously disposed in the through contact region OXB and the stacked bodies LMa and LMb on both sides of the through contact region OXB through the adjacent pillars HST. In contrast, as to be described later, the word lines WL the replacement of which from the insulating layers NL is inhibited in the replacement inhibition portion INr each has an edge facing the pillars HST connected by the plate-like portion DSC and having a shape formed by connecting a plurality of arcs.
As long as the adjacent pillars HST are connected to each other, the degree of overlapping of the disk-like end portions is not limited to the example of
Each plate-like portion DSC is constituted by a part of the SiO2 layer/SiN layer/SiO2 layer constituting the dummy layer MEd. Specifically, each plate-like portion DSC is constituted by the SiO2 layer of the dummy layer MEd that is the closest layer to the side surface of each pillar HST.
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In the above configuration, by the pillars HST arranged in the X direction and the plate-like portions DSC protruding from the pillars HST and arranged in the height direction, the through contact region OXB is shielded from the region where the contacts LI are arranged. The pillars HST connected by the plate-like portions DSC inhibit replacement in the through contact region OXB in a process for replacing the insulating layers NL with the word lines WL, which is to be described later.
(Method for Manufacturing Semiconductor Memory Device)
Next, an example of a method for manufacturing the semiconductor memory device 1 according to the embodiment is described with reference to
Note that, it is assumed that the peripheral circuit CUA on the substrate SB has been formed at the time of
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Here, a condition with good step coverage is used for embedding into the pillars PL and HST. For this reason, when the dummy layer MEd is embedded in the hole HSTh, the gap formed by receding the insulating layers NL with heat phosphoric acid is also filled with a part of the dummy layer MEd. That is, the outermost SiO2 layer of the dummy layer MEd is formed on the lower surfaces of the insulating layers IL on the upper layer side and on the upper surfaces of the insulating layers IL on the lower layer side in the gap. The SiO2 layer on the upper and lower surfaces grows further, and the entire gap is filled with the SiO2 layer.
With the above, the pillars HST including the plate-like portions DSC protruding at the height positions of the insulating layers NL are formed.
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At this time, the columnar portions HR extending in the stacking direction of the stacked bodies LMag and LMbg and reaching the source line SL support the stacked bodies LMag and LMbg having the gaps. In addition, the pillars HST connected to each other by the plate-like portions DSC may also function as the support columns of the stacked bodies LMag and LMbg.
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The processing for replacing the sacrificial layers, such as the insulating layers NL or the like, with the word lines WL as illustrated in
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Then, the insulating layer 54 is formed on the insulating layer 53. A plug CH that penetrates the insulating layers 54 and 53 and is connected to the channel layer CN of each pillar PL is formed. A plug VO that penetrates the insulating layer 54 and is connected to the respective contacts LI and C4 is formed. Furthermore, the upper layer wiring thereof is formed.
With the above, the semiconductor memory device 1 according to the embodiment is manufactured.
In a process for manufacturing a semiconductor memory device, such as a three-dimensional nonvolatile memory, after a stacked body formed by stacking a plurality of insulating layers via a different insulating layer is processed to form pillars, the insulating layers are replaced with word lines. At this time, in order to pass a contact that connects the upper structure and the lower structure of the stacked body, the insulating layers may be left in a partial region of the stacked body. For this purpose, a configuration for inhibiting the replacement in the partial region is provided.
As a configuration for inhibiting the replacement, for example, when forming a slit for replacement, a slit parallel to this slit may be formed in the stacked body, and an SiO2 layer or the like may be formed on the inner wall of the slit to function as a slit for inhibiting replacement. However, it is required to form a slit for replacement without an SiO2 layer or the like on the inner wall and a slit for inhibiting replacement with an SiO2 layer or the like on the inner wall in parallel, and which can cause a large dimensional conversion difference between these slits.
According to the semiconductor memory device 1 in the embodiment, the pillars HST formed in parallel with the pillars PL are provided as a configuration for inhibiting replacement. Thus, it is possible to inhibit replacement in the through contact region OXB while the dimensional conversion difference of the slits ST is reduced.
According to the semiconductor memory device 1 in the embodiment, the plate-like portions DSC included in the pillars HST are embedded in parallel with the process for embedding the memory layers ME of the pillars PL. Thus, it is possible to embed the plate-like portions DSC under a condition with good step coverage, and to more reliably inhibit the replacement in the through contact region OXB.
According to the semiconductor memory device 1 in the embodiment, the pillars HST each have a lower end connected to the source line SL and are connected to each other by the plate-like portions DSC. Thus, it is possible for the pillars HST, in addition to the columnar portions HR, to support the stacked bodies LMag and LMbg in the replacement.
In the above embodiment, the diameter and pitch of the pillars HST at the height position of each insulating layer IL have been substantially equal to the diameter and pitch of the pillars PL. In addition, the plate-like portions DSC have protruded from the pillars HST, and the adjacent pillars HST have been connected to each other by the plate-like portions DSC. However, the diameter of each pillar HST at the height position of each insulating layer IL may be increased, and the protrusion amount of the plate-like portion DSC from each pillar HST may be reduced accordingly. Alternatively, the diameter of each pillar HST may be reduced, and the protrusion amount of the plate-like portion DSC from each pillar HST may be increased accordingly. Similarly, the pitch of the pillars HST may not be equal to the pitch of the pillars PL.
Next, a semiconductor memory device in Modified example 1 of the embodiment is described with reference to
As illustrated in
According to the semiconductor memory device in Modified example 1, the replacement inhibition portion INra surrounds the through contact region OXB. Thus, it is possible to prevent heat phosphoric acid from infiltrating from the X direction, and to more reliably inhibit the replacement in the through contact region OXB.
According to the semiconductor memory device in Modified example 1, the pillars HST arranged in the Y direction prevent heat phosphoric acid from infiltrating from the X direction. Thus, it is possible to shorten the arrangement of the pillars HST in the X direction by omitting the arrangement in the X direction of the excessive pillars HST for diverting the infiltration of the heat phosphoric acid in the through contact region OXB. Therefore, it is possible to reduce the region surrounded by the replacement inhibition portion INra.
According to the semiconductor memory device in Modified example 1, the replacement inhibition portion INra is constituted by a plurality of pillars HST. Thus, by variously changing the arrangement of the pillars HST, it is possible to form the replacement inhibition portion INra in a desired shape.
Next, a semiconductor memory device in Modified example 2 of the embodiment is described with reference to
As illustrated in
Each columnar portion RST penetrates the boundary between the stacked bodies LMa and LMb and the through contact region OXB in the stacking direction of the stacked bodies LMa and LMb and reaches the source line SL. Each columnar portion RST includes a bonding portion Brr in the bonding layer Bi. Each columnar portion RST is filled with an insulating layer made of the same material as the columnar portions HR, such as a SiO2 layer or the like.
The diameter and pitch of the columnar portions RST at the height position of each insulating layer IL are substantially equal to the diameter and pitch of the columnar portions HR, for example. However, the diameter of the columnar portions RST may not be equal to the diameter of the columnar portions HR as long as the adjacent columnar portions RST are connected to each other by plate-like portions DSCr to be described later. Similarly, the pitch of the columnar portions RST may not be equal to the pitch of the columnar portions HR.
A plurality of flat plate-like portions DSCr protrudes from the side surface of each columnar portion RST at the height positions of the word lines WL. Each plate-like portion DSCr is constituted by a part of the insulating layer with which the columnar portions RST are filled, and has a shape formed by, for example, overlapping the end portion of a disk-like member extending concentrically with the side surface of each columnar portion RST with the end portions of the adjacent columnar portions RST in a top view.
As a result, the adjacent columnar portions RST are connected to each other at the end portions of the plate-like portions DSCr at the same height position of the columnar portions RST. In addition, the insulating layers IL are continuously disposed in the through contact region OXB and the stacked bodies LMa and LMb on both sides of the through contact region OXB through the adjacent columnar portions RST.
Such the columnar portions RST are formed in parallel with the columnar portions HR. That is, the diameters of holes formed in parallel with the holes HRh for forming the columnar portions HR are expanded at the insulating layers NL to form the columnar portions RST having the plate-like portions DSCr.
In the above embodiment and Modified examples 1 and 2, the semiconductor memory device has included the stacked bodies LMa and LMb configured in two tiers, but is not limited thereto. The semiconductor memory device may include only one-tiered stacked body or three-or-more tiered stacked body.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2019-168051 | Sep 2019 | JP | national |
