Patent Application
20160307836
The present invention generally relates to a structure of a semiconductor device. In particular, the present invention relates to an improved semiconductor memory device bit line transistor structure with discrete bit line transistor gate.
As semiconductor technology continues to be reduced in scale, bit line to bit line pitch gets increasingly smaller in non-volatile memory structures. In traditional bit line transistor structures, bit line transistor (BLT) induced voltage drop (IR drop) and BLT may be inversely proportional, e.g. as the size of the bit cell is reduced the BLT IR drop increases. Further, as a result, smaller global bit line (GBL) spacing may cause process window issues, e.g. a smaller process window and increased coupling noise.
Embodiments of the present invention are therefore provided that may provide for a semiconductor memory device bit line transistor structure with discrete BLT gate. In an example embodiment, a semiconductor memory device is provided including a plurality of diffusion region pairs comprising first and second diffusion regions. Each of the diffusion regions comprise source and drain regions of a bit line transistor pair. The semiconductor memory device also includes a plurality of bit line transistor gate pairs in contact with the respective diffusion region pairs. A first bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of a first bit line transistor of the first diffusion region and the first bit lite transistor of the second diffusion region and a second bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of the second bit line transistor of the first diffusion region and a second bit line transistor of the second diffusion layer.
In an example embodiment of the semiconductor memory device, the bit line transistor gates comprise a discrete poly layer. In some example embodiments the semiconductor memory also includes a plurality of conducting line quartets, a first conducting line of the quartet is in electrical contact with a gate contact of the first bit line transistors of a first diffusion region pair, a second conducting line of the quartet is in electrical contact with a gate contact of the first bit line transistors of a second diffusion region pair, a third conducting line of the quartet is in electrical contact with a gate contact of the second bit line transistors of a first diffusion region pair, and a fourth conducting line of the quartet is in electrical contact with a gate contact of the second bit line transistors of the second diffusion region pairs.
In an example embodiment of the semiconductor memory device, the first and second bit line transistor of the respective diffusion regions comprises first and second drain regions and a common source region. In some example embodiments of the semiconductor memory device the first and second drain regions comprise a plurality of drain contacts. In an example embodiment of the semiconductor memory device, the common source region comprises a plurality of source contacts.
In some example embodiments of the semiconductor memory device, the first and second bit line transistor of the respective diffusion regions comprises first and second source regions and a common drain region. In an example embodiment of the semiconductor memory device, the first and second source regions comprise a plurality of source contacts. In some example embodiments of the semiconductor memory device, the common drain region comprises a plurality of drain contacts.
In an example embodiment of the semiconductor memory device, the discrete poly layer layers comprise a first end and a second end and the discrete poly layers further include a width projection at the first and second ends. In some example embodiments, the semiconductor memory device also includes at least one memory sector including four diffusion region pairs and four bit line transistor gate pairs. The four diffusion regions and four bit line transistor gate pairs are disposed in two columns and two rows.
In an example embodiment, the semiconductor memory device also includes a plurality of local bit lines (LBLs) having first and second ends and a first and second memory sector pair. The first memory sector is disposed on a first end and in electrical contact with the LBLs, and the second memory sector is disposed at a second end of the plurality of LBLs. In some example embodiments of the semiconductor memory device, the bit line transistors of the first memory sector comprise odd bit line transistors and the bit line transistors of the second memory sector comprise even bit line transistors.
Having thus described the invention in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:
Some embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. Indeed, various embodiments of the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements.
As used in the specification and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly indicates otherwise. For example, reference to “a memory device” includes a plurality of such memory devices.
Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation. All terms, including technical and scientific terms, as used herein, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs unless a term has been otherwise defined. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning as commonly understood by a person having ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure. Such commonly used terms will not be interpreted in an idealized or overly formal sense unless the disclosure herein expressly so defines otherwise.
The inventors have conceived of a semiconductor memory device bit line transistor structure (BLT) which includes discrete BLT gates. The discrete BTL gates may allow for a larger global bit line (GBL) processing window, a larger read window and a smaller BLT area. At a fixed spacing less GBL counts allows for wider line/space width, therefore during lithography inter-metal dielectric (IMD) filling may be improved. The larger read widow may additionally cause the BLT structure to have less GBL to GBL coupling noise over traditional BLT structures. The wider GBL spacing may also reduce the parasitic capacitance reducing cross-talk during read operations. The BLT structure may have comparable or in some instances better, e.g. smaller voltage drop (IR drop) for each BLT.
The BLT structure 100A configuration may include a narrow diffusion region 104 width, causing a smaller overall size of the BLT area, but may also include a significant IR drop.
The BLT structure 100B may have a wider diffusion width than BLT structure 100A causing a lower IR drop, but also has a significantly larger BLT structure area.
The BLT structure 100C may have a wider diffusion region width than BLT structure 100A, which may result in an IR drop comparable to the IR drop of BLT structure 100B. The BLT structure 100C may also have a smaller BLT area than BLT structure 100B.
The diffusion regions 216 may have drain contacts 220A and 220B of the BLTs disposed at each end of the diffusion region. A source contact 220C may be disposed in the relative center of the diffusion region 216, between the two drain regions. Although this specification make reference to a BLT structure in which each diffusion region has two drain regions and a common source region, one of ordinary skill in the art would understand that the BLT structure may alternatively have diffusion regions which include two source regions with a common drain region.
Discrete poly BLT gate pairs 218 may be in contact with the diffusion region 216. The BLT gate pairs 218 may be disposed on the diffusion regions, substantially in between the source region and drain region of the diffusion regions. The BLT gates 218 may include a gate contact 220D.
The semiconductor memory device BLT structure with discrete BLT gates may reduce the BLT area, reduce GBL to GBL coupling noise, allowing for an enlarged the read window and an enlarged GBL processing window. Additionally, the fabrication of the BLT structure with discrete BLT gates requires no additional mask layers or process flows and may reduce die costs due to the reduction of BLT area minimizing area overhead.
Many modifications and other embodiments of the inventions set forth herein will come to mind to one skilled in the art to which these inventions pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, although the foregoing descriptions and the associated drawings describe exemplary embodiments in the context of certain exemplary combinations of elements and/or functions, it should be appreciated that different combinations of elements and/or functions may be provided by alternative embodiments without departing from the scope of the appended claims. In this regard, for example, different combinations of elements and/or functions than those explicitly described above are also contemplated as may be set forth in some of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
