Semiconductor memory device

Abstract

HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1D are vertical cross-sectional views illustrating sequential process steps for forming an MIM capacitor structure according to a first embodiment of the present invention.

FIGS. 2A to 2D are vertical cross-sectional views illustrating sequential process steps for forming an MIM capacitor structure according to a second embodiment of the present invention.

FIG. 3 is a vertical cross-sectional view illustrating a process of manufacturing a DRAM according to a third embodiment of the present invention.

FIGS. 4A to 4C are vertical cross-sectional views illustrating sequential process steps for forming an MIM capacitor structure according to a fourth embodiment of the present invention.

FIG. 5 is a vertical cross-sectional view illustrating a process of manufacturing a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

Claims

1. A semiconductor memory device comprising: a substrate;a MOS transistor disposed on said substrate;a plug electrically connected to a source region or a drain region of said MOS transistor;a lower electrode of a metal material electrically connected to said plug;a dielectric layer disposed on said lower electrode and made up of either a solid solution of hafnium oxide and yttrium oxide or a layer stack of hafnium oxide and yttrium oxide; andan upper electrode of a metal material disposed on said dielectric layer;wherein said upper and lower electrodes and said dielectric layer form a capacitor; andwherein said dielectric layer is a film formed by chemical vapor deposition to a thickness of 5 nm-10 nm.

2. A semiconductor memory device comprising: a substrate;a MOS transistor disposed on said substrate;a plug electrically connected to a source region or a drain region of said MOS transistor;a lower electrode of a metal material electrically connected to said plug;a dielectric layer disposed on said lower electrode and made up of either a solid solution of hafnium oxide and lanthanum oxide or a layer stack of hafnium oxide and lanthanum oxide; andan upper electrode of a metal material disposed on said dielectric layer;wherein said upper and lower electrodes and said dielectric layer form a capacitor; andwherein said dielectric layer is a film formed by chemical vapor deposition to a thickness of 5 nm-10 nm.

3. A semiconductor memory device comprising: a substrate;a MOS transistor disposed on said substrate;a plug electrically connected to a source region or a drain region of said MOS transistor;a lower electrode of a metal material electrically connected to said plug;a dielectric layer disposed on said lower electrode and made up of either a solid solution of zirconium oxide and yttrium oxide or a layer stack of zirconium oxide and yttrium oxide; andan upper electrode of a metal material disposed on said dielectric layer;wherein said upper and lower electrodes and said dielectric layer form a capacitor; andwherein said dielectric layer is a film formed by chemical vapor deposition to a thickness of 5 nm-10 nm.

4. A semiconductor memory device comprising: a substrate;a MOS transistor disposed on said substrate;a plug electrically connected to a source region or a drain region of said MOS transistor;a lower electrode of a metal material electrically connected to said plug;a dielectric layer disposed on said lower electrode and made up of either a solid solution of zirconium oxide and lanthanum oxide or a layer stack of zirconium oxide and lanthanum oxide; andan upper electrode of a metal material disposed on said dielectric layer;wherein said upper and lower electrodes and said dielectric layer form a capacitor; andwherein said dielectric layer is a film formed by chemical vapor deposition to a thickness of 5 nm-10 nm.