Claims
- 1. A method of accessing a semiconductor memory device which operates in synchronism with a clock signal, comprising the steps of:inputting a control information segment including a control signal and address signals in synchronism with the clock signal; designating memory cells in a memory cell array by decoding the address signals in response to transition of the control signal; receiving a plurality of data items stored in the designated memory cells of addresses which correspond to the address signals, in synchronism with the clock signal and a predetermined number of cycles of the clock signal after the transition of the control signal; and outputting a plurality of data items stored in the memory cells and storing a plurality of input data items into the memory cells, in synchronism with the clock signal and two cycles or more of the clock signal after the transition of the control signal.
- 2. A method of accessing a semiconductor memory device according to claim 1, wherein the control signal includes a chip enable signal.
- 3. A method of accessing a semiconductor memory device according to claim 1, wherein the address signals include a row address signal and a column address signal.
- 4. A method of accessing a semiconductor memory device according to claim 3, wherein a first timing of fetching the row address signal, a second timing of fetching the column address signal and a third timing of inputting/outputting the data segments are determined each to correspond to a predetermined number of cycles of the clock signal.
- 5. A method of accessing a semiconductor memory device which operates in synchronism with a clock signal, comprising the steps of:inputting a control information segment including first and second control signals and address signals in synchronism with the clock signal; designating memory cells in a memory cell array by decoding the address signals in response to transition of the first control signal; receiving, in response to a state of the second control signal and in synchronism with the clock signal, a plurality of data items stored in the designated memory cells of addresses which correspond to the address signals a predetermined number of cycles of the clock signal after the transition of the first control signal; and outputting a plurality of data items stored in the memory cells and storing a plurality of input data items into the memory cells, in synchronism with the clock signal and two cycles or more of the clock signal after the transition of the first control signal.
- 6. A method of accessing a semiconductor memory device according to claim 5, wherein the first control signal includes a chip enable signal.
- 7. A method of accessing a semiconductor memory device according to claim 5, wherein the second control signal includes a read/write signal.
- 8. A method of accessing a semiconductor memory device according to claim 5, wherein an output enable signal determines whether or not a plurality of data items stored in the memory cells are to be externally output in synchronism with the clock signal.
- 9. A method of accessing a semiconductor memory device according to claim 5, wherein the address signals include a row address signal and a column address signal.
- 10. A method of accessing a semiconductor memory device according to claim 9, wherein a first timing of fetching the row address signal, a second timing of fetching the column address signal and a third timing of inputting/outputting the data segments are determined each to correspond to a predetermined number of cycles of the clock signal.
Priority Claims (2)
Number |
Date |
Country |
Kind |
P02-273170 |
Oct 1990 |
JP |
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P03-255354 |
Oct 1991 |
JP |
|
Parent Case Info
This application is a divisional of application Ser. No. 09/433,338, filed Nov. 4, 1999, now U.S. Pat. No. 6,249,481 which in turn is a divisional of application Ser. No. 09/236,832, filed Jan. 25, 1999, now U.S. Pat. No. 5,995,442 which is in turn a divisional of application Ser. No. 09/017,948, filed Feb. 3, 1998, now U.S. Pat. No. 5,926,436 which is in turn a continuation of application Ser. No. 08/779,902, filed Jan. 7, 1997, now U.S. Pat. No. 5,740,122 which is in turn a continuation of application Ser. No. 08/463,394, filed Jun. 5, 1995, now U.S. Pat. No. 5,612,925 which is a continuation of application Ser. No. 08/223,222, filed Apr. 5, 1994, now U.S. Pat. No. 5,500,829 which is in turn a divisional of application Ser. No. 07/775,602, filed Oct. 15, 1991, now U.S. Pat. No. 5,313,437.
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Continuations (3)
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Date |
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Parent |
08/779902 |
Jan 1997 |
US |
Child |
09/017948 |
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US |
Parent |
08/463394 |
Jun 1995 |
US |
Child |
08/779902 |
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US |
Parent |
08/223222 |
Apr 1994 |
US |
Child |
08/463394 |
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US |